KR20080001191A - Tft array substrate and method for manufacturing the same - Google Patents

Abstract

A thin film transistor array substrate and a manufacturing method thereof are provided to form a high-capacity storage capacitor by using only a passivation as an insulation layer of the capacitor. A substrate(100) having a first region is prepared, and then a gate electrode(G) and a common wiring are formed on the substrate. A gate insulation layer(53) is formed on the entire surface of the substrate, and then is patterned to form a common wiring contact hole exposing the common wiring. A semiconductor layer(54) is formed on the gate insulation layer, and then source/drain electrodes(S,D) are formed on the semiconductor layer while forming a dummy metal layer. A passivation(57) is formed on the entire surface comprising the source/drain electrodes, and then is patterned to form a pixel electrode contact hole. A pixel electrode(59a) is formed to be connected to the drain electrode via the pixel electrode contact hole.

Description

Thin film transistor array substrate and its manufacturing method {TFT array substrate and Method for manufacturing the same}

Figure 1a is a plan view showing a typical thin film transistor array substrate

1B is an enlarged view of a pixel region of a thin film transistor array substrate.

1C is a cross-sectional view taken along line AA ′ of the active region of FIG. 1B, a cross-sectional view of the gate pad portion of FIG. 1A, and a cross-sectional view of the data pad portion of the active region of FIG.

2 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to the present invention.

<Description of the code | symbol about the principal part of drawing>

100: substrate G: gate electrode

D: drain electrode S: source electrode

48: dummy metal layer 56: common wiring

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same.

BACKGROUND ART Liquid crystal display devices, which have recently been in the spotlight as flat panel displays, have been actively researched due to their high contrast ratio, suitable for gradation display or moving image display, and low power consumption.

In particular, it can be manufactured with a thin thickness, so it can be used as an ultra-thin display device such as a wall-mounted TV, and it is also used as a display of a battery-powered notebook computer because it is light in weight and consumes significantly less than a CRT CRT. It is attracting attention as a display device.

Generally, a liquid crystal display device includes a thin film array substrate on which a thin film transistor (TFT) and a pixel electrode are formed in each pixel area defined by a gate wiring and a data wiring, and a color filter array on which a color filter layer and a common electrode are formed. The substrates are arranged to face each other, and a liquid crystal having dielectric anisotropy is formed therebetween, and switching the TFTs added to the hundreds of thousands of pixels through the pixel selection address wiring to switch the voltage to the corresponding pixels. It is driven in such a way that it is applied.

At this time, the color filter array substrate and the thin film array substrate are bonded by a sealing material, and a driving circuit on a printed circuit board (PCB) is connected to the thin film transistor array substrate through a tape carrier package (TCP).

Specifically, as shown in FIG. 1A, the thin film transistor array substrate 11 is divided into an active region 60 and a pad portion region 61, and a plurality of thin film transistor array substrates 11 are formed on the glass substrate of the active region 60. The gate line 12 and the data line 15 cross each other, and the pixel region P is defined by the gate line 12 and the data line 15, and the gate line 10 and the data line 12 are formed. A thin film transistor (TFT: Thin Film Transistor, not shown) is formed as a switching element at an intersection point.

The pad region 61 includes a plurality of gate pads 22 extending from the gate lines 12 to apply gate driving signals of gate drivers to the gate lines 12, and data signals of the data driver. A plurality of data pads 25 extending from the data wires 15 are formed to apply to the respective data wires 15 to interface electrical signals with external driving circuits, respectively.

FIG. 1B is an enlarged view of the pixel region P of the thin film transistor array substrate illustrated in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line AA ′ of the active region of FIG. 1B, and the gate pad part 22 of FIG. And a cross-sectional view of the data pad unit 25 are described below.

1B and 1C, by depositing and patterning a conductive material such as a metal layer on the substrate 10, gate lines 12 and gates protruding from the gate lines 12 arranged at regular intervals in the active region. A common electrode 16 parallel to the electrode G, the gate line 12, and a common electrode 18 protruding from the common line 16 into the pixel region are formed, and a gate pad 12p is formed in the gate pad part. do.

Subsequently, a gate insulating layer 13 is formed on the entire surface of the substrate 10 on which the gate electrode G, the common electrode 18, and the gate pad 12p are formed, and a thin film is formed in the active region in which the gate insulating layer 13 is formed. The semiconductor layer 14 used as the channel layer of the transistor is formed.

Thereafter, a conductive material such as a metal layer is deposited and patterned on the gate insulating layer including the semiconductor layer 14 to form a source S and a drain D on the semiconductor layer 14 in the active region, and The data pad 14p is formed.

Next, a passivation layer 17 is formed on the entire surface of the substrate on which the source S, the drain D, and the data pad 14p are formed, and the passivation layer 17 is patterned to expose the drain electrode D in the active region. A contact hole, a contact hole exposing the gate pad 12p and a contact hole exposing the data pad 14p are formed.

A metal film such as a transparent conductive film is formed on the substrate on which the contact hole is formed, and then patterned to form a first contact plug connected to the pixel electrode 19a and the gate pad 12p connected to the drain electrode D in the active region. A second contact plug 19c connected to the 19b) and the data pad 14p is formed.

On the other hand, the storage capacitor Cst for maintaining the signal voltage applied to the liquid crystal overlaps a part of the common wiring 16 adjacent to the pixel electrode 19a with the gate insulating layer 13 and the passivation layer 17 therebetween. It is formed by.

However, the storage capacitor Cst1 is formed by the overlap between the neighboring common wiring 16 and the pixel electrode 19a. In the related art, the area between the pixel electrode and the common wiring is large, resulting in a decrease in the aperture ratio.

There is a method of reducing the width of the common wiring in order to prevent the reduction of the aperture ratio. However, when the width of the common wiring is reduced, desired capacitance cannot be obtained. Therefore, there is a limit in reducing the width of the common wiring.

Accordingly, the present invention for solving the above problems is to provide a thin film transistor array substrate and a method of manufacturing the same to form a large-capacity storage capacitor without loss of an opening.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate, including: providing a substrate having a first region, forming a gate electrode and a common wiring on the substrate, and including the gate electrode Forming a gate insulating film on the entire surface of the substrate; forming a common wiring contact hole exposing the common wiring by patterning the gate insulating film; forming a semiconductor layer on the gate insulating film over the gate electrode; Simultaneously forming a source / drain electrode on the semiconductor layer and filling the common wiring contact hole to form a dummy metal layer; forming a protective layer on the entire surface including the source / drain electrode; and patterning the protective layer to form a pixel electrode contact. Forming a hole; the drain electrode through the pixel electrode contact hole And forming a pixel electrode connected.

The dummy metal layer is connected to the common wiring to form a lower electrode of the storage capacitor.

The pixel electrode in an area overlapping the lower electrode of the storage capacitor is an upper electrode of the storage capacitor.

The first region is an active region, and the substrate including the first region further includes a second region including a gate pad portion and a data pad portion.

The method may further include forming a gate pad in the gate pad part when the gate wiring, the gate electrode, and the common wiring are formed, and forming a data pad in the data pad part when the source / drain electrode and the dummy metal layer are formed.

The method may further include forming first and second pad open regions in the gate pad part and the data pad part, respectively, when the pixel electrode contact hole is formed.

The method may further include forming first and second transparent conductive layers on the gate pad part and the data pad part to connect the gate pad and the data pad to the gate pad part and the data pad part, respectively, when the pixel electrode is formed.

The thin film transistor array substrate of the present invention for achieving the above object is a substrate having a first region, a common wiring and a gate electrode spaced apart on the first substrate, on the first substrate except the upper portion of the common wiring A gate insulating layer formed on the gate insulating layer overlapping the gate electrode, a source electrode and a drain electrode formed on the semiconductor layer to be spaced apart from each other, a dummy metal layer in contact with the common wiring, the source / drain electrode, and A protective film formed on the dummy metal layer, and a pixel electrode electrically connected to the drain electrode.

The dummy metal layer in contact with the common wiring is a lower electrode of the storage capacitor.

The pixel electrode overlapping the lower electrode of the storage capacitor is an upper electrode of the storage capacitor, and the first region is an active region.

The substrate having the first region may further include a second region including a gate pad portion and a data pad portion, and the gate pad portion may include a gate pad formed on the substrate, a gate insulating film and a protective layer formed on the gate pad, and the gate. A first transparent conductive film in contact with the pad is further provided.

The data pad part may further include a gate insulating film formed on the substrate, a data pad formed on the gate insulating film, a protective film formed on the data pad, and a second transparent conductive film contacting the data pad.

An embodiment of a liquid crystal display device and a method of manufacturing the same according to the present invention having the above characteristics will be described with reference to the accompanying drawings.

2 is a plan view illustrating a thin film transistor array substrate of a liquid crystal display according to the present invention.

As shown in FIG. 2, the thin film transistor array substrate of the liquid crystal display according to the present invention may be disposed to cross each other so that the gate wiring 52 and the data wiring 55 define a pixel region, and the gate wiring 52 and the gate wiring 52. The thin film transistor T formed at the intersection region of the data line 55, the common line 56 parallel to the gate line 52, and the common electrode protruding from the common line 56 to the pixel region P. A storage capacitor Cst2 formed by an overlap between the pixel electrode 59a disposed in the pixel region adjacent to the common electrode 58 and the common wiring 56 and the pixel electrode 59a. It is configured to include.

The thin film transistor T includes a source electrode S branched from the data line 12, a gate electrode G branched from the gate line 10, and an island-shaped drain electrode D, respectively.

Here, the common wiring 56 of the neighboring common wiring 56 and the pixel electrode 59a constituting the storage capacitor Cst2 is connected to the dummy metal layer 48 of FIG. 3E to form a lower electrode of the storage capacitor. By forming, a capacitor of high capacity can be formed without changing the aperture ratio.

That is, the storage capacitor Cst2 is formed by overlapping the common wiring 56 and the pixel electrode 59a connected to the dummy metal layer 48 of FIG. 3E with the passivation layer interposed therebetween, so that only the passivation layer is used as the insulating layer of the storage capacitor. Since this is used, it is possible to form a storage capacitor with a higher capacity than when using the gate insulating film and the protective film as the insulating layer of the storage capacitor in the prior art.

3E is a cross-sectional view illustrating a thin film transistor array substrate of a liquid crystal display according to the present invention.

For reference, a cross-sectional view of the thin film transistor array substrate illustrated in FIG. 3E includes an active region (cross-sectional view taken along line B-B 'of FIG. 2) defined as a region in which a storage capacitor is formed and a region in which a thin film transistor is formed. The gate pad portion region and the data pad portion region are shown briefly.

As shown in FIG. 3E, a thin film transistor gate electrode G is formed in an active region on the substrate 100 to be used as a thin film transistor array substrate, and a gate insulating film is formed on the gate electrode G. 53 and a semiconductor layer 54 are formed, and a source electrode S and a drain electrode D are formed on the semiconductor layer 54 so as to be spaced apart from each other so as to overlap the gate electrode, and the source / drain is formed. A passivation layer 57 is formed on the substrate including the electrodes S and D, and a pixel electrode 59a penetrating the passivation layer to contact the drain electrode D is formed.

In addition, a common wiring 56 used as a lower electrode for the storage capacitor is formed at a predetermined interval from the gate electrode G in an area where the storage capacitor is formed among the active regions on the substrate 100 to be used as the thin film transistor array substrate. A gate insulating film 53 is formed on the entire surface of the substrate including the common wiring 56, and a dummy metal layer 48 penetrating the gate insulating film 53 and contacting the common wiring 56 is formed. The passivation layer 57 is formed on the entire surface of the substrate including the dummy metal layer 48, and the pixel electrode 59a is formed on the passivation layer 57 so as to overlap the dummy metal layer 48 and the common wiring 56.

A gate pad portion 52p is formed in the gate pad region on the substrate on which the thin film transistor array is formed, and a gate insulating film 53 and a protective film 57 are formed on the gate pad portion 52p, and the protective film 57 ) And a first contact plug 59b penetrating through the gate insulating layer 53 and in contact with the gate pad portion 52p.

A gate insulating film 53 is formed in the data pad region on the substrate where the thin film transistor array is formed, a data pad portion 54p is formed on the gate insulating film 57, and a protective film is formed on the data pad portion 52p. A 57 is formed and includes a second contact plug 59c penetrating through the passivation layer 57 and in contact with the data pad portion 54p.

According to the exemplary embodiment of the present invention, the storage capacitor Cst2 is formed by overlapping the common wiring 56 and the pixel electrode 59a connected to the dummy metal layer 48 with the passivation layer 57 interposed therebetween. Since only the protective film 57 is used as the insulating layer of the lodge capacitor, it is possible to form a storage capacitor having a higher capacity than when using the gate insulating film and the protective film as the insulating layer of the storage capacitor in the prior art.

Such a method of manufacturing a thin film transistor of a liquid crystal display according to an exemplary embodiment of the present invention is illustrated in FIGS. 3A to 3E, which will be described below with reference to the drawings.

As shown in FIG. 3A, a metal having low resistivity, such as Al, Cr, Cu, Mo, or Al alloy, is deposited on the first substrate 100 by sputtering, followed by a patterning process using a photolithography process. In the active region, a gate wiring (not shown in FIG. 3A but shown as 52 in FIG. 2), a gate electrode G, and a common wiring 56 are formed at a predetermined distance from the gate electrode G. A gate pad 52p is formed in the pad portion. Subsequently, silicon oxide (SiOx) or silicon nitride (SiNx), which is an insulating material, is deposited on the entire surface of the substrate including the gate electrode G by using a plasma enhanced chemical vapor deposition method to form a gate insulating layer 53.

3B, a patterning process using a photolithography process or the like is performed on the gate insulating layer 53 to form a contact hole 49 exposing the common wiring 56 formed in the active region. .

Next, as shown in FIG. 3C, after depositing amorphous silicon (a-Si: H) on the gate insulating film 53 on which the contact hole 49 is formed, a plasma chemical vapor deposition method is used. The semiconductor layer 54 is formed on the gate insulating layer 53 overlapping with the gate electrode G by performing a patterning process using a photolithography process or the like.

Subsequently, a metal having low resistivity, such as Al, Cr, Cu, Mo, or Al alloy, is deposited on the gate insulating layer 53 on which the semiconductor layer 54 is formed by sputtering, and then a patterning process using a photolithography process is performed. Thus, the source electrode S / drain electrode D overlapping the gate electrode G is formed in the active region, and the dummy metal layer 48 is buried in the contact hole 49 exposing the common wiring 56. The data pad portion 54p is formed in the data pad region.

Meanwhile, the common wiring 56 and the dummy metal layer 48 are connected through the contact hole 49 formed through the gate insulating layer 53, which becomes a lower electrode of the storage capacitor Cst2, and the gate electrode ( G), the laminated film of the semiconductor layer 54 and the source / drain electrodes S and D becomes a thin film transistor T. As shown in FIG.

Subsequently, as illustrated in FIG. 3D, an insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface including the thin film transistor T to form a protective film 57.

Finally, as shown in FIG. 3E, a patterning process using a photolithography process or the like is performed on the passivation layer 57 to form a contact hole in the active region, and simultaneously First and second pad open regions are formed, respectively. Subsequently, a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), is deposited and patterned on the entire surface of the substrate where the contact hole and the pad open area are formed, thereby forming the pixel electrode 59a and the first and second transparent conductive films. (59b, 59c) are formed.

The pixel electrode 59a is connected to the drain electrode D through the contact hole, and the first and second transparent conductive layers 59b and 59c are connected to the gate through the first and second pad open regions. This step is completed by connecting to the pad 52p and the data pad 54p, respectively.

In addition, the pixel electrode 59a overlaps the lower electrode of the storage capacitor including the common wiring 56 and the dummy metal layer 48. The pixel electrode 59a becomes the upper electrode of the storage capacitor.

As such, the storage capacitor Cst2 is formed of an insulating layer of the storage capacitor formed of the passivation layer 57, and a lower electrode and a pixel electrode 59a of the storage capacitor formed of the dummy metal layer 48 and the common wiring 56. The upper electrode of the storage capacitor is formed.

Therefore, in the storage capacitor of the present invention, since only the protective film 57 is used as the insulating layer of the storage capacitor, a storage capacitor having a higher capacity than the gate insulating film and the protective film can be formed as the insulating layer of the storage capacitor in the prior art. It becomes possible. In other words, since the capacity of the storage capacitor is inversely proportional to the thickness of the insulating layer of the storage capacitor, the insulating layer thickness of the storage capacitor of the present invention is reduced than the thickness of the insulating layer of the conventional storage capacitor, so that the storage capacitor of the present invention The amount will increase.

The liquid crystal display of the present invention can form a large capacity storage capacitor without changing the aperture ratio.

According to the above-described thin film transistor array substrate and the manufacturing method thereof, since only the protective film is used as the insulating layer of the storage capacitor, the gate insulating film and the protective film are used as the insulating layer of the storage capacitor. There is an effect that can form a large storage capacitor without changing the regulation.

Claims (15)

Providing a substrate having a first region; Forming a gate electrode and a common wiring on the substrate; Forming a gate insulating film on the entire surface including the gate electrode; Patterning the gate insulating layer to form a common wiring contact hole exposing the common wiring; Forming a semiconductor layer on the gate insulating layer on the gate electrode; Forming a dummy metal layer by filling a source / drain electrode on the semiconductor layer on the gate insulating layer and simultaneously filling the common wiring contact hole; Forming a protective film on the entire surface including the source / drain electrodes; Patterning the passivation layer to form a pixel electrode contact hole; And forming a pixel electrode connected to the drain electrode through the pixel electrode contact hole. The method of claim 1, wherein the dummy metal layer And a lower electrode of the storage capacitor connected to the common wiring. The method of claim 2, And the pixel electrode in the region overlapping the lower electrode of the storage capacitor is an upper electrode of the storage capacitor. The method of claim 1, wherein the first region is A method of manufacturing a thin film transistor array substrate, characterized in that it is an active region. The substrate of claim 1, wherein the substrate is provided with the first region. And a second region having a gate pad portion and a data pad portion. The method according to claim 1 or 5, And forming a gate pad in the gate pad part when the gate wiring, the gate electrode and the common wiring are formed, and forming a data pad in the data pad part when the source / drain electrode and the dummy metal layer are formed. A method of manufacturing a thin film transistor array substrate. 6. The thin film transistor array of claim 1, further comprising forming first and second pad open regions in each of the gate pad portion and the data pad portion when the pixel electrode contact hole is formed. 7. Method of manufacturing a substrate. The method of claim 7, wherein when the pixel electrode is formed, first and second transparent conductive layers are formed on the gate pad and the data pad to connect the gate pad and the data pad through the first and second pad open regions, respectively. Method of manufacturing a thin film transistor array substrate further comprising the step. A substrate having a first region; A common line and a gate electrode spaced apart from each other on the first substrate; A gate insulating film formed on the first substrate except for the upper portion of the common wiring; A semiconductor layer formed on the gate insulating layer overlapping the gate electrode; A source electrode and a drain electrode formed on the semiconductor layer to be spaced apart from each other by a predetermined interval; A dummy metal layer in contact with the common wiring; A passivation layer formed on the source / drain electrodes and the dummy metal layer; And a pixel electrode electrically connected to the drain electrode. The method of claim 9, wherein the dummy metal layer in contact with the common wiring A thin film transistor array substrate, characterized in that the lower electrode of the storage capacitor. The thin film transistor array substrate of claim 10, wherein the pixel electrode overlapping the lower electrode of the storage capacitor is an upper electrode of the storage capacitor. The method of claim 9, wherein the first region is A thin film transistor array substrate comprising an active region. The substrate of claim 9, wherein the substrate provided with the first region is provided. And a second region having a gate pad portion and a data pad portion. The method of claim 13, wherein the gate pad portion A gate pad formed on the substrate; A gate insulating film and a protective film formed on the gate pad; And And a first transparent conductive film in contact with the gate pad. The method of claim 13, wherein the date pad unit A gate insulating film formed on the substrate; A data pad formed on the gate insulating layer; A protective film formed on the data pad; And And a second transparent conductive film in contact with the data pad.

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