KR20070120768A - Driving circuit for display device and method for driving the same - Google Patents

Abstract

A method and a circuit for driving a display device are provided to prevent a degradation of an image quality due to a decrease in a charging ratio by increasing a pulse width for a region with the decreased charging ratio. A driving circuit for a display device includes a display panel(10), gate driving ICs(24-27), a data driving IC(31) and a timing controller(40). The display panel displays an image. The gate driving ICs supply scan pulses to the display panel. The data driving IC supplies an image signal to the display panel. The timing controller generates clock pulses with different pulse widths according to a position of the gate driving IC. Each of the gate driving ICs supplies scan pulses with different pulse widths in response to the corresponding clock pulse. The scan pulse has a pre-charging period, which is overlapped by a previous scan pulse by a predetermined amount of interval.

Description

Driving device for display device and driving method thereof {Driving circuit for display device and method for driving the same}

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a shift register provided in the gate circuit film shown in FIG. 1. FIG.

3 is a waveform diagram illustrating scan pulses output from a shift register illustrated in FIG. 2;

FIG. 4 is a waveform diagram illustrating other scan pulses output from the shift register shown in FIG. 2. FIG.

＊ Explanation of symbols for main parts of drawing *

20 to 23: first to fourth gate circuit film

24 to 27: first to fourth gate integrated circuit IC

GD1 to GD4: first and fourth regions

31: data integrated circuit IC

AST1 to DSTn: A1 to D2 stage

CLK1 to CLK8: first to eighth clock pulses

AVout1 to DVout4: A1 to D4 scan pulse

The present invention relates to a display device and a driving method thereof capable of preventing a deterioration in image quality caused by insufficient charging of image data due to gate-on time distortion.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, and a timing controller for controlling the gate driver and the data driver.

The gate driver includes a shift register to sequentially output scan pulses. The shift register is composed of a number of stages connected dependently to each other. Each of the plurality of stages receives at least one clock pulse among a plurality of clock pulses having a sequential phase difference from each other. The scan pulses are sequentially output to sequentially scan the gate lines of the liquid crystal panel.

However, the conventional liquid crystal display device has a problem that the input signal is distorted due to an increase in the amount of load including the resistance and the capacitor component of the liquid crystal panel as the liquid crystal display becomes larger and higher in resolution. That is, since the load increases as the gate line and the data line provided in the liquid crystal panel move away from the gate driver and the data driver, the time for which the gate line is turned on is distorted. As a result, the charging rate of the data signal is lowered. The picture quality deteriorates. In particular, the farther away from the data driver, the shorter the data charging time due to the load of the liquid crystal panel, the lower the image quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a display device and a driving method thereof capable of preventing a deterioration in image quality caused by insufficient charging of image data due to gate-on time distortion.

In order to achieve the above object, a driving apparatus of a display device according to an exemplary embodiment of the present invention includes a display panel for displaying an image, a gate driving integrated circuit for supplying scan pulses to the display panel, and supplying an image signal to the display panel. And a timing controller for generating clock pulses having different pulse widths according to positions of the gate driving integrated circuits, wherein each of the gate driving integrated circuits is provided from the timing controller. The scan pulses having different pulse widths are supplied in response to the corresponding clock pulses, and the scan pulses have a precharge period overlapping with the previous scan pulses for a predetermined period.

In addition, the driving method of the image display device according to an embodiment of the present invention for achieving the above object is the step of generating a clock pulse having a different pulse width in accordance with the position of the gate driving integrated circuit, and in response to the clock pulse And generating scan pulses having different pulse widths, wherein the scan pulses have a pre-charge period overlapping with a previous scan pulse for a predetermined period.

Hereinafter, a driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

1 illustrates a liquid crystal panel 10 including a plurality of gates and data lines, and a plurality of gate circuits in which a plurality of gate ICs 24 to 27 are mounted to drive the plurality of gate lines. A plurality of data circuit films 30 mounted with films 20 to 23, a plurality of data ICs 31 for driving a plurality of data lines, a plurality of gate ICs 24 to 27, and a plurality of data ICs. A timing controller 40 for controlling 31.

The liquid crystal panel 10 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines and a plurality of data lines, and a liquid crystal capacitor connected to the TFT. The liquid crystal capacitor is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal between them. The TFT supplies the data signal from each of the data lines to the pixel electrode in response to the scan pulse from each of the gate lines.

The gate ICs 24 to 27 are mounted on the gate circuit films 20 to 23, respectively, to be connected to the liquid crystal panel 10, and the data IC 31 is mounted to the data circuit film 30, respectively, to the liquid crystal panel 10. And data are connected between the PCB. In addition, the data IC 31 is connected to the timing controller 40 through the data PCB and the data circuit film 30, and the gate ICs 24 to 27 are the data PCB, the data circuit film 30, and the liquid crystal panel 10. And the timing controller 40 via the gate circuit films 20 to 23. The timing controller 40 may be mounted on the data PCB or mounted on the main PCB to be connected to the data PCB through the FPC. In this case, the gate and data circuit films 20 to 23, 30 may be TCP films or COF films.

The gate ICs 24 to 27 include shift registers that sequentially generate scan pulses, that is, gate high pulses, in response to gate control signals input from the timing controller 40. The configuration and driving method for the shift register will be described later.

The data IC 31 converts the digital image data into analog image data according to a data control signal input from the timing controller 40, and the analog image of one horizontal line for each horizontal period in which scan pulses are supplied to the gate lines. Supply data to the data lines. That is, the data IC 31 selects a gamma voltage having a predetermined level according to the gray value of the analog image data and supplies the selected gamma voltage to the data lines.

Here, the liquid crystal panel 10 is divided into first to fourth regions GD1 to GD4 to correspond to the first to fourth gate ICs 24 to 27. The gate control signal input from the timing controller 40 is weakened farther from the first to fourth gate ICs 24 to 27. Specifically, although not shown in the drawings, the gate-on time decreases as the distance from the output buffer included in the first to fourth gate ICs 24 to 27 increases. In addition, the further away from the output buffer of the data IC 31, the weaker the signal of the image data. Therefore, since the signal of the region farthest from the fourth gate IC 27 of the fourth region GD4 and the farthest from the data IC 31 shown in the drawing is weakest, the fourth region GD4 is affected by the signal distortion. For the most vulnerable area.

Since the fourth region GD4 is farther from the fourth gate IC 27, the resistance of the liquid crystal panel 10 and the load of the capacitor increase, so that the signal on, for example, the gate-on time is reduced. As a result, the video data charging rate from the data IC 31 is affected by the gate-on time and the defective rate of image quality is increased.

In order to prevent distortion of the gate and data signals, the first to fourth gate ICs 24 to 27 according to the present invention may include clock timings in which pulse widths are modulated according to the first to fourth regions GD1 to GD4. 40). In addition, scan pulses having different pulse widths are sequentially output according to the first to fourth regions GD1 to GD4 using the clock pulses of which the pulse width is modulated.

FIG. 2 is a diagram illustrating a shift register provided in the gate IC of FIG. 1.

The shift register shown in FIG. 2 is composed of n stages AST1 to DSTn and one dummy stage STn + 1 connected to each other. The n stages AST1 to DSTn and the dummy stages STn + 1 sequentially output n scan pulses AVout1 to DVoutn. Here, the n scan pulses AVout1 to DVoutn output from the n stages AST1 to DSTn are sequentially supplied to the gate lines of the liquid crystal panel 10 to sequentially scan the gate lines.

To this end, the n stages AST1 to DSTn and the dummy stages STn + 1 are commonly supplied with the first and second driving voltages VDD and VSS. In addition, at least one clock pulse having a pulse width modulated according to the first to fourth regions GD1 to GD4, that is, the first to eighth clock pulses CLK1 to CLK8 is applied.

Here, the A1 stage AST1 receives the start pulse SP from the timing controller 40, and the A2 through dummy stages AST2 through STn + 1 receive the output signal of the preceding stage as a trigger signal. The A1 to D2 stages AST1 to DSTn receive the output signal of the next stage as a reset signal. Here, the first driving voltage VDD means the gate on voltage VGON, and the second driving voltage VSS means the gate off voltage VGOFF.

A plurality of A stages not shown in the drawings, including the A1 to A4 stages AST1 to AST4, are embedded in the first gate IC 24 shown in FIG. 1, and are not shown including the B1 and B2 stages BST1 and BST2. A number of B stages, which are not included, are embedded in the second gate IC 25. In addition, a plurality of C stages including the C1 and C2 stages CST1 and CST2 are embedded in the third gate IC 26, and a plurality of D stages and dummy stages STn + including the D1 and D2 stages DST1 and DST2. 1) is embedded in the fourth gate IC 27.

Accordingly, the plurality of A stages including the A1 to A4 stages AST1 to AST4 are sequentially supplied with the first and second clock pulses CLK1 and CLK2, and the plurality of A stages including the B1 and B2 stages BST1 and BST2. The B stages are sequentially supplied with the third and fourth clock pulses CLK3 and CLK4. The C stages including the C1 and C2 stages CST1 and CST2 are sequentially supplied with the fifth and sixth clock pulses CLK5 and CLK6, and the plurality of D stages including the D1 and D2 stages DST1 and DST2. The stages are sequentially supplied with the seventh and eighth clock pulses CLK7 and CLK8.

FIG. 3 is a waveform diagram of scan pulses output in a plurality of stages shown in FIG. 2.

The scan pulses AVout1 to DVout4 shown in FIG. 3 are sequentially outputted with different pulse widths according to the first to fourth regions GD1 to GD4. Specifically, in the first region GD1, a plurality of A stages, not illustrated, including the A1 to A4 stages AST1 to AST4, supply the first and second clock pulses CLK1 and CLK2 having a pulse width reduced by 1H. Receive. Then, the first and second clock pulses CLK1 and CLK2 are used to output a plurality of scan pulses AVout1 to CVout4 having a pulse width of 1H. This is because the first gate IC 24 of the first region GD1 is located closest to the data IC 31 so that the output characteristic of the signal applied to the first region GD1, that is, the gate-on time does not decrease. The video data charging rate from the IC 31 does not decrease. For this reason, the driving time of one frame can be made the same by increasing the width of scan pulses DVout1 to DVout4 in the fourth region GD4 where the output characteristic is most degraded by 1H.

Also, in the second region GD2, a plurality of B stages, which are not shown, including the B1 and B2 stages BST1 and BST2, supply the third and fourth clock CLK3 and CLK4 pulses whose pulse width is reduced by 0.5H. Receive. Then, a plurality of scan pulses BVout1 to BVout4 having a pulse width of 1.5H are output using the third and fourth clock signals CLK3 and CLK4. This is because the width of the scan pulses CVout1 to CVout4 in the third region GD3 in which the output characteristics are deteriorated on the assumption that the output characteristics of the signal applied to the second region GD2 is not deteriorated is also increased by 0.5H.

In the third region GD3, a plurality of C stages (not shown) including the C1 and C2 stages CST1 and CST2 are supplied with the fifth and sixth clock pulses CLK5 and CLK6 having a pulse width increased by 0.5H. The plurality of scan pulses CVout1 to CVout4 having a pulse width of 2.5H are output using the fifth and sixth clock pulses CLK5 and CLK6. In the fourth region GD4, a plurality of D stages (not shown) including the D1 and D2 stages DST1 and DST2 are supplied with the seventh and eighth clock pulses CLK7 and CLK8 having a pulse width increased by 1H. . The plurality of scan pulses DVout1 to DVout4 having a pulse width of 3H are output using the seventh and eighth clock pulses CLK7 and CLK8.

As described above, scan pulses AVout1 to DVout4 having different pulse widths may be supplied to the respective gate ICs 24 to 27 while maintaining the same driving time of one frame. The pulse widths of the scan pulses AVout1 to BVout4 supplied to the first region GD1 and the second region GD2 in the first and second gate ICs 24 and 25 positioned closest to the data IC 31 are determined. Decrease. The pulse widths of the scan pulses CVout1 to DVout4 in the third region GD3 and the fourth region GD4 located far from the data IC 31 are increased.

4 is a waveform diagram of other scan pulses output from the shift register shown in FIG. 2.

The scan pulses AVout1 to DVout4 shown in FIG. 4 are sequentially overlapped with each other for a certain period according to the first to fourth regions GD1 to GD4 and have different pulse widths. Specifically, the gate lines adjacent to each other among the gate lines sequentially driven along the first to fourth regions GD1 to GD4 are simultaneously driven for a predetermined period. This is a method of increasing the width of the scan pulses CVout1 to DVout4 input to the third and fourth regions GD3 and GD4, unlike the case in which the outputs do not overlap each other. Also, as the scan pulses AVout1 to DVout4 are supplied to the gate lines, the charging time of the image data is increased, thereby increasing the effective period in which the gate lines are driven.

Specifically, in the first region GD1, a plurality of A stages, not shown, including the A1 to A4 stages AST1 to AST4, supply the first and second clock pulses CLK1 and CLK2 having a pulse width reduced by 2H. Receive. Then, the first and second clock pulses CLK1 and CLK2 are used to output a plurality of scan pulses AVout1 to AVout4 having a pulse width of 1H. This is because the first gate IC 24 of the first region GD1 is located closest to the data IC 31 so that the output characteristic of the image data applied to the first region GD1, that is, the charging rate does not decrease. . Therefore, the driving time of one frame can be made the same by increasing the width of scan pulses DVout1 to DVout4 in the fourth region GD4 where the video data filling rate decreases according to the gate-on time by 2H.

Also, in the second region GD2, a plurality of B stages, which are not shown, including the B1 and B2 stages BST1 and BST2 through the second gate IC 25, have the pulse widths reduced by 1H. The clock pulses (CLK3, CLK4) are supplied. A plurality of scan pulses BVout1 to BVout4 having a pulse width of 2H size are output using the third and fourth clock pulses CLK3 and CLK4. In order to increase the width of scan pulses CVout1 to CVout4 in the third region GD3 where the filling rate of the image data is lowered since the filling rate of the image data applied to the second region GD2 is not lowered. to be.

In the third region GD3, a plurality of C stages (not shown), including the C1 and C2 stages CST1 and CST2, have a size of 4H using the fifth and sixth clock pulses CLK5 and CLK6 having a pulse width increased by 1H. A plurality of scan pulses CVout1 to CVout4 having a pulse width of is outputted. In the fourth region GD4, a plurality of D stages (not shown) including the D1 and D2 stages DST1 and DST2 use the seventh and eighth clock pulses CLK7 and CLK8 having a pulse width increased by 2H. A plurality of scan pulses DVout1 to DVout4 having a pulse width of 5H magnitude are output.

Accordingly, the widths of the scan pulses AVout1 to BVout4 of the first area GD1 and the second area GD2 are reduced while the driving time of one frame remains the same, and the third area GD3 is stable. ) And the pulse widths of the scan pulses CVout1 to DVout4 of the fourth region GD4 may be further increased.

As described above, the driving device of the display device according to the present invention increases the supply lines of the clock pulses CLK1 to CLK8 shown in FIG. 2, thereby scanning the scan pulses AVout1 to DVout4 shown in FIGS. 3 and 4. Unlike this, clock pulses having different pulse widths may be supplied according to each stage AST1 to DSTn.

Specifically, the smallest width flux pulse is supplied to the stage AST1 at the position closest to the gate ICs 24 to 27 and the data IC 31, and the gate ICs 24 to 27 and the data IC 31 are supplied. The farthest stage DSTn is supplied with the widest clock pulse. At this time, the increase rate and the decrease rate of the pulse width are adjusted to maintain the driving time of one frame. As a result, because the gate ICs 24 to 27 and the data IC 31 are located far from each other, the pulse width can be increased along the gate line where the charging rate of the image data decreases, thereby reducing the degradation of the image quality of the displayed image. have.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the present invention has the following effects in the display device and its driving method.

While maintaining a constant driving time of one frame, scan pulses having an increased pulse width according to areas where the charging rate of the image data is weak may be prevented, thereby preventing deterioration in image quality due to a decrease in the charging rate of the image data.

Claims (12)

A display panel displaying an image; A gate driving integrated circuit supplying a scan pulse to the display panel; A data driver integrated circuit supplying an image signal to the display panel; And A driving apparatus of a display apparatus comprising a timing controller for generating clock pulses having different pulse widths according to positions of the gate driving integrated circuits. Each of the gate driving integrated circuits supplies scan pulses having different pulse widths in response to corresponding clock pulses from the timing controller, and the scan pulses have a precharge period overlapping with a previous scan pulse for a predetermined period. A drive device for a display device. The method of claim 1, The clock pulse The clock supplied to the gate driving integrated circuit located far from the data driving integrated circuit as the pulse width of the clock pulse supplied to the gate driving integrated circuit located near the data driving integrated circuit is reduced so that the driving time of one frame is the same. And a pulse width of the pulse is increased. The method of claim 2, The scan pulse Scan output from the gate driving integrated circuit located far from the data driving integrated circuit as the pulse width of the scan pulse output from the gate driving integrated circuit located close to the data driving integrated circuit is reduced so that the driving time of one frame is the same. And a pulse width of the pulse is increased. The method of claim 3, wherein The scan pulse The driving device of the display device, characterized in that the output is overlapped with each other during the 1H to 3H period. The method of claim 1, The clock pulse The driving device of the display device, characterized in that the output is overlapped with each other during the 1H to 3H period. The method of claim 5, The clock pulse The pulse width of the clock pulse supplied to the stage located far from the data driving integrated circuit increases as the pulse width of the clock pulse supplied to the stage of the gate driving integrated circuit located close to the data driving integrated circuit increases. A drive device for a display device. Generating clock pulses having different pulse widths according to positions of the gate driving integrated circuits; And A method of driving a display device comprising generating scan pulses of different pulse widths in response to the clock pulses. And the scan pulse has a precharge period overlapping with a previous scan pulse for a predetermined period. The method of claim 7, wherein The clock pulse As the pulse width of the clock pulse supplied to the gate driving integrated circuit located close to the data driving integrated circuit is reduced so that the driving time of one frame is the same, the clock pulse supplied to the gate driving integrated circuit located far from the data driving integrated circuit is reduced. A driving method of a display device, characterized in that the pulse width is increased. The method of claim 8, The scan pulse The gate driving located far from the data driving integrated circuit as the pulse width of the scan pulse output from the data driving integrated circuit located close to the data driving integrated circuit is reduced in response to the clock pulse so that the driving time of one frame is the same. And a pulse width of the scan pulse output from the integrated circuit is increased. The method of claim 9, The scan pulse A method of driving a display device, the output device being superimposed on one another during a period of 1H to 3H. The method of claim 8, The clock pulse A method of driving a display device, the output device being superimposed on one another during a period of 1H to 3H. The method of claim 11, The clock pulse The pulse width of the clock pulse supplied to the stage located far from the data driving integrated circuit is increased as the pulse width of the clock pulse supplied to the stage of the gate driving integrated circuit located close to the data driving integrated circuit increases. A method of driving a display device.

Images