KR20070120057A - Step-up/step-down type dc-dc converter, and control circuit and control method of the same - Google Patents

Abstract

A step-up/step-down type DC-DC converter, and a method and a circuit for controlling the DC-DC converter are provided to improve an operation efficiency of the DC-DC converter by lowering an average switching frequency of a switching element while decreasing a peak-to-peak value of an inductor current. A first switching element(FET1) is connected between a voltage input terminal(Vin) and a first terminal of an inductor(L1). A first rectifying element(FET2) is connected between a reference voltage and the first terminal of the inductor. A second rectifying element(FET4) is connected between a voltage output terminal(Vout) and a second terminal of the inductor. A second switching element(FET3) is connected between the reference voltage and the second terminal of the inductor. In a first state, the first and second switching elements are turned on. In a second state, the first and second switching elements are turned off. In a third state, the first switching element is turned on, while the second switching element is turned off. A first periodic operation is performed at a first period in the second state. A second periodic operation is performed at a second period, which is longer than the first period, in the first and third states.

Description

Control method of step-up type DC-DC converter, step-up type DC-DC converter and control method of step-up type DC-DC converter {STEP-UP / STEP-DOWN TYPE DC-DC CONVERTER, AND CONTROL CIRCUIT AND CONTROL METHOD OF THE SAME}

1 is a circuit diagram of a step-up / down DC-DC converter 1.

2 is a circuit diagram showing a state of the state 1.

3 is a circuit diagram showing a state of the state 2.

4 is a circuit diagram showing a state of the state 3.

5 is a state transition diagram of the first embodiment;

6 is a waveform diagram of a DC-DC converter 1 according to the first embodiment.

7 is a waveform diagram showing a conventional circuit operation.

8 is a state transition diagram according to the second embodiment.

9 is a waveform diagram of a DC-DC converter 1 according to the second embodiment.

10 is a circuit diagram of a DC-DC converter 1b.

Fig. 11 is a waveform diagram of a DC-DC converter 1b in the third embodiment.

12 is a circuit diagram of a conventional DC-DC converter 100.

<Explanation of symbols for the main parts of the drawings>

1: DC-DC converter 11: control circuit

CLK: Clock signal COMP1: Voltage comparator

ERA: error amplifier Eout: output signal

FET1, FET2, FET3, FET4: Transistor

IL: Inductor Current Iout: Output Current

L1: Choke Coil OSC: Oscillator

SC: Status control circuit T: Basic cycle

T1, T1a: first period T2: second period

TO1, TO1a: first periodic operation TO2: second periodic operation

Tin: Input Terminal Tout: Output Terminal

V1: output signal Vin: input voltage

Vout: Output Voltage Vs: Current Sense Signal

Cross Reference of Related Application

This application is based on and claims the benefit of priority from Japanese Priority Patent Application No. 2006-167677 filed June 16, 2006 and Japanese Patent Application No. 2007-151323 filed June 7, 2007, respectively. The entire contents are used here for reference.

The present invention relates to a control method of a step-down type DC-DC converter, a step-down type DC-DC converter, and a control method of a step-down type DC-DC converter. In particular, the average switching frequency of the switching element can be lowered, resulting in high efficiency. A step-down type DC-DC converter that can be designed can be used.

The step-up / down DC-DC converter connects an inductor to three terminals of the voltage input terminal, the voltage output terminal, and the reference potential by the on / off operation of the switching element, and stores the energy in the inductor from the input side (1). And the state 2 emitting energy from the inductor to the output side are alternately repeated at a predetermined frequency.

The step-up / down DC-DC converter disclosed in Patent Document 1 further includes a state 3 for connecting a voltage input terminal and a voltage output terminal through an inductor and supplying energy to the output. Then, within one clock cycle, the state 1 and the state 3 are switched, or the state 2 and the state 3 are switched.

In the conventional boosted DC-DC converter 100 shown in FIG. 12, transistors FET101 to FET103 are provided. By turning off the transistor FET103 when the DC-DC converter 100 is stopped, the dark current flowing from the input voltage Vin to the load RL is prevented.

Moreover, patent documents 2-7 are disclosed as said related art.

[Patent Document 1] US Patent No. 6087816

[Patent Document 2] U.S. Patent No.6275016

[Patent Document 3] Japanese Patent Application Laid-Open No. 2005-192312

[Patent Document 4] Japanese Patent Laid-Open No. 55-68877

[Patent Document 5] US Patent No. 5402060

[Patent Document 6] US Patent No. 4395675

[Patent Document 7] Japanese Patent Laid-Open No. 56-141773

[Patent Document 8] Japanese Patent Application Laid-Open No. 2000-134943

In recent years, miniaturization of inductors is progressing in accordance with the demand for miniaturization and lightening of electronic devices. In this case, since the peak-to-peak current value of the inductor current needs to be suppressed, the switching frequency increases, and as a result, the switching loss tends to increase. Therefore, in order to reduce switching loss, it is necessary to reduce the switching frequency while suppressing the peak-to-peak current value of the inductor current. However, Patent Document 1 does not describe such reduction of the switching frequency, and it is problematic because the reduction of the switching loss cannot be achieved.

In the conventional step-up DC-DC converter 100 shown in FIG. 12, when the transistor FET103 is turned on when starting from the stop state, the charging current to the output capacitor C101 causes the rush current Ir. ). As a result, the net voltage of the input voltage Vin is generated, which may cause a malfunction such as a protection circuit to operate. In addition, since the output voltage Vout rises rapidly from 0 (V) to the input voltage Vin by the rush current Ir, it is difficult to gradually increase the output voltage Vout from zero to a predetermined set voltage. There is a problem that start control cannot be performed. In addition, the rush current Ir is a problem because each element constituting the circuit may be destroyed.

SUMMARY OF THE INVENTION The present invention has been made to solve at least one of the problems of the background art, and can reduce the number of switching in the unit time of the switching element, that is, the average switching frequency, while suppressing the peak-to-peak current value of the inductor current. It is an object of the present invention to provide a step-up / down DC-DC converter capable of achieving high efficiency. It is a second object of the present invention to provide a step-up / down DC-DC converter capable of performing a step-up operation while realizing both soft start control and prevention of dark current.

The first state is a state in which the first and second switching elements are turned on. In this case, one terminal of the inductance element is connected to the voltage input terminal, and the other terminal is connected to the reference potential. In the first state, energy is accumulated in the inductance element from the voltage input terminal side, and the inductor current increases with a steep constant slope over time. The increase slope is determined by (input voltage) / (inductance value).

The second state is a state in which the first and second switching elements are turned off. In this case, one terminal of the inductance element is connected to the reference potential, and the other terminal is connected to the voltage output terminal. In the second state, energy is released from the inductance element to the voltage output terminal side, and the inductor current decreases with a steep constant slope over time. The decreasing slope is determined by-(output voltage) / (inductance value).

The third state is a state in which the first switching element is turned on and the second switching element is turned off. In this case, one terminal of the inductance element is connected to the voltage input terminal, and the other terminal is connected to the voltage output terminal. In the third state, when the input voltage is higher than the output voltage, energy from the voltage input terminal side accumulates in the inductance element and is also supplied to the voltage output terminal side, and the inductor current increases with a constant slope with the passage of time. Conversely, when the input voltage is lower than the output voltage, energy is released from the inductance element to the voltage output terminal side, and the inductor current decreases with a constant slope with the passage of time. At this time, the increase or decrease slope of the inductor current in the third state becomes smaller than the increase or decrease slope in the first and second states. In addition, when the input voltage approaches the output voltage, the inclination of the inductor current in the third state becomes almost zero. Then, conduction control of the first and second switching elements is performed to realize the first, second, and third states.

The first periodic operation is an operation performed in a predetermined first period including the second state. In the second state of the first periodic operation, the inductor current decreases with a steep constant slope. The second periodic operation is an operation performed in a second period larger than the first period including the first state and the third state. In the first state of the second periodic operation, the inductor current increases with a steep constant slope. In the third state of the second periodic operation, the inductor current increases with a gentle increase slope than the increase slope of the first state, or decreases with a gentle decrease slope than the decrease slope of the second state. Then, the first periodic operation and the second periodic operation are repeated.

In the present invention, in the second periodic operation, the change in the inductor current is slowed down by switching from the first state to the third state. Therefore, since the peak-to-peak current value of the inductor can be prevented from increasing, the second period of the second period operation can be made larger than the first period of the first period operation. As a result, since the average switching frequency of the first and second switching elements can be lowered, the switch drive loss occurring at the time of switching the switch on or off, or the conduction of the switch in the transient state at the time of switching the on / off switching The loss can be reduced. Therefore, it becomes possible to raise the efficiency of a DC-DC converter.

The soft start control circuit outputs a soft start signal whose value rises or falls over time. In the case where control is difficult to gradually increase the output voltage from zero to the set voltage, the value of the soft start signal is increased. In addition, when the control which makes it difficult to gradually reduce the output voltage from the set voltage to zero, the value of the soft start signal is lowered. The error amplifier amplifies the error between the output voltage and the lower one of the reference voltage and the soft start signal which defines the set voltage of the output voltage. The switching control circuit switches the control of the first to fourth switching elements in accordance with the magnitude relationship between the output voltage and the input voltage. In addition, the switching control circuit controls the switching duty of the first to fourth switching elements in accordance with the output of the error amplifier.

The following describes the stop of the DC-DC converter. When the DC-DC converter is stopped, all of the first to fourth switching elements are kept in the off state. Here, although there is a first switching element on the current path from the voltage input terminal to the voltage output terminal, the polarity of the body diode of the first switching element is reversed from the voltage input terminal to the voltage output terminal. Thus, the first switching element interrupts the current path from the voltage input terminal to the voltage output terminal. Accordingly, generation of dark current flowing from the voltage input terminal to the voltage output terminal when the DC-DC converter is stopped can be prevented. In addition, by preventing the dark current, the output voltage at the time of stopping the DC-DC converter can be maintained at 0 (V).

Next, the period in which the output voltage is lower than the input voltage in the operation of the DC-DC converter will be described. In this period, the first state in which the first and third switching elements are turned on and the second state in which the second and fourth switching elements are turned on are alternately switched by the switching control circuit. At this time, the switching duty of the first to fourth switching elements is determined according to the output of the error amplifier.

In the first state, since the first terminal of the inductance element is connected to the voltage input terminal and the second terminal is connected to the reference potential, energy is accumulated in the inductance element from the voltage input terminal side. In the second state, since the first terminal of the inductance element is connected to the reference potential and the second terminal is connected to the voltage output terminal, energy is discharged from the inductance element to the voltage output terminal side. Thus, since the 1st state and the 2nd state are repeated alternately, a lifting operation is performed. Then, since the voltage rising and falling operation is not conducted directly between the voltage input terminal and the voltage output terminal, the rush current is prevented from flowing from the voltage input terminal to the voltage output terminal side. Therefore, the situation where the output voltage rises rapidly to the input voltage is prevented, so that the soft start operation which gradually raises or lowers the output voltage according to the rising or falling of the soft start signal becomes possible.

In addition, the period in which the output voltage is higher than the input voltage in the operation of the DC-DC converter will be described. In this period, the switching control circuit keeps the first switching element on and the second switching element off. In addition, the switching control circuit alternately turns the third switching element and the fourth switching element on. Therefore, the boost converter is formed by the third and fourth switching elements and the inductance element. In addition, the switching duty of the third and fourth switching elements is determined by the output of the error amplifier.

When the third switching element is turned on and the fourth switching element is turned off, the first terminal of the inductance element is connected to a voltage input terminal, the second terminal is connected to a reference potential, and energy is interned toward the voltage input terminal side. Accumulate in DUX elements. In addition, when the third switching element is in the off state and the fourth switching element is in the on state, the first terminal of the inductance holding is connected to the reference potential, the second terminal is connected to the voltage output terminal, and energy from the inductance element is obtained. Is emitted to the voltage output terminal side. In this way, since the third switching element and the fourth switching element are alternately turned on, the boosting operation is performed. By switching from the step-up operation to the step-up operation, the number of transistors in which the switching operation is performed can be reduced from four of the first to fourth switching elements to two of the third and fourth switching elements. Thus, it is possible to reduce switching losses.

In the step of turning off the first to fourth switching elements, the DC-DC converter is stopped. At this time, the current path from the voltage input terminal to the voltage output terminal is interrupted by the first switching element. As a result, it is possible to prevent the dark current flowing from the voltage input terminal to the voltage output terminal when the DC-DC converter is stopped.

In the stopped state of the DC-DC converter, the process proceeds to the step of alternately performing the first state and the second state in accordance with the start command. In the first state, energy is accumulated in the inductance element from the voltage input terminal side. In the second state, energy is released from the inductance element to the voltage output terminal side. As described above, since the first state and the second state are alternately repeated, the step-up / down operation is performed, so that the rush current is prevented from flowing from the voltage input terminal to the voltage output terminal side without directly conducting the voltage input terminal and the voltage output terminal. . Thus, soft start operation is possible.

As the output voltage becomes higher than the input voltage, the first switching element is kept on and the second switching element is off, while the third switching element and the fourth switching element are alternated depending on the output of the error amplifier. Go to the step to turn on. In this step, the boost converter is formed by the third and fourth switching elements and the inductance element to perform the boost operation. By switching from the step-up operation to the step-up operation, the number of transistors in which the switching operation is performed can be reduced from four of the first to fourth switching elements to two of the third and fourth switching elements. Therefore, switching loss can be reduced.

As described above, in the control circuit of the step-up / down DC-DC converter, the control method of the step-up / down DC-DC converter, and the step-up / down DC-DC converter in the present invention, the dark current can be prevented when the DC-DC converter is stopped. In the period during which the output voltage is lower than the voltage during the operation of the DC-DC converter, the step-up / down operation is performed, thereby preventing the occurrence of the rush current and the soft start operation. In addition, when the output voltage is higher than the input voltage during the operation of the DC-DC converter, the boosting operation is performed, whereby the switching loss can be reduced. As a result, it is possible to construct a step-up / down DC-DC converter capable of performing a step-up operation while realizing both soft start control and prevention of dark current.

Hereinafter, the present invention will be described. 1 is a circuit diagram of a step-up / down DC-DC converter 1 according to the present invention. This DC-DC converter has a configuration of a so-called H bridge type switching regulator, and includes a choke coil L1, transistors FET1, FET2, FET3, FET4, an output capacitor C1, and a control circuit 11. An input terminal Tin is connected to the drain terminal of the transistor FET1, and an input voltage Vin is input thereto. The source terminal of the transistor FET1 is connected to the terminal Tx of the choke coil L1 and the drain terminal of the transistor FET2. The source terminal of transistor FET2 is connected to a reference potential. Gate terminals of the transistors FET1 and FET2 are connected to the output terminals DH1 and DL1 of the control circuit 11, respectively.

The drain terminal of the transistor FET4 is connected to the output terminal Tout, and the input voltage Vin is stepped up or down and output as the output voltage Vout. In order to accumulate electric power supplied through the choke coil L1, the output capacitor C1 is connected to the output terminal Tout. In addition, the output terminal Tout is connected to the input terminal FB of the control circuit 11. The source terminal of the transistor FET4 is connected to the terminal Ty of the choke coil L1 and the drain terminal of the transistor FET3. The source U of the transistor FET3 is connected to the reference potential. Gate terminals of the transistors FET3 and FET4 are connected to the output terminals DH2 and DL2 of the control circuit 11, respectively. In addition, the input voltage Vin is supplied to the control circuit 11 as the power supply voltage Vcc.

The structure of the control circuit 11 is demonstrated. The current sense signal Vs that detects the inductor current IL flowing through the choke coil L1 is input to the input terminal CS. The input terminal FB is connected to one terminal of the resistance element R1 connected to the reference potential via the resistance element R2. The connection point of the resistance elements R1 and R2 is connected to the inverting input terminal of the error amplifier ERA. The reference voltage e1 is applied to the non-inverting input terminal of the error amplifier ERA. The output signal Eout is output from the error amplifier ERA. The output terminal of the error amplifier ERA is connected to the non-inverting input terminal of the voltage comparator COMP1, and the output signal Eout is input. In addition, the input terminal CS is connected to the inverting input terminal of the voltage comparator COMP1 to input the current sense signal Vs. The output signal V1 is output from the voltage comparator COMP1. In addition, the clock signal CLK is output from the oscillator OSC. The output terminal of the voltage comparator COMP1 and the output terminal of the oscillator OSC are connected to the status control circuit SC. The output terminals * Q1 and * Q2 are connected to the output terminals DL1 and DL2 while the output terminals Q1 and Q2 of the status control circuit SC are connected to the output terminals DH1 and DH2. The control signals VQ1, * VQ1, VQ2 and * VQ2 are output from the output terminals Q1, * Q1, Q2 and * Q2, respectively. The status control circuit SC controls the control signals VQ1, * VQ1, VQ2, * VQ2 in accordance with the clock signal CLK and the output signal V1.

The operation of the DC-DC converter 1 will be described. In the DC-DC converter 1, as shown in Figs. 2, 3, and 4, the states (1) and (2) depend on the combination of the on / off states of the transistors FET1, FET2, FET3, and FET4. And (3).

When the control signals VQ1 and VQ2 are at the high level and the control signals * VQ1 and * VQ2 are at the low level, the transistors FET1 and FET3 are turned on and the transistors FET2 and FET4 are turned off. Therefore, as shown in FIG. 2, the terminal Tx of the choke coil L1 is connected to the input terminal Tin, and the terminal Ty is connected to the reference potential and becomes the state 1. In the state 1, energy is accumulated in the choke coil L1 from the input terminal Tin side, and the inductor current IL increases with a steep constant slope as time passes. At this time, when the inclination value of the choke coil L1 is L, the increase slope becomes a value determined by (Vin / L).

When the control signals * VQ1 and * VQ2 are high level and the control signals VQ1 and VQ2 are low level, the transistors FET1 and FET3 are turned off and the transistors FET2 and FET4 are turned on. Therefore, as shown in FIG. 3, the terminal Tx of the choke coil L1 is connected to the reference potential, the terminal Ty is connected to the output terminal Tout, and becomes the state 2. In the state 2, energy is emitted from the choke coil L1 to the output terminal Tout side and the inductor current IL decreases with a steep constant slope with the passage of time. At this time, the decreasing slope becomes a value determined by-(Vout / L).

When the control signals VQL and * VQ2 are at the high level and the control signals * VQ1 and VQ2 are at the low level, the transistors FET1 and FET4 are turned on and the transistors FET2 and FET3 are turned off. Therefore, as shown in FIG. 4, the terminal Tx of the choke coil L1 is connected to the input terminal Tin, and the terminal Ty is connected to the output terminal Tout to form the state 3. . In the state 3, when the input voltage Vin is higher than the output voltage Vout, energy from the input terminal Tin side is accumulated in the choke coil L1 and is also supplied to the output terminal Tout side. The inductor current IL increases with a constant slope over time. On the contrary, when the input voltage Vin is lower than the output voltage Vout, energy is released from the choke coil L1 to the output terminal Tout side, and the inductor current IL decreases with a constant slope with the passage of time. . At this time, the increase inclination or decrease inclination of the inductor current IL in the state 3 becomes smaller than the increase inclination of the state 1 or the decrease inclination of the state 2. In addition, when the input voltage Vin approaches the output voltage Vout, the inclination of the inductor current IL in the state 3 becomes almost zero.

The operation of the DC-DC converter 1 in the first embodiment will be described with reference to FIGS. 5 and 6. In the first embodiment, as shown in the state transition diagram of FIG. 5, the first periodic operation TO1 is constituted by the state 1 and the state 2, and the state 1 and the state 3 are provided. The second periodic operation TO2 is configured. And state (1) ⇒ (2) ⇒ (1) ⇒ (3) ⇒ (1). As the state transitions in the order of, the first periodic operation TO1 and the second periodic operation TO2 are alternately repeated.

The operation of the DC-DC converter 1 in the first embodiment will be described using the waveform diagram of FIG. 6. The clock signal CLK is a signal composed of clock pulses of the basic period T. In addition, the output current Iout is an average value of the inductor current IL. Here, the period in which the first periodic operation TO1 is performed is referred to as the first period T1, and the period in which the second periodic operation TO2 is performed is referred to as the second period T2. The first period T1 becomes equal to the basic period T of the clock signal CLK, and the second period T2 becomes a value n times the first period T1. Here, the value of n is a natural number of two or more, and is set to a predetermined value according to, for example, a change in load or a relationship between the input voltage Vin and the output voltage Vout. In this embodiment, the case of n = 4 is demonstrated. In addition, in this embodiment, when the input voltage Vin approaches at the same value as the output voltage Vout, operation | movement in the case where the inclination of the current sense signal Vs in the state 3 is almost zero is performed. Explain.

The first periodic operation TO1 will be described. At time t1 (Fig. 6), in accordance with the vertical rising edge of the clock pulse of the clock signal CLK, the status control circuit SC shifts the control signal VQ2 to a high level, and causes the control signal * VQ2 to shift. Transition to low level. Thus, the state 1 is set, and the first periodic operation TO1 is started. In the state 1, in order to receive energy from the input side with the choke coil L1 disconnected from the output side, the current sense signal Vs increases with a steep slope.

At time t2, when the current sense signal Vs reaches the output signal Eout, the output signal V1 of the voltage comparator C0MP1 transitions from the low level to the high level. The status control circuit SC shifts the control signals VQ1 and VQ2 to the low level as the high level output signal V1 is input, and causes the control signals * VQ1 and * VQ2 to the high level. . Therefore, the state 1 is switched from the state 2 to the state 2. In the state 2, the choke coil L1 is disconnected from the input side and simultaneously connected to the output side, so that the current sense signal Vs decreases with a steep slope. Then, the state 2 is maintained until the next clock signal CLK is input.

Next, the second periodic operation TO2 will be described. At time t3, in accordance with the vertical rising edge of the clock pulse of the clock signal CLK, the status control circuit SC shifts the control signals VQ1 and VQ2 to a high level, and the control signals * VQ1 and * VQ2. Transitions to low level. Therefore, the state 2 is switched from the state 1. Accordingly, the first periodic operation TO1 ends, and the second periodic operation TO2 starts. In the state 1, the current sense signal Vs increases with a sharp drop.

At time t4, when the current sense signal Vs reaches the output signal Eout, the output signal V1 of the voltage comparator COMP1 transitions from the low level to the high level. The status control circuit SC shifts the control signal VQ2 to the low level as the high level output signal V1 is input, and causes the control signal * VQ2 to the high level. Therefore, the state 1 is switched from the state 3.

Then, the state 3 is maintained until the second period T2 elapses. In the state 3, since the input voltage Vin approaches the output voltage Vout, the slope of the current sense signal Vs is almost zero, as shown in FIG. Therefore, the current sense signal Vs keeps the value at time t4 almost constant. In this way, an almost maximum current is maintained in the choke coil L1 during the period of the state 3.

At time t8, the second period T2 ends. Then, in accordance with the vertical rising edge of the clock signal CLK, the status control circuit SC makes the control signal VQ2 transition to the high level and the control signal * VQ2 to the low level. Therefore, the state 3 is switched from the state 3 to the state 1. Accordingly, the second periodic operation TO2 ends and the first periodic operation TO1 starts.

In the state 1 of the first periodic operation TO1, the current sense signal Vs increases with a steep slope. Here, the maximum current sense signal Vs is maintained during the period of the state 3 in the immediately preceding second period T2. Therefore, since the current sense signal Vs has reached the output signal Eout at the time t8, the state transitions from state 1 to 2 at time t9 after the minimum on-pulse period has elapsed.

Thus, state (1) ⇒ (2) ⇒ (1) ⇒ (3) ⇒ (1)... In this order, each state is repeated, so that the first periodic operation TO1 and the second periodic operation TO2 are alternately repeated. And in the area shown by the oblique part of FIG. 6, energy is supplied to the output terminal Tout side, and output current Iout is supplied to a load.

In addition, the number of switching per unit time will be described with reference to FIG. 6. In this embodiment, the switching is defined as the number of times the transistors FET1, FET2, FET3, and FET4 are turned off to on or off or turned on. Thus, in one switching, there are two transition states. In the operation of FIG. 6 according to the first embodiment, the transistors FET1 and FET2 have only one switching in a period (= (n + 1) × T) in which the first period T1 and the second period T2 are aligned. Is done once. Therefore, the switching count SC1 per unit time of the transistors FET1 and FET2 is represented by the following equation.

SC1 = 1 / ((n + 1) x T) (times / sec)... Formula (1)

In the same manner, the transistors FET3 and FET4 are switched twice in a period (= (n + 1) × T) in which the first period T1 and the second period T2 are matched. Therefore, the number of times of switching SC2 per unit time of the transistors FET3 and FET4 is represented by the following equation.

SC2 = 2 / ((n + 1) x T) (times / sec)... Formula (2)

In doing so, the average switching frequency ASC per transistor is given by the following equation.

ASC = 1.5 / ((n + 1) x T) (times / sec)... Formula (3)

On the other hand, Fig. 7 shows an example of the conventional circuit operation. In the conventional circuit operation, the transistors FET1, FET2, FET3, and FET4 all operate in the same basic period T, not two kinds of periods. Therefore, it is not controlled over a plurality of clock cycles of the clock signal CLK. In this case, the transistors FET1, FET2, FET3, and FET4 are switched once in two cycles (= 2 x T). Therefore, the number of switching PSC per unit time of the transistors FET1, FET2, FET3, and FET4 is represented by the following equation.

PSC = 1 / (2 x T) (times / sec)... Formula (4)

By doing so, in formulas (3) and (4), when n≥3, it can be seen that the average switching frequency ASC of the first embodiment is smaller than the conventional switching frequency PSC.

As described above in detail, in the DC-DC converter 1 according to the first embodiment, the inductor current IL is switched from the state 1 to the state 3 in the second periodic operation TO2. The increasing slope of is slowed down. Therefore, since the peak-to-peak current value of the inductor current IL can be prevented from increasing regardless of the magnitude of the second period T2 of the second period operation TO2, the first period operation ( Compared to the first period T1 of the TO1, the second period T2 of the second period operation TO2 may be increased. Since the first period T1 is referred to as one clock cycle of the clock signal CLK, the second period T2 is made larger than the first period T1 so as to cover the plurality of clock cycles of the clock signal CLK. By controlling, it becomes possible to perform multi-clock control. As a result, the average switching frequency of the transistors FET1, FET2, FET3, and FET4 can be lowered, so that the switch drive loss generated when the switch is turned on / off or in the transient state during the on / off switching can be reduced. The conduction loss of a switch can be reduced. Therefore, it becomes possible to raise the efficiency of a DC-DC converter.

The operation of the DC-DC converter 1 in the second embodiment will be described with reference to FIGS. 8 and 9. In the second embodiment, the first periodic operation TO1a is used instead of the first periodic operation TO1 of the first embodiment. As shown in the state transition diagram of FIG. 8, the first periodic operation TO1a is constituted by the state 2, and the second periodic operation TO2 is constituted by the state 1 and the state 3. . And state (1) ⇒ (3) ⇒ (2) ⇒ (1)... As the state transitions in the order of, the first periodic operation TO1a and the second periodic operation TO2 are alternately repeated.

The operation of the DC-DC converter 1 in the second embodiment will be described using the waveform diagram of FIG. 9. Here, the period in which the first periodic operation TO1a is performed is referred to as the first period T1a. The first period T1a becomes equal to the basic period T of the clock signal CLK. In addition, since it is the same as that of 1st Embodiment about another structure, detailed description is abbreviate | omitted here.

The first periodic operation TO1a will be described. At time t11, in accordance with the vertical rising edge of the clock pulse of the clock signal CLK, the status control circuit SC shifts the control signal VQ1 to the low level and transitions the control signal * VQ1 to the high level. Let's do it. Thus, the state 2 is set, and the first periodic operation TO1a is started. In the state 2, the current sense signal Vs decreases with a steep slope. Then, the state 2 is maintained until the next clock signal CLK is input. As a result, in the first period Tla, the period of the state 2 is fixed to the predetermined basic period T.

Next, the second periodic operation TO2 will be described. At time t13, in accordance with the vertical rising edge of the clock pulse of the clock signal CLK, the status control circuit SC shifts the control signals VQ1 and VQ2 to a high level, and the control signals * VQ1 and * VQ2. Transitions to low level. Therefore, the state 2 is switched from the state 1. Accordingly, the first periodic operation TO1a ends and the second periodic operation TO2 starts. In the state 1, the current sense signal Vs increases with a steep slope.

At the time t14, when the current sense signal Vs reaches the output signal Eout, the status control circuit SC switches the control signal VQ2 to a low level as the high level output signal V1 is input. Transition to the high level. Therefore, the state 1 is switched from the state 3. Then, the state 3 is maintained until the second period T2 elapses. In the state 3, since the input voltage Vin approaches the output voltage Vout, the slope of the current sense signal Vs is almost zero, as shown in FIG.

At time t18, the second period T2 ends. Then, in accordance with the vertical rising edge of the clock signal CLK, the status control circuit SC shifts the control signal VQ1 to the low level and shifts the control signal * VQ1 to the high level. Therefore, the state 3 is switched from the state 2 to the state 2. Accordingly, the second periodic operation TO2 ends, and the first periodic operation TO1a starts.

Thus, state (2) ⇒ (1) ⇒ (3) ⇒ (2)... In this order, each state is repeated, so that the first periodic operation TO1a and the second periodic operation TO2 are alternately repeated. And in the area shown by the oblique part of FIG. 9, energy is supplied to the output terminal Tout side, and output current Iout can be supplied to a load.

In addition, the number of switching per unit time will be described with reference to FIG. 9. In the operation of FIG. 9 according to the second embodiment, the transistors FET1, FET2, FET3, and FET4 have a period (= (n + 1) × T) in which the first period T1 and the second period T2 are matched. , Switching is performed once. Therefore, the switching count SCa per unit time of the transistors FET1, FET2, FET3, and FET4 is represented by the following equation.

SCa = 1 / ((n + 1) x T) (times / sec)... Formula (5)

By doing so, in formulas (3) and (5), it can be seen that when n≥2, the number of times of switching SCa decreases compared to the conventional number of times of switching PSC.

As described in detail above, in the DC-DC converter 1 according to the second embodiment, the first periodic operation TO1a is constituted only by the state 2, and the state 2 during the basic period T. The state of is maintained. In addition, in the second periodic operation TO2, since the switching is made from the state 1 to the state 3, the increase inclination of the inductor current IL is slowed down. This makes it possible to further reduce the number of switching of FET3 and FET4 while preventing the peak-to-peak current value of the inductor current IL from increasing. Therefore, it becomes possible to raise the efficiency of a DC-DC converter.

The operation of the DC-DC converter 1b in the third embodiment will be described with reference to FIGS. 10 and 11. 10, the circuit diagram of the DC-DC converter 1b which concerns on 3rd Embodiment is shown. The DC-DC converter 1b has, for example, a configuration of an H bridge type switching regulator, and includes P-type transistors FET1b and FET4b and N-type transistors FET2b and FET3b. The transistors FET1b to FET4b have body diodes BD1 to BD4, respectively. The body diode BD1 makes the direction of the input terminal Tin forward from the terminal Tx, and the body diode BD2 makes the direction of the terminal Tx forward from the reference potential, and the body diode BD3 refers to the reference. The direction of the terminal Ty is forward from the potential, and the body diode BD4 makes the direction of the output terminal Tout from the terminal Ty forward. One end of the load RL is connected to the output terminal Tout, and the other end is connected to the reference potential.

The control circuit 11b is provided with the control elements R1 and R2, the soft start control circuit SS, the error amplifier ERA2, and the switching control circuit 12. As shown in FIG. The operation control signal CNT is input to the soft start control circuit SS through the input terminal TS, and the soft start signal VCS is output. The contact point of the resistance elements R1 and R2 is connected to the inverting input terminal of the error amplifier ERA2, and the divided voltage VN1 is input. In addition, the reference potential e1b is input to the first non-inverting input terminal of the error amplifier ERA2, and the soft start signal VCS is input to the second non-inverting input terminal. The error amplifier ERA2 amplifies the smaller of the reference potential e1b and the soft start signal VCS, the divided voltage VN1, and outputs the output signal Eout2.

The switching control circuit 12 includes a PWM control circuit PWM1, a voltage comparator COMP2, an inverter INV1, and an AND circuit AND1. The output voltage Vout is input to the inverting input terminal of the voltage comparator COMP2, and the input voltage Vin is input to the non-inverting input terminal through the input terminal TI. The output signal V2 output from the voltage comparator COMP2 is input to the AND circuit AND1. The output signal Eout2 is input to the PMW control circuit PMW1. The control signal VQ1b output from the PMW control circuit PMW1 is input to the gate terminals of the transistors FET3b and FET4b through the output terminal D2, and is inverted to the inverter INV1 and input to the AND circuit AND1. do. The control signal VQ2b output from the AND circuit AND1 is input to the gate terminals of the transistors FET1b and FET2b through the output terminal D1. In addition, since the other structure is the same as the DC-DC converter 1 of 1st Embodiment, detailed description is abbreviate | omitted here.

The operation of the DC-DC converter 1b will be described using the operation waveform diagram in FIG. 11. The control circuit 11b starts the soft start operation of the DC-DC converter 1b as the operation control signal CNT input from the CPU or the like not shown is at the high level, and as the level is low, the DC- The DC converter 1b is stopped. The soft start operation here refers to an operation that is difficult to gradually raise the output voltage Vout from zero to a predetermined set voltage when the DC-DC converter 1b is stopped.

The stop time of the DC-DC converter 1b before time t21 is demonstrated. On the current path from the input terminal Tin to the output terminal Tout, the transistors FET1b and FET4b exist. At the time of stopping the DC-DC converter, both the transistors FET1b and FET4b are kept in the off state. The polarity of the body diode BD1 of the transistor FET1b is reversed from the input terminal Tin toward the output terminal Tout. Therefore, the current path from the input terminal Tin to the output terminal Tout is interrupted by the transistor FET1b. As a result, when the DC-DC converter 1b is stopped, generation of dark current flowing from the input terminal Tin to the output terminal Tout can be prevented. In addition, by preventing the dark current, the output voltage Vout at the time of stopping the DC-DC converter 1b can be kept at 0 (V).

The operation at the start of the DC-DC converter 1b will be described. When the operation control signal CNT transitions from the low level to the high level at time t21, the DC-DC converter 1b is started. As the operation control signal CNT becomes high, the soft start signal VCS output from the soft start control circuit SS gradually rises from 0 (V) (arrow A1). In the period from time t21 to time t23, the soft start signal VCS is lower than the reference voltage e1b. Therefore, the error amplifier ERA2 determines the difference between the soft start signal VCS and the divided voltage VN1. Amplify.

The PMW control circuit PMW1 compares an internally generated triangle wave with the output signal Eout2 and outputs a high level control signal VQ1b when the output signal Eout2 is higher than the triangle wave. Therefore, the PMW control circuit PMW1 performs the operation of the output voltage pulse width converter which outputs a pulse of pulse width corresponding to the magnitude of the output signal Eout2.

The operation in the period from the time t21 to the time t22 in which the output voltage Vout is lower than the input voltage Vin will be described. In this period, the high level output signal V2 is output from the voltage comparator COMP2 and is input to the AND circuit AND1. The AND circuit AND1 then passes the output signal of the inverter INV1 and outputs it as the control signal VQ2b. (Arrow A2)

While the control signal VQ1b is at a high level or the control signal VQ2b is at a low level, the transistors FET1b and FET3b are turned on and the transistors FET2b and FET4b are turned off. Therefore, as shown in FIG. 2, the terminal Tx of the choke coil L1 is connected to the input terminal Tin, and the terminal Ty is connected to the reference potential to become the state 1. In the state 1, energy is accumulated in the choke coil L1 from the input terminal Tin side.

On the other hand, while the control signal VQ1b is at the low level and the control signal VQ2b is at the high level, the transistors FET1b and FET3b are turned off and the transistors FET2b and FET4b are turned on. Therefore, as shown in FIG. 3, the terminal Tx of the choke coil L1 is connected to the reference electric potential, the terminal Ty is connected to the output terminal Tout, and becomes the state 2. As shown in FIG. In the state 2, energy is discharged from the choke coil L1 to the output terminal Tout side.

Therefore, in the period from the time t21 to the time t22, the state 1 and the pressure 2 are alternately repeated, and the pressure raising and lowering operation is performed. As the step-up / down operation is performed, since the transistors FET1b and FET4b do not conduct at the same time, direct conduction of the input voltage Vin and the output voltage Vout is prevented, and as a result, the output capacitor is prevented from the input voltage Vin. Rush current is prevented from flowing to C1. Therefore, since the situation where the output voltage Vout rises abruptly to the input voltage Vin is prevented, the output voltage Vout gradually rises with the rise of the soft start signal VCS. In other words, the soft start operation can be performed in the DC-DC converter 1b.

Next, the operation in the period of time t22 or more in which the output voltage Vout is higher than the input voltage Vin will be described. At the time t22, when the output voltage Vout reaches the input voltage Vin, the output signal V2 inverts from the high level to the low level in the voltage comparator COMP2 (arrow A3). The AND circuit AND1 masks the output signal of the inverter INV1 as the low level output signal V2 is input, so that the control signal VQ2b of the AND circuit AND1 is fixed at the low level (arrow A4). ). Therefore, the transistor FET1b is fixed in the on state, and the transistor FET2b is fixed in the off state, so that the terminal Tx of the choke coil L1 is fixed in the state connected to the input terminal Tin.

Since the transistor FET3b is turned on and the transistor FET4b is turned off while the control signal VQ1b is at the high level, the terminal Ty is connected to the reference potential and energy is choked from the input terminal Tin side. Accumulate to L1. On the other hand, while the control signal VQ1b is at the low level, the transistor FET3b is turned off and the transistor FET4b is turned on, so that the terminal Ty is connected to the output terminal Tout and from the choke coil L1. Energy is released to the output terminal Tout side. Therefore, in the period after time t22, the boost converter is formed by the transistors FET3b and FET4b and the choke coil L1, and the boost operation is performed. In addition, the switching duty of the transistors FET3b and FET4b is determined according to the output signal Eout2 of the error amplifier ERA2.

In the boost operation, when the control signal VQ1b is at the low level, the transistors FET1b and FET4b conduct simultaneously, and the input voltage Vin and the output voltage Vout conduct directly. A current path from the input voltage Vin to the output capacitor C1 is formed through the transistor FET1b, the choke coil L1, and the transistor FET4b. Therefore, when the voltage raising operation is performed in the period in which the output voltage Vout is lower than the input voltage Vin, the rush current flows from the input voltage Vin to the output capacitor C1. However, in the DC-DC converter 1b according to the third embodiment, in the period in which the output voltage Vout is lower than the input voltage Vin, the step-up operation rather than the step-up operation is performed. Then, in the step-up / down operation, no current path from the input voltage Vin to the output capacitor C1 is formed, so that the rush current is prevented from flowing. Therefore, the situation where the output voltage Vout rises rapidly to the input voltage Vin is prevented, so that the soft start operation can be performed.

In the DC-DC converter 1b according to the third embodiment, after the time t22 at which the output voltage Vout becomes higher than the input voltage Vin, the step-up operation is switched from the step-up operation to the step-up operation. Therefore, it is possible to reduce the transistor from which the switching operation is performed from four to two while preventing the rush current, thereby reducing the switching loss.

As mentioned above, in the DC-DC converter 1b of this invention, generation | occurrence | production of a dark current at the time of stop is prevented. At the time of starting, in the period in which the output voltage is lower than the input voltage, the step-up / down operation is performed, thereby enabling soft start operation. Further, at the time of start-up, the boosting operation is performed in a period in which the output voltage is higher than the input voltage, so that switching loss can be reduced. As a result, it becomes possible to realize a DC-DC converter with a dark current prevention function capable of realizing rush current prevention and output lamp control.

In addition, this invention is not limited to the said embodiment, Of course, various improvement and modification are possible in the range which does not deviate from the meaning of this invention. In the first embodiment, the case where the input voltage Vin and the output voltage Vout are close to each other and the inclination of the current sense signal Vs in the state 3 is almost zero has been described, but the present invention is not limited to this embodiment. Do not. When the input voltage Vin is higher than the output voltage Vout, in the state 3, the current sense signal Vs increases with a constant slope. At the end of the second period T2, the current sense signal Vs reaches the output signal Eout, whereby the state in the first period T1 subsequent to the second period T2 ( The period of 1) becomes the minimum on pulse period. On the other hand, when the input voltage Vin is lower than the output voltage Vout, in the state 3, the current sense signal Vs decreases with a constant slope. At the end of the second period T2, the current sense signal Vs is lower than the output signal Eout, so that the state 1 in the first period T1 subsequent to the second period T2 is obtained. Is a period until the current sense signal Vs reaches the output signal Eout. Therefore, in either case, the operation of the first embodiment is possible. Also in the second embodiment, the operation of the present invention can be performed either when the input voltage Vin is higher than the output voltage Vout or when the input voltage Vin is lower than the output voltage Vout. Of course.

In addition, in this embodiment, although the 1st period T1 was made the same as the fundamental period T, it is a matter of course that the case where 1st period T1 differs from the fundamental period T is also included.

In addition, in this embodiment, although the 2nd period T2 is n times the 1st period T1, and the value of n is two or more natural numbers, it is not limited to this form. Of course, n must be a real number larger than 1. For example, when the basic period T is divided to obtain the first period T1, n can be made real. In this case, assuming that the first period T1 can be obtained by dividing the basic period T by two, and the second period T2 can be obtained by dividing the basic period T by five minutes. The two cycles T2 become 2.5 times the first cycle T1. Note that even if the cycle itself of the clock signal CLK is modulated between the first period T1 and the second period T2, n can of course be made real.

In addition, of course, in this embodiment, the compensation signal for control stabilization may be applied to the current sense signal Vs and the output signal Eout.

In addition, in this embodiment, although the 2nd period T2 was set as the fixed value which has the period four times the 1st period T1, it is not limited to this aspect. Of course, the second period T2 may dynamically control the relationship between the input voltage and the output voltage and the change of the output load. For example, if the variable control to reduce the second period T2 due to a change in the output load occurs, the period of the state 3 can be reduced, so that the followability of the DC-DC converter can be improved. In addition, as the difference voltage between the input voltage Vin and the output voltage Vout decreases, the second period T2 is increased, and as the difference voltage increases, the dynamically variable control is made to decrease the second period T2. This makes it possible to reduce the number of switching more.

In addition, in 1st Embodiment, although the abundance ratio of 1st periodic operation TO1 and 2nd periodic operation TO2 is 1: 1, it is not limited to this form, Abundance ratio can be set to arbitrary values. Of course it is. Then, by controlling the existence ratio of the first periodic operation TO1 and the second periodic operation TO2 variably, the time ratio of the state 3 to the entire state can be adjusted. For example, the first periodic operation TO1 and the second periodic operation TO2 are performed by TO1, TO1, TO2, TO1... By repeating in the order described above, when the existence ratio of the second periodic operation TO2 is lowered, the same effect as that of shortening the period of the state 3 can be obtained.

In the present embodiment, the transistors FET2 and FET4 are used as the synchronous rectification elements. However, the present invention is not limited to this embodiment and may be rectified using a diode element. For example, the structure which replaces at least one of transistors FET2 and FET4 with a diode, and the structure which has a diode in parallel with at least one of transistors FET2 and FET4 may be sufficient.

In addition, in this embodiment, although FET1, FET2, FET3, and FET4 are N type FET in FIG. 1, it is not limited to this form, Any or all of FET1, FET2, FET3, FET4 is P type. It goes without saying that the configuration may be replaced with a FET.

In addition, the current sense signal Vs is not limited to the type of detecting the inductor current IL flowing through the choke coil L1, but may be a type of detecting the current flowing in at least one of the transistors FET1 and FET3. Of course.

In addition, in 1st and 2nd embodiment, in the 2nd periodic operation TO2, since the switching from the state 1 to the state 3 is performed, the increase inclination of the inductor current IL is slowed and peak-to-tolerance is carried out. Although it is said that the peak current value can be prevented from being large, it is not limited to this form. The reduction inclination of the inductor current IL may be slowed down by switching from the state 2 to the state 3. Accordingly, since the bottom current value of the inductor current IL can be prevented from increasing, the second period T2 can be made larger than the first period T1.

In the first and second embodiments, the clock signal CLK is used for the step-up / down DC-DC converter, but is not limited to this embodiment. The DC-DC converter switches to the step-down DC-DC converter when the input voltage Vin is higher than the output voltage Vout, and the boost-type DC-DC converter when the input voltage Vin is lower than the output voltage Vout. It is a matter of course that the clock signal CLK can be used in common in these DC-DC converters when the structure is switched.

In addition, the control circuits 11 and 11b of this embodiment may be comprised by a single or a plurality of semiconductor chips. It goes without saying that the DC-DC converter 1 may be configured by a single or a plurality of semiconductor chips, or may be configured as a module.

In addition, although the DC-DC converter 1b of 3rd Embodiment is voltage-mode controlled, it is not limited to this form. A point of the invention according to the third embodiment is to switch the step-up operation and the step-up operation according to the comparison result between the output voltage and the input voltage. Therefore, it is a matter of course that the current mode may be controlled.

In the third embodiment, although the transistors FET1b and FET4b are P-type transistors, they are not limited to this embodiment. Since the polarity of the body diode of the transistor FET1b needs to be in the forward direction from the terminal Tx to the input terminal Tin, of course, it may be an N-type transistor.

In addition, although the soft start operation | movement at the time of the start of the DC-DC converter 1b was demonstrated in 3rd Embodiment, it is not limited to this form. It goes without saying that the soft start control of gradually decreasing the output voltage Vout from the predetermined set voltage to zero at the end of the DC-DC converter 1b can be performed. In this case, the voltage boosting operation is performed in a period in which the output voltage is higher than the voltage, and the output voltage is lower than the output voltage.

In addition, transistor FET1 is an example of a first switching element, transistor FET2 is an example of a first rectifying element, transistor FET4 is an example of a second rectifying element, transistor FET3 is an example of a second switching element, The choke coil L1 is an example of an inductance element, and the control circuit 11 is an example of each control part. In addition, transistor FET1b is an example of a first switching element, transistor FET2b is an example of a second switching element, transistor FET3b is an example of a third switching element, transistor FET4b is an example of a fourth switching element, The PMW control circuit PMW1 is an example of the control signal generation circuit, the voltage comparator COMP2 is an example of the comparator, and the AND circuit AND1 is an example of each of the mask circuits.

According to the control method of the step-up / down DC-DC converter, the step-up / down DC-DC converter, and the control method of the step-down DC-DC converter of the present invention, firstly, a switching element is provided while suppressing the peak-to-peak current value of the inductor current. It is possible to provide a step-down type DC-DC converter capable of lowering the average switching frequency of and increasing the efficiency. Secondly, it becomes possible to provide a step-up / down DC-DC converter capable of performing a step-up operation while realizing both soft start control and prevention of dark current.

Claims (18)

A first switching element connected between the voltage input terminal and one terminal of the inductance element, A first rectifying element connected between a reference potential and one terminal of the inductance element,  A second rectifying element connected between the voltage output terminal and the other terminal of the inductance element, A second switching element connected between the reference potential and the other terminal of the inductance element In the control method of the step-up DC-DC converter having a, A first state in which the first and second switching elements are on, a second state in which the first and second switching elements are off, and the first switching element is in an on state and the second state Each of the third states in which the switching element is turned off, A first periodic operation including the second state and performed in a predetermined first period, and a second periodic operation including the first state and the third state and performed in a second period greater than the first period. A control method of a step-up type DC-DC converter, characterized in that. The method of claim 1, wherein the first periodic operation is performed by: Starting the first periodic operation by being set to the first state; Switching from the first state to the second state as the current of the inductance element reaches a predetermined value Control method of a step-up type DC-DC converter comprising a. 2. The control method according to claim 1, wherein the first periodic operation comprises starting the first periodic operation by being set to the second state. The method of claim 1, wherein the second periodic operation is performed by: Starting the second periodic operation by being set to the first state; Switching from the first state to the third state as the current of the inductance element reaches a predetermined value Control method of a step-up type DC-DC converter comprising a. 5. The control method according to claim 4, wherein the second period is a period of n times (n is a real number greater than 1) of the first period. The method of claim 5, wherein n is a natural number of two or more. The method of claim 1, wherein the first rectifying device is a third switching device, The second rectifying element is a fourth switching element, In the first state, the third and fourth switching elements are turned off, In the second state, the third and fourth switching elements are turned on, And in the third state, the fourth switching device is turned on and the third switching device is turned off. A first switching element connected between the voltage input terminal and one terminal of the inductance element, A first rectifying element connected between a reference potential and one terminal of the inductance element, A second rectifying element connected between the voltage output terminal and the other terminal of the inductance element, A second switching element connected between the reference potential and the other terminal of the inductance element; A first state in which the first and second switching elements are on, a second state in which the first and second switching elements are off, and the first switching element is in an on state and the second state Control unit for controlling each of the third states in which the switching element is turned off Including; A first periodic operation including the second state and performed in a predetermined first period, and a second periodic operation including the first state and the third state and performed in a second period greater than the first period. A control circuit of a step-up / down DC-DC converter, characterized in that. The method of claim 8, further comprising a third switching device as the first rectifying device, A fourth switching element as the second rectifying element, The control unit, In the first state, the third and fourth switching elements are turned off, In the second state, the third and fourth switching elements are turned on, The control circuit of the step-up / down DC-DC converter, wherein in the third state, the fourth switching device is turned on and the third switching device is turned off. A first switching element connected between the voltage input terminal and one terminal of the inductance element, A first rectifying element connected between a reference potential and one terminal of the inductance element, A second rectifying element connected between the voltage output terminal and the other terminal of the inductance element, A second switching element connected between the reference potential and the other terminal of the inductance element; A first state in which the first and second switching elements are on, a second state in which the first and second switching elements are off, and the first switching element is in an on state and the second state Control unit for controlling each of the third states in which the switching element is turned off Including; A first periodic operation including the second state and performed in a predetermined first period, and a second periodic operation including the first state and the third state and performed in a second period greater than the first period. Step-up-type DC-DC converter, characterized in that. A first switching element connected between a voltage input terminal and a first terminal of an inductance element, the first switching element having an antiparallel diode connected from the first terminal of the inductance element in a direction of the voltage input terminal; A second switching element connected between a reference potential and the first terminal of the inductance element, A third switching element connected between the reference potential and the second terminal of the inductance element, A fourth switching element connected between the voltage output terminal and the second terminal of the inductance element, A soft start control circuit for outputting a soft start signal whose value rises or falls with time; An error amplifier for amplifying an error between a reference voltage defining a set voltage of an output voltage, a lower one of the soft start signals, and the output voltage; In a period in which the output voltage is lower than the input voltage, the first state in which the first and third switching elements are turned on, and the second state in which the second and fourth switching elements are turned on, Alternately depending on the output of the error amplifier, In the period in which the output voltage is higher than the input voltage, the first switching device is kept in an on state, the second switching device is in an off state, and the third switching device and the fourth switching device are connected to each other. A switching control circuit which alternately turns on according to the output of the error amplifier Control circuit of the step-up-type DC-DC converter comprising a. The method of claim 11, wherein the switching control circuit, A control signal generation circuit for outputting a control signal having a pulse width according to the magnitude of the output signal of the error amplifier; A comparator for comparing the output voltage and the input voltage; According to the result of the comparator, a mask circuit for passing the control signal when the output voltage is lower than the input voltage, and masks the control signal when the output voltage is higher than the input voltage Control circuit of the step-up-type DC-DC converter comprising a. 13. The method of claim 12, wherein the output of the comparator is at a low level in a period in which the output voltage is higher than the input voltage, And the mask circuit is a logical AND circuit. The method of claim 11, wherein the error amplifier, A first terminal having a first polarity and to which the output voltage is input; A second terminal having a second polarity and to which the reference voltage is input; A third terminal having a second polarity and to which the soft start signal is input; Control circuit of the step-up-type DC-DC converter comprising a. The method of claim 12, wherein the error amplifier, A first terminal having a first polarity and to which the input voltage is input; A second terminal having a second polarity and to which the reference voltage is input; A third terminal having a second polarity and to which the soft start signal is input; Control circuit of the step-up-type DC-DC converter comprising a. The method of claim 13, wherein the error amplifier, A first terminal having a first polarity and to which the output voltage is input; A second terminal having a second polarity and to which the reference voltage is input; Control circuit of the step-up-type DC-DC converter comprising a. A first switching element connected between the voltage input terminal and the first terminal of the inductance element, A second switching element connected between a reference potential and the first terminal of the inductance element, A third switching element connected between the reference potential and a second terminal of the inductance element, A fourth switching element connected between the voltage output terminal and the second terminal of the inductance element In the control method of the step-up DC-DC converter comprising: Turning off the first to fourth switching elements; In response to a start command, alternately performing a first state in which the first and third switching elements are turned on, and a second state in which the second and fourth switching elements are turned on; As the output voltage becomes higher than the input voltage, the first switching element is kept in an on state and the second switching element is in an off state, and at the same time the third switching element is in accordance with the output of the error amplifier. Alternately turning on the fourth switching element Control method of a step-up type DC-DC converter comprising a. A first switching element connected between the voltage input terminal and the first terminal of the inductance element, the first switching element having an anti-parallel diode conducting from the first terminal of the inductance element in the direction of the voltage input terminal; A second switching element connected between a reference potential and said first terminal of said inductance element, A third switching element connected between the reference potential and a second terminal of the inductance element, A fourth switching element connected between the voltage output terminal and the second terminal of the inductance element, A soft start control circuit for outputting a soft start signal whose value rises or falls with time; An error amplifier which amplifies an error between a reference voltage for determining a set voltage of an output voltage and a lower one of the soft start signals and the output voltage; In a period in which the output voltage is lower than the input voltage, the first state in which the first and third switching elements are turned on, and the second state in which the second and fourth switching elements are turned on, Alternately depending on the output of the error amplifier, In the period in which the output voltage is higher than the input voltage, the first switching device is kept in an on state, the second switching device is in an off state, and the third switching device and the fourth switching device are connected to each other. A switching control circuit which alternately turns on according to the output of the error amplifier Step-up-type DC-DC converter comprising a.

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