KR20070118445A - Data compensation circuit and display device having the same - Google Patents

Abstract

A data compensation circuit and a display device having the same are provided to reduce an overall size of a memory by compressing frame data before storing the frame data in the memory. A memory(110) stores previous compression data from previous frame data. A decoder(120) extracts the previous compression data from the memory and outputs the extracted data. A codec(130) compresses current frame data into current compression data and stores the current compression data in the memory. The codec extracts the current compression data. A first processor(140) outputs a first difference value between the previous and current extracted data. The second processor(150) outputs the previous extracted data based on the first difference value and the current frame data. A compensator(160) compensates for the current frame data based on the previous extracted data and the current frame data and outputs current compensation data.

Description

DATA COMPENSATION CIRCUIT AND DISPLAY DEVICE HAVING THE SAME}

1 is a block diagram illustrating a data compensation circuit according to an exemplary embodiment of the present invention.

2 and 3 are graphs showing voltages and luminances corresponding to current frames compensated by the data compensation circuit shown in FIG. 1.

4 is a block diagram illustrating a data compensation circuit according to another exemplary embodiment of the present invention.

FIG. 5 is an internal block diagram of the compensator shown in FIG. 4.

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: data compensation circuit 110: memory

120: decoding unit 130: code decoding unit

140: first processing unit 150: second processing unit

160: compensation unit 300: display unit

400: gate driving circuit 500: data driving circuit

600: timing controller 1000: liquid crystal display device

The present invention relates to a data compensation circuit and a display device having the same, and more particularly, to a data compensation circuit and a display device having the same, which can improve productivity and prevent data corruption.

In general, a liquid crystal display device includes two display substrates and a liquid crystal layer interposed therebetween. The liquid crystal display device displays a desired image by applying an electric field to the liquid crystal layer, and controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field.

As such liquid crystal display devices are widely used as display screens of televisions as well as display devices of computers, the necessity of realizing moving images is increasing. However, the conventional liquid crystal display device is difficult to implement a video because the response speed of the liquid crystal is slow.

Specifically, since the response speed of the liquid crystal molecules is slow, it takes some time for the voltage charged in the liquid crystal capacitor to reach a target voltage (that is, a voltage capable of obtaining desired luminance). In particular, when the difference between the previous voltage and the target voltage already charged in the liquid crystal capacitor in the previous frame is large, applying only the target voltage from the beginning may not reach the target voltage during the 1H time when the switching element is turned on.

Therefore, the conventional liquid crystal display device adopts a DCC (Dynamic Capacitance Compensation) method to speed up the response speed of the liquid crystal. In the DCC method, a response voltage of the liquid crystal is increased by applying a correction voltage to the current frame in consideration of the target voltage of the current frame and the previous voltage of the previous frame.

However, the liquid crystal display adopting the DCC method requires a frame memory for storing the previous voltage of the previous frame. At this time, the number and size of the frame memories lower the productivity of the liquid crystal display and increase the manufacturing cost.

Accordingly, it is an object of the present invention to provide a data compensation circuit for reducing the memory size to improve productivity and preventing data loss.

Further, another object of the present invention is to provide a display device having the data compensation circuit described above.

The data compensation circuit according to the present invention includes a memory, a decoder, a code decoder, a first processor, a second processor, and a compensator. The memory stores previous compressed data compressed from previous frame data during the previous frame, and the decoder restores the previous compressed data read from the memory during the current frame and outputs previous reconstructed data. The code decoder compresses current frame data into current compressed data during the current frame, stores the current frame data in the memory, restores the current compressed data, and outputs current decompressed data.

The first processing unit outputs a first difference value between the previous restoration data and the current restoration data, and the second processing unit generates previous restoration data based on the first difference value and the current frame data. The compensator compensates for the current frame data based on the previous restoration data and the current frame data, and outputs current compensation data.

The display device according to the present invention includes first and second memories, first and second decoders, code decoders, first to fourth processing units, and compensation units. The first memory stores the n-2 th compressed data compressed from the n-2 th frame data during the n-1 th frame (where n represents the current frame), and the n-2 previously stored during the n th frame. Outputs the first compressed data, and stores the n−1 th compressed data compressed from the n−1 th frame data. The second memory stores the n-1 th compressed data during the n-1 th frame and outputs the n-1 th compressed data previously stored during the n th frame.

The first decoder decompresses the n-2th compressed data during the nth frame and outputs n-2th decompressed data, and the second decoder decompresses the n-1th compressed data during the nth frame. Output the n-1th reconstruction data. The code decoder compresses the n-th frame data into the n-th compressed data during the n-th frame and stores it in the second memory, restores the n-th compressed data, and outputs n-th decompressed data.

The first processing unit outputs a first difference value between the n-2th reconstruction data and the nth reconstruction data, and the second processing unit is based on the first difference value and the nth frame data n-2. First restore data. The third processing unit outputs a second difference value between the n-th recovery data and the n-th recovery data, and the fourth processing unit outputs n-1 based on the second difference value and the n-th frame data. First restore data. The compensator compensates for the n-1 th restoring data based on the n-2 th restoring data, the n-1 th restoring data, and the n th frame data, and outputs an n-1 th restoring data. .

According to such a data compensating circuit and a display device having the same, since the compressed data is stored in the memory, the total size of the memory can be reduced, and in the case of displaying a still picture, the current frame data without undergoing compression and restoration is output. Data corruption can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a data compensation circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the data compensation circuit 100 according to an exemplary embodiment of the present invention may include a memory 110, a decoder 120, a code decoder 130, a first processor 140, and a second processor ( 150 and the compensation unit 160.

The memory 110 stores previously compressed data Fc (n-1) compressed from the previous frame data F (n-1). As an example of the present invention, if the previous frame data F (n-1) is 24 bits, the previous compressed data Fc (n-1) is 8 bits compressed to 1/3. Thus, the memory 110 has a size smaller than 2 ^m (where m is the number of bits of the previous frame data F (n-1)). As an example of the present invention, when the previous frame data F (n-1) is 24 bits, the memory 110 has a size of 2 ⁸ . As described above, since the compressed data of less than one frame is stored in the memory 110, the size of the memory 110 can be reduced.

The decoder 120 reads the previous compressed data Fc (n-1) previously stored in the memory 110 during the current frame, restores the previous compressed data Fc (n-1), and restores the previous. Output the data Fd (n-1). Specifically, the decoder 120 restores the previous compressed data Fc (n-1) composed of m / 3 bits to the previous decompressed data Fd (n-1) composed of m bits.

Meanwhile, the code decoder 130 receives current frame data F (n) during the current frame and compresses the current frame data F (n) into current compressed data Fc (n). After the storage in the memory 110. As an example of the present invention, the current frame data F (n) is composed of m bits, and the current compressed data Fc (n) is composed of m / 3 bits. In addition, the code decoder 130 restores the current compressed data Fc (n) during the current frame and outputs current decompressed data Fd (n).

The first processing unit 140 outputs a first difference value ΔFd (n) between the previous restoration data Fd (n-1) and the current restoration data Fd (n), and the second processing unit 150 generates the previous reconstruction data Fd` (n-1) based on the first difference value ΔFd (n) and the current frame data F (n). Specifically, the second processing unit 150 adds the first difference value ΔFd (n) to the current frame data F (n) to restore the previous restoration data Fd ′ (n-1). Create In the case of a still picture, the current restoration data Fd (n) is equal to the previous restoration data Fd (n-1), so that the first difference value ΔFd (n) becomes zero. In this case, the second processor 150 outputs the previous restoring data Fd` (n-1) that is the same as the current frame data F (n).

The compensator 160 compensates the current frame data F (n) based on the previous restoration data Fd` (n-1) and the current frame data F (n) to present the current frame data F (n). The compensation data F` (n) is output. In detail, the compensator 160 is configured to set the current value if the second difference between the previous restoration data Fd ′ (n-1) and the current frame data F (n) is less than or equal to a preset first reference value. The current compensation data F '(n) having the same value as the frame data F (n) is output. Therefore, in the case of a still picture, since the first difference value ΔFd (n) is 0, the previous restoration data Fd ′ (n-1) has the same value as the current frame data F (n). Have

In the current frame, the current frame data F (n) which is not compressed or decompressed is output as it is. As a result, damage to the still image can be prevented by displaying an image using the raw current frame data F (n).

Meanwhile, when the second difference value is greater than the first reference value, the compensation unit 160 overdrives the current compensation data F ′ (n) by a preset correction value than the current frame data F (n). )

Hereinafter, current compensation data overdriven by the compensation unit 160 will be described in detail with reference to FIGS. 2 and 3.

2 and 3 are graphs showing voltages and luminances corresponding to current compensation data compensated by the data compensation circuit shown in FIG. 1. 2 and 3, the x axis represents time and the y axis represents voltage and luminance. Here, the voltage represents a voltage applied to the liquid crystal layer every frame, and the luminance represents the brightness of light passing through the liquid crystal layer.

Referring to FIG. 2, previous frame data corresponds to a first target voltage Vt1, and current frame data corresponds to a second target voltage Vt2 that is higher than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 is greater than a preset reference value, even if the second target voltage Vt2 is applied to the liquid crystal layer, the desired target luminance Lt in one frame is achieved. Hard to reach In order to solve this problem, the compensator 160 (shown in FIG. 1) may set the second target voltage Vt2 higher than the second target voltage Vt2 in the current frame n. Overdrive with). Therefore, in the current frame n, the third target voltage Vt3 is applied to the liquid crystal layer, and as a result, the rising time is reduced to reach the desired target luminance Lt in one frame.

Referring to FIG. 3, previous frame data corresponds to a first target voltage Vt1, and current frame data corresponds to a second target voltage Vt2 lower than the first target voltage Vt1. When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 is greater than a preset reference value, even if the second target voltage Vt2 is applied to the liquid crystal layer, the desired target luminance Lt in one frame is achieved. Hard to reach In order to solve this problem, the compensator 160 (shown in FIG. 1) has a third target voltage Vt3 which is lower than the second target voltage Vt2 in the current frame n. Overdrive with). Therefore, in the current frame n, the third target voltage Vt3 is applied to the liquid crystal layer, and as a result, the rising time is reduced to reach the desired target luminance Lt in one frame.

In this way, the response speed of the liquid crystal can be improved by applying the overdried voltage to the liquid crystal layer.

4 is a block diagram illustrating a data compensation circuit according to another exemplary embodiment of the present invention, and FIG. 5 is an internal block diagram of the compensation unit illustrated in FIG. 4.

Referring to FIG. 4, the data compensating circuit 200 according to another exemplary embodiment of the present invention may include first and second memories 210 and 220, first and second decoders 230 and 240, and a code decoder. 250, first, second, third and fourth processing units 260, 270, 280, and 290 and a compensating unit 295.

The first memory 210 has n-second compressed data Fc (n-2) compressed from n-second frame data F (n-2), where n represents a current frame. The n-1 th compressed data Fc (n-1), which is compressed from the n-1 th frame data F (n-1), is stored in the second memory 220. The first memory 210 outputs the n-2 th compressed data Fc (n-2) previously stored for the n th frame, and then the n-1 th compressed data Fc (n-1). Save it. The second memory 220 outputs the n−1 th compressed data Fc (n−1) previously stored during the n th frame. As an example of the present invention, when the n-2 th and n-1 th frame data consists of m bits, the n-2 th and n-1 th compressed data consists of m / 3 bits. The first and second memories 210 and 220 have a size smaller than 2 ^m . In one embodiment of the present invention, the first and second memories 210 and 220 have a size of 2 ^{m / 3} .

The first decoder 230 restores the n-second compressed data Fc (n-2) during the n-th frame, and outputs n-th reconstructed data Fd (n-2). The second decoder 240 reconstructs the n−1 th compressed data Fc (n−1) during the n th frame and outputs n−1 th recovered data Fd (n−1). As an example of the present invention, the first and second decoders 230 and 240 may include the n-2 and n-1 compressed data Fc (n-2) and Fc (n-1) composed of m / 3 bits. Are restored to the n-th and n-th reconstruction data Fd (n-2) and Fd (n-1) respectively composed of m bits.

The code decoder 250 receives n-th frame data F (n) during the n-th frame, and receives the n-th frame data F (n) from the n-th compressed data Fc (n). Compressed to provide to the second memory 220. Also, the code decoder 250 restores the nth compressed data Fc (n) during the nth frame and outputs nth decompressed data Fd (n).

The first processor 260 outputs a first difference value ΔFd (n-2) between the n−2th reconstruction data Fd (n-2) and the nth reconstruction data Fd (n). The second processor 270 performs n-th reconstruction data Fd` based on the first difference value ΔFd (n-2) and the n-th frame data F (n). n-2)). Here, the second processing unit 270 adds the first difference value ΔFd (n-2) to the nth frame data F (n) to restore the n−2th reconstruction data Fd ′ ( n-2)).

The third processing unit 280 outputs a second difference value ΔFd (n-1) between the n−1th restored data Fd (n−1) and the n−th restored data Fd (n). The fourth processing unit 290 is based on the second difference value ΔFd (n-1) and the nth frame data F (n), and the n−1th reconstruction data Fd ′ ( n-1)). Here, the fourth processor 290 adds the second difference value ΔFd (n−1) to the nth frame data F (n) to restore the n−1th reconstruction data Fd ′ ( n-1)).

The compensator 295 is configured to perform the n-2 th reconstruction data Fd` (n-2), the n-1 th reconstruction data Fd` (n-1), and the n th frame data F. Based on (n)), the n-1 th reconstruction data Fd` (n-1) is compensated and the n-1 th compensation data F` (n-1) is output.

As shown in FIG. 5, the compensator 295 includes first and second compensators 296 and 297. The first compensator 296 uses n− based on the n−2 th restoring data Fd` (n-2) and the n−1 th restoring data Fd ′ (n-1). The first compensation restoration data Fd`` (n-1) is generated, and the second compensation unit 297 performs the n-1th compensation restoration data Fd`` (n-1) and the nth Based on the frame data F (n), the n−1 th compensation data F ′ (n−1) is generated.

Specifically, the first compensator 296 may include a third of the n-2 th reconstruction data Fd` (n-2) and the n-1 th reconstruction data Fd` (n-1). If the difference value is equal to or less than the first predetermined reference value, the n-th compensation compensation data Fd `` (n-1) having the same value as the n-second recovery data Fd` (n-2). Outputs and the n-1 th compensation restoration data Fd `` (n-1) overdried from the n-1 th restoring data Fd` (n-1) if equal to or greater than the first reference value. Outputs

In the case of a still picture, since the first and second difference values ΔFd (n-2) and ΔFd (n-1) are 0, the n-2 and n-1 reconstruction data Fd` (n-2) ) And Fd` (n-1) have the same value as the n frame data F (n). In addition, since the third difference value becomes 0, the first compensator 296 stores the n-1 compensation restoring data Fd`` (n−) having the same value as the n frame data F (n). 1))

On the other hand, the second compensation unit 297 has the n-th compensation data (Fd `` (n-1)) is smaller than the second reference value, the n-th frame data (F (n)) is a third When the reference value is larger than the reference value, the n-1 compensation data F ′ (n-1) is generated by a second correction value than the n−1 th compensation restoration data Fd ″ (n−1), and the n The n-th compensation compensation data when the first compensation recovery data Fd `` (n-1) is equal to or greater than the second reference value or the n-th frame data F (n) is equal to or less than the third reference value; The n-th compensation data F` (n-1) equal to (Fd`` (n-1)) is generated.

In the case of a still picture, the second compensator 297 performs the n-1 th compensation data F ′ (n-1), which is the same as the n−1 th compensation restoration data Fd ″ (n−1). Create Here, the n-th compensation data (Fd `` (n-1)) has the same value as the n-th frame data (F (n)), and thus, the n-th compensation data F` ( n-1)) has the same value as the n-th frame data F (n).

As described above, when the still image is displayed, the first and second compensators 296 and 297 output the n-th frame data F (n) which is not compressed or decompressed. As a result, damage to the still image can be prevented by displaying an image using the unprocessed n-th frame data F (n).

6 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the liquid crystal display device 1000 according to an exemplary embodiment of the present invention may include a display unit 300 for displaying an image, a gate driving circuit 400 driving the display unit 300, and a data driving circuit ( 500, a gray voltage generator 800 connected to the data driving circuit 500, and a timing controller 600 for controlling driving of the gate driving circuit 400 and the data driving circuit 500.

The display unit 300 includes a plurality of gate lines GL1 to GLn for receiving a gate voltage and a plurality of data lines DL1 to DLm for receiving a data voltage. The display unit 300 has a plurality of pixel regions defined in a matrix form by the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm, and pixels 310 are provided in each pixel region. . The pixel 310 includes a thin film transistor 311, a liquid crystal capacitor C _LC , and a storage capacitor C _ST .

As shown in the figure, a gate electrode of the thin film transistor 311 is connected to a first gate line GL1, a source electrode is connected to a first data line DL1, and a liquid crystal capacitor C _LC . The storage capacitor C _ST is connected in parallel with the drain electrode of the thin film transistor 311.

For example, the display unit 300 may include a lower substrate, an upper substrate facing the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate.

The lower substrate includes pixel electrodes, which are first electrodes of the plurality of gate lines GL1 to GLn, the plurality of data lines DL1 to DLm, the thin film transistor 311, and the liquid crystal capacitor C _LC . . Accordingly, the thin film transistor 311 applies the data voltage to the pixel electrode in response to the gate voltage.

The common electrode, which is the second electrode of the liquid crystal capacitor C _LC , is formed on the upper substrate, and a common voltage is applied to the common electrode. The liquid crystal layer interposed between the pixel electrode and the common electrode serves as a dielectric. Therefore, the liquid crystal capacitor C _LC is charged with a voltage corresponding to the potential difference between the data voltage and the common voltage.

The gate driving circuit 400 is electrically connected to a plurality of gate lines GL1 to GLn of the display unit 300 to provide the gate voltages to the plurality of gate lines GL1 to GLn. The data driving circuit 500 is electrically connected to a plurality of data lines DL1 to DLm provided in the display unit 300, and selects a gray scale voltage from the gray voltage generator 800 to select the plurality of data. It is provided as the data voltage on the lines DL1 to DLm.

The timing controller 600 receives various control signals, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock MCLK, a data enable signal DE, and the like. The timing controller 600 outputs a gate control signal CONT1 and a data control signal CONT2 based on the various control signals.

The gate control signal CONT1 is provided to the gate driving circuit 400 as a signal for controlling the operation of the gate driving circuit 400. The gate control signal CONT1 may be a vertical start signal for starting the operation of the gate driving circuit 400, a gate clock signal for determining an output timing of the gate voltage, and an output enable signal for determining an on pulse width of the gate voltage. And the like.

The gate driving circuit 400 outputs the gate voltage formed by a combination of a gate on voltage Von and a gate off voltage Voff in response to the gate control signal CONT1 from the timing controller 600.

The data control signal CONT2 is provided to the data driving circuit 500 as a signal for controlling the operation of the data driving circuit 500. The data control signal CONT2 is a horizontal start signal for starting the operation of the data driving circuit 500, an inversion signal for inverting the polarity of the data voltage, and an output for determining when the data voltage is output from the data driver. An indication signal or the like.

In addition, the timing controller 600 is formed in a chip form, and the timing controller 600 includes a data compensation circuit 100 shown in FIG. 1. In particular, since the compressed data is stored in the memory 110 (refer to FIG. 1), the total size of the memory 110 is reduced, and as a result, the memory 110 is embedded in the timing controller 600. You can.

The data compensation circuit 100 receives the current frame data F (n) from an external graphic controller (not shown) in the current frame and compensates with the current compensation data F ′ (n). The data driving circuit 500 receives the current compensation data F ′ (n) in response to the data control signal CONT1 from the timing controller 600, and receives the gray level voltage generator 800 from the gray level voltage generator 800. The gradation voltage corresponding to the current compensation data F ′ (n) is selected among the gradation voltages, and is converted to the data voltage and output.

Thus, the display unit 300 displays an image in response to the data voltage and the gate voltage. In particular, in the case of a still picture, the current compensation data F ′ (n) is converted into a data voltage corresponding to the current frame data F (n) which has not been compressed or reconstructed. Images can be displayed using undamaged data.

According to such a data compensating circuit and a display device having the same, frame data is compressed and stored in a memory, and compressed data read from the memory is transmitted to a compensating unit after a recovery process.

Therefore, the overall size of the memory can be reduced, and as a result, the memory can be incorporated in the timing controller, thereby reducing the manufacturing cost of the display device and improving productivity.

In addition, when the still image is displayed, the image is displayed by using the current frame data which has not undergone the compression and restoration process, thereby preventing the still image from being damaged.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (17)

A memory in which previous compressed data compressed from previous frame data is stored; A decoder for restoring the previous compressed data read out from the memory during a current frame and outputting previous restored data; A code decoder which compresses current frame data into current compressed data during the current frame and stores the same in the memory, restores the current compressed data, and outputs current decompressed data; A first processor configured to output a first difference value between the previous restored data and the current restored data; A second processor configured to output previous restoration data based on the first difference value and the current frame data; And And a compensator for compensating the current frame data based on the previous restoration data and the current frame data to output current compensation data. The data compensation circuit of claim 1, wherein the previous restoration data is a value obtained by adding the first difference value to the current frame data. The display apparatus of claim 2, wherein the compensation unit outputs the current compensation data having the same value as the current frame data when a second difference between the previous restoration data and the current frame data is less than or equal to a preset first reference value. A data compensation circuit configured to output the current compensation data increased by a preset correction value than the current frame data when the first reference value is larger than the first reference value. The method of claim 3, wherein when the first difference value is 0, the second processor outputs the previous restoration data that is the same as the current frame data. And the current compensation data is the same as the current frame data. 2. The data compensation circuit according to claim 1, wherein the memory has a size smaller than 2 ^m (where m is the number of bits of the current frame data). 6. The data compensation circuit according to claim 5, wherein said memory has a size of 2 ^{m / 3} . The method of claim 6, wherein the decoding unit restores the previous compressed data composed of m / 3 bits to the previous decompressed data composed of m bits, And the code decoder compresses the current frame data consisting of m bits into the current compressed data consisting of m / 3 bits. a first memory in which n-2 compressed data compressed from n-2th frame data (where n represents a current frame) are stored in advance; a second memory in which n−1 th compressed data compressed from n−1 th frame data is pre-stored; a first decoder to decompress the n-2th compressed data during the nth frame and output the n-2th decompressed data; A second decoder for restoring the n-1th compressed data during the nth frame and outputting n-1th recovered data; A code decoder for compressing n-th frame data into the n-th compressed data during the n-th frame to the second memory, restoring the n-th compressed data, and outputting n-th decompressed data; A first processor configured to output a first difference value between the n-th recovery data and the n-th recovery data; A second processor for outputting n-th reconstruction data based on the first difference value and the n-th frame data; A third processor configured to output a second difference value between the n-th reconstruction data and the n-th reconstruction data; A fourth processing unit outputting the n-1th reconstruction data based on the second difference value and the nth frame data; And A compensator configured to compensate for the n-1 th restoring data based on the n-2 th restoring data, the n-1 th restoring data, and the n th frame data to output an n-1 th restoring data; And a data compensation circuit. 10. The method of claim 8, wherein the n-2th reconstruction data is a value obtained by adding the first difference value to the nth frame data, And the n-1th reconstruction data is a value obtained by adding the second difference value to the nth frame data. 9. The data compensation circuit according to claim 8, wherein the first and second memories have a size smaller than 2 ^m (where m is the number of bits of the n frame data). 11. The data compensation circuit of claim 10, wherein the first and second memories have a size of 2 ^{m / 3} . A data compensation circuit which generates current compensation data based on previous frame data and current frame data; A data driving circuit outputting a data voltage corresponding to the current compensation data in response to a data control signal; A gate driving circuit outputting a gate voltage in response to the gate control signal; And A display unit configured to display an image in response to the data voltage and the gate voltage; The data compensation circuit, A memory in which previously compressed data compressed from the previous frame data is stored; A decoder for restoring the previous compressed data read out from the memory during a current frame and outputting previous restored data; A code decoder which compresses the current frame data into current compressed data during the current frame and stores the current frame data in the memory, restores the current compressed data, and outputs current restored data; A first processor configured to output a first difference value between the previous restored data and the current restored data; A second processor configured to output previous restoration data based on the first difference value and the current frame data; And And a compensator for compensating the current frame data based on the previous restoration data and the current frame data to output current compensation data. The display device of claim 12, wherein the previous restoration data is a value obtained by adding the first difference value to the current frame data. 13. The display device according to claim 12, wherein the memory has a size smaller than 2 ^m (where m is the number of bits of the current frame data). The display device of claim 12, further comprising a timing controller configured to provide the data control signal to the data driver circuit in response to a control signal from an external device and to provide the gate control signal to the gate driver circuit. Device. The method of claim 15, wherein the timing controller is in the form of a chip, And the data compensation circuit is built in the timing controller. The display device of claim 12, wherein the display part includes a plurality of pixels arranged in a matrix form. Each pixel, A thin film transistor configured to output the data voltage in response to the gate voltage; And And a liquid crystal capacitor charging a potential difference between the data voltage and a preset reference voltage.

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