CN101089940B - Display apparatus having data compensating circuit - Google Patents

Display apparatus having data compensating circuit Download PDF

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Publication number
CN101089940B
CN101089940B CN2007101091277A CN200710109127A CN101089940B CN 101089940 B CN101089940 B CN 101089940B CN 2007101091277 A CN2007101091277 A CN 2007101091277A CN 200710109127 A CN200710109127 A CN 200710109127A CN 101089940 B CN101089940 B CN 101089940B
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China
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data
decompressed
packed
frame
current
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CN101089940A (en
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南亨植
朴东园
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Samsung Display Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020060073457A external-priority patent/KR20080012522A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Abstract

In a data compensating circuit and a display apparatus having the same, a previous compressed data compressed from a previous frame data is previously stored in a memory, a decoder decompresses the previous compressed data from the memory to output a previous decompressed data, a coder-decoder compresses a present frame data into a present compressed data to store the present compressed data in the memory and decompresses the present compressed data to output a present decompressed data. A first processor outputs a difference value between the previous decompressed data and the present decompressed data, a second processor adds the present frame data and the difference value to generate a previous re-decompressed data. A compensator outputs a present compensation data based on the previous re-decompressed data and the present frame data. Thus, the size of the memory may be reduced while preventing damage of data.

Description

Display device with data compensating circuit
The application requires the 2006-52607 korean patent application submitted on June 12nd, 2006 and the right of priority of the 2006-73457 korean patent application submitted on August 3rd, 2006, and this application all is disclosed in this for reference.
Technical field
The present invention relates to a kind of display device, more particularly, relate to a kind of display device with the data compensating circuit that can avoid corrupted data.
Background technology
Usually, LCD (LCD) comprises two display base plates and a liquid crystal layer that places between the described substrate.LCD is applied to liquid crystal layer with electric field, controlling optical transmission through liquid crystal layer by adjusting electric field intensity, thereby shows desired images.
Recently, LCD is widely used as display device, shows moving image to be used for computing machine, televisor etc.Yet traditional LCD is not suitable for showing moving image, and this is because response speed of liquid crystal is slower.
The response speed of liquid crystal molecule is because liquid crystal capacitor is charged to enough voltage to obtain the required time of display brightness of expectation slowly.Particularly, when the voltage difference between previous voltage that charges into liquid crystal capacitor and the target voltage is very big, when connecting on-off element, during the 1H cycle, liquid crystal capacitor is not charged to target voltage.Also can be like this even just target voltage is applied to capacitor from the beginning in 1H cycle.
For fear of this problem, traditional LCD adopts dynamic capacitance compensation (DCC) method, so that accelerate response speed of liquid crystal.According to the DCC method, based on the target voltage of present frame and the previous voltage of previous frame, during present frame, bucking voltage is applied to pixel, so that accelerate response speed of liquid crystal.
Yet in order to store the voltage of previous frame, in the traditional LCD that adopts the DCC method, other frame memory is necessary.As a result, owing to the quantity and the big or small productive rate reduction that causes LCD of frame memory, and manufacturing cost increases.
Summary of the invention
The invention provides a kind of can be by reducing memory size and avoiding corrupted data to improve the data compensating circuit of its productive rate.
The present invention also provides a kind of display device with above-mentioned data compensating circuit.
In one aspect of the invention, data compensating circuit comprises: storer, demoder, scrambler-demoder, first processor, second processor and compensator.Memory stores is from the data of previous frame compression, and during present frame, demoder decompresses to the previous packed data of reading from storer.During present frame, scrambler-demoder compresses current frame data, and current packed data is stored in the storer, and current packed data is decompressed with the output decompressed data.
First difference of the difference between first processor output previous decompressed data of indication and the current decompressed data, second processor had been exported before decompressed data once more based on first difference and current frame data.Compensator based on before once more decompressed data and current frame data the compensation current frame data, to export current offset data.
In another aspect of this invention, data compensating circuit comprises: first memory, second memory, scrambler, comparer, demoder, compensator and data selector.
In first memory, store in advance from (n-2) frame data (n-2) packed data of (wherein, n represents present frame), and will be stored in the second memory in advance from (n-1) packed data of (n-1) frame data.Scrambler is converted to the n packed data with the n frame data at n image duration, and comparer compares (n-2) packed data, (n-1) packed data and n packed data mutually, selects signal with output.
Demoder is condensed to n decompressed data, (n-1) decompressed data and (n-2) decompressed data with n packed data, (n-1) packed data and (n-2) packed data decompress(ion) respectively.Compensator is exported first offset data based on n decompressed data, (n-1) decompressed data and (n-2) decompressed data, and data selector is in response to selecting signal to export n frame data or first offset data as output data.
In another aspect of this invention, data compensating circuit comprises: first memory, second memory, first demoder, second demoder, scrambler-demoder, first processor, second processor, the 3rd processor, four-processor and compensator.First memory is stored (n-2) packed data from (n-2) frame data in (n-1) image duration, export (n-2) packed data of storage in advance image duration at n, and storage is from (n-1) packed data of (n-1) frame data.Second memory is stored (n-1) packed data in (n-1) image duration, and exports (n-1) packed data of storage in advance image duration at n.
First demoder decompresses (n-2) packed data to export (n-2) decompressed data at n image duration, and second demoder decompresses (n-1) packed data to export (n-1) decompressed data at n image duration.Scrambler-demoder is n frame data boil down to n packed data, so that the n packed data is stored in the second memory, and image duration n packed data decompress(ion) is condensed to the n decompressed data at n.
First difference of the difference between first processor output indication (n-2) decompressed data and the n decompressed data, second processor is exported (n-2) decompressed data once more based on first difference and n frame data.Second difference of the difference between the 3rd processor output indication (n-1) decompressed data and the n decompressed data, four-processor produces (n-1) decompressed data once more based on second difference and n frame data.Compensator is based on (n-2) decompressed data, (n-1) decompressed data and n frame data compensation (n-1) decompressed data once more once more once more, to export (n-1) offset data.
In another aspect of this invention, display device comprises: data compensating circuit, data drive circuit, gate driver circuit and display unit.Data compensating circuit receives the n frame data, to compensate the n frame data as output data image duration at n.Data drive circuit is converted to data voltage in response to data controlling signal with the data that compensate, to export this data voltage.Gate driver circuit is exported grid voltage in response to grid control signal.Display unit is in response to data voltage and grid voltage display image.
Data compensating circuit comprises: first memory, second memory, scrambler, comparer, demoder, compensator and data selector.
To be stored in advance the first memory from (n-2) packed data of (n-2) frame data compression, and will be stored in the second memory in advance from (n-1) packed data of (n-1) frame data compression.Scrambler is converted to the n packed data with the n frame data at n image duration, and comparer compares (n-2) packed data, (n-1) packed data and n packed data mutually, selects signal with output.
Demoder is condensed to n decompressed data, (n-1) decompressed data and (n-2) decompressed data with n packed data, (n-1) packed data and (n-2) packed data decompress(ion) respectively.Compensator is exported first offset data based on n decompressed data, (n-1) decompressed data and (n-2) decompressed data, and data selector is in response to selecting signal to export n frame data or first offset data as output data.
According to top description,, therefore can reduce the size of storer because packed data is stored in the storer.In addition, under the situation that shows the freeze frame image, output both be not compressed does not have decompressed current frame data yet, thereby avoids corrupt data.
Description of drawings
By the detailed description of considering below in conjunction with accompanying drawing, above-mentioned and other advantage of the present invention will become apparent, wherein:
Fig. 1 is the block diagram that illustrates according to the exemplary embodiment of data compensating circuit of the present invention;
Fig. 2 and Fig. 3 illustrate corresponding to the brightness of the present frame that compensates by the data compensating circuit shown in Fig. 1 and the curve map of voltage;
Fig. 4 is the block diagram that illustrates according to another exemplary embodiment of data compensating circuit of the present invention;
Fig. 5 is the internal frame diagram of the compensator shown in Fig. 4;
Fig. 6 is the block diagram that illustrates according to another exemplary embodiment of data compensating circuit of the present invention;
Fig. 7 is the internal frame diagram of the compensator shown in Fig. 6; With
Fig. 8 is the block diagram that the liquid crystal display with the data compensating circuit shown in Fig. 1 is shown.
Embodiment
Should be appreciated that, when mention a certain element or layer another element or layer " on ", " being connected to " or " being attached to " another element or when layer, this element or layer can be directly on another element or layer, be connected to or be attached to another element or layer, or have intermediary element or middle layer.On the contrary, when mention element another element or layer " on ", " being directly connected to " or " directly being attached to " another element or when layer, do not have intermediary element or middle layer.Carry throughout, identical label is represented components identical.As term used herein " and/or " comprise any one and all combinations of the project of listing of one or more association.
Should be appreciated that first, second waits and describes different elements, assembly, zone, layer and/or part although use term here, these elements, assembly, zone, layer and/or part should not be limited to these terms.These terms only are used to an element, assembly, zone, layer or part and another element, assembly, zone, layer or part are distinguished.So, under the situation that does not break away from instruction of the present invention, first element, first assembly, first area, ground floor or the first of discussing below can be called second element, second assembly, second area, the second layer and/or second portion.
Easyly can use the term in relevant space here in order to describe, for example " ... under ", " ... following ", " following ", " ... on ", " top " etc., to describe the relation of element shown in the accompanying drawing or feature and other (or a plurality of) element or feature.Should be appreciated that the term in relevant space is in order to comprise the different azimuth of the device in using or operating except the orientation that is described in the drawings.For example, if device in the accompanying drawings is reversed, then be described as be in other elements or feature " following " or " under " element will be positioned at thereafter on described other elements or the feature.So, exemplary term " ... under " can comprise " ... on " and " ... under " two kinds of orientation.Device can be by location (revolve turn 90 degrees or in other orientation) differently, and correspondingly explains the descriptor in the relevant space of using here.
Term used herein only is in order to describe the purpose of specific embodiment, is not in order to limit the present invention.Here employed singulative is intended to comprise equally plural form, unless context is indicated clearly.Will be further understood that term " comprises " and/or " comprising ", when using in this manual, the existence of its expression feature, integral body, step, operation, element and/or the assembly narrated does not exist or adds in one or more other feature, integral body, step, operation, element, assembly and/or their groups but do not get rid of.
Below, describe the present invention with reference to the accompanying drawings in detail.
Fig. 1 is the block diagram that illustrates according to the exemplary embodiment of data compensating circuit of the present invention.
With reference to Fig. 1, data compensating circuit 100 comprises: storer 110, demoder 120, scrambler-demoder 130, first processor 140, second processor 150 and compensator 160.
In storer 110, store in advance from the data Fc (n-1) of previous frame data F (n-1) compression.In the present embodiment, if frame data F (n-1) comprises 24 bits, then previous packed data Fc (n-1) comprises 1/3rd 8 bits that are compressed to frame data F (n-1).So storer 110 is less than 2 m(m represents the bit number of frame data F (n-1)).That is to say that when previous frame data F (n-1) comprised 24 bits, the size of storer 110 was 2 8Similarly, storage has the packed data of the data volume of the amount that is less than a frame in storer 110, thereby can reduce the size of storer 110.
During present frame, demoder 120 is read the previous packed data Fc (n-1) that is stored in advance in the storer 110, and previous packed data Fc (n-1) is decompressed to export previous decompressed data Fd (n-1).Particularly, demoder 120 is condensed to previous packed data Fc (n-1) decompress(ion) of m/3 bit the previous decompressed data Fd (n-1) of m bit.
During present frame, scrambler-demoder 130 receives current frame data F (n), and with current frame data F (n) the current packed data Fc of boil down to (n) so that current packed data Fc (n) is stored in the storer 110.Current frame data F (n) comprises the m bit, and current packed data Fc (n) comprises the m/3 Bit data.Frame scrambler-demoder 130 decompresses current packed data Fc (n) to export current decompressed data Fd (n) during present frame.
The first difference DELTA F d (n) between first processor 140 output previous decompressed data Fd (n-1) and the current decompressed data Fd (n), second processor 150 based on the first difference DELTA F d (n) and current frame data F (n) generation before once more decompression (re-decompressed) data Fd ' (n-1).Particularly, second processor 150 had been produced before once more decompressed data Fd ' (n-1) with the first difference DELTA F d (n) mutually with current frame data F (n).For freeze frame (free-frame) image, current decompressed data Fd (n) is identical with previous decompressed data Fd (n-1), thereby the first difference DELTA F d (n) equals zero.Therefore, exportable identical with current frame data F (n) before decompressed data Fd ' was (n-1) once more for second processor 150.
Compensator 160 based on before once more decompressed data Fd ' (n-1) and current frame data F (n) compensate current frame data F (n), to export current offset data F ' (n).Particularly, when before once more decompressed data Fd ' (n-1) and second difference between the current frame data F (n) during less than predetermined first reference value, the compensator 160 outputs current offset data F ' identical with current frame data F (n) is (n).Therefore, for the freeze frame image, the first difference DELTA F d (n) equals zero, thereby before decompressed data Fd ' was (n-1) identical with current frame data F (n) once more.
During present frame, output both be not compressed does not have decompressed current frame data F (n) yet.So, do not have processed current frame data F (n) to be used to display image, thereby avoid damaging the freeze frame image.
When described second difference during greater than described first reference value, compensator 160 outputs compare with current frame data F (n) increased the predetermined backoff value current offset data F ' (n).
Below, describe in detail by overdrive (overdrive) the current offset data of (increase or reduce) of compensator 160 with reference to Fig. 2 and Fig. 3.
Fig. 2 and Fig. 3 be illustrate with by the corresponding brightness of current offset data after the data compensating circuit shown in Fig. 1 compensation and the curve map of voltage.In Fig. 2 and Fig. 3, x axle express time, the y axle is represented voltage and brightness.Described voltage table is shown in the voltage that every frame is applied to liquid crystal layer, and the brightness through the light of liquid crystal layer is represented in described brightness.
With reference to Fig. 2, frame data is corresponding to the first target voltage Vt1, and current frame data is corresponding to the second target voltage Vt2 that is higher than the first target voltage Vt1.When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 during,, within a frame, can not obtain desired destination brightness Lt even second target voltage is applied to liquid crystal layer greater than predetermined reference value.In order to address this problem, compensator 160 (as shown in Figure 1) is overdrived (increase) to the 3rd target voltage Vt3 that is higher than the second target voltage Vt2 with the second target voltage Vt2 during present frame n.Thereby, during present frame n, the 3rd target voltage Vt3 is applied to liquid crystal layer, thus the rise time of the voltage of liquid crystal layer can be reduced, and can in a frame, obtain desired destination brightness Lt.
With reference to Fig. 3, frame data is corresponding to the first target voltage Vt1, and current frame data is corresponding to the second target voltage Vt2 that is lower than the first target voltage Vt1.When the voltage difference between the first target voltage Vt1 and the second target voltage Vt2 during,, within a frame, can not obtain desired destination brightness Lt even the second target voltage Vt2 is applied to liquid crystal layer greater than predetermined reference value.In order to address this problem, compensator 160 (as shown in Figure 1) is overdrived (reducing) to the 3rd target voltage Vt3 that is lower than the second target voltage Vt2 with the second target voltage Vt2 during present frame n.Thereby, during present frame n, the 3rd target voltage Vt3 is applied to liquid crystal layer, thereby can reduces the fall time of the voltage of liquid crystal layer, and can in a frame, obtain desired destination brightness Lt.
As mentioned above, the voltage of will overdrive (increase or reduce) is applied to liquid crystal layer, thereby improves the response speed of the liquid crystal molecule of liquid crystal layer.
Fig. 4 is the block diagram that illustrates according to another exemplary embodiment of data compensating circuit of the present invention.Fig. 5 is the internal frame diagram of the compensator shown in Fig. 4.
With reference to Fig. 4, data compensating circuit 200 comprises: first memory 210, second memory 220, first demoder 230, second demoder 240, scrambler-demoder 250, first processor 260, second processor 270, the 3rd processor 280, four-processor 290 and compensator 295.
In first memory 210, store (n-2) packed data Fc (n-2) in advance from (n-2) frame data F (n-2), will store in advance in the second memory 220 from (n-1) packed data Fc (n-1) of (n-1) frame data F (n-1).First memory 210 is exported (n-2) packed data Fc (n-2) of storage in advance at n image duration, and stores (n-1) packed data Fc (n-1).Second memory 220 is exported (n-1) packed data Fc (n-1) of storage in advance image duration at n.In the present embodiment, if each of (n-2) frame data and (n-1) frame data comprises the m bit, then each of (n-2) packed data and (n-1) packed data comprises the m/3 bit.Each of first memory 210 and second memory 220 is less than 2 mAs the example of present embodiment, the size of each of first memory 210 and second memory 220 is about 2 M/3
First demoder 230 decompresses (n-2) packed data Fc (n-2) to export (n-2) decompressed data Fd (n-2) at n image duration, and second demoder 240 decompresses (n-1) packed data Fc (n-1) to export (n-1) decompressed data Fd (n-1) at n image duration.In the present embodiment, first demoder 230 and second demoder 240 (n-2) decompressed data Fd (n-2) and (n-1) decompressed data Fd (n-1) of respectively (n-2) packed data Fc (n-2) and (n-1) packed data Fc (n-1) decompress(ion) of m/3 bit being condensed to the m bit.
Scrambler-demoder 250 receives n frame data F (n) at n image duration, and with n frame data F (n) boil down to n packed data Fc (n) so that n packed data Fc (n) is offered second memory 220.Scrambler-demoder 250 decompresses n packed data Fc (n) to export n decompressed data Fd (n) at n image duration.
The first difference DELTA F d (n-2) between first processor 260 output (n-2) decompressed data Fd (n-2) and the n decompressed data Fd (n), decompressed data Fd ' is (n-2) once more based on the first difference DELTA F d (n-2) and n frame data F (n) generation (n-2) for second processor 270.Second processor 270 is produced (n-2) mutually with the first difference DELTA F d (n-2) and n frame data F (n), and decompressed data Fd ' is (n-2) once more.
The second difference DELTA F d (n-1) between the 3rd processor 280 output (n-1) decompressed data Fd (n-1) and the n decompressed data Fd (n), decompressed data Fd ' is (n-1) once more based on the second difference DELTA F d (n-1) and n frame data F (n) generation (n-1) for four-processor 290.Four-processor 290 is produced (n-1) mutually with the second difference DELTA F d (n-1) and n frame data F (n), and decompressed data Fd ' is (n-1) once more.
Compensator 295 based on (n-2) once more decompressed data Fd ' (n-2), (n-1) once more decompressed data Fd ' (n-1) and n frame data F (n) compensate (n-1) once more decompressed data Fd ' (n-1), offset data F ' is (n-1) to export (n-1).
As shown in Figure 5, compensator 295 comprises: first compensator 296 and second compensator 297.First compensator 296 based on (n-2) once more decompressed data Fd ' (n-2) and (n-1) once more decompressed data Fd ' (n-1) produces (n-1) and compensates decompressed data F " (n-1).Second compensator 297 is based on (n-1) compensation decompressed data Fd " offset data F ' is (n-1) (n-1) to produce (n-1) with n frame data F (n).
Particularly, decompressed data Fd ' is (n-2) and (n-1) when three difference of decompressed data Fd ' between (n-1) is less than predetermined first reference value once more once more as (n-2), the output of first compensator 296 and (n-1) be (n-1) identical (n-1) compensation decompressed data Fd of decompressed data Fd ' once more " (n-1); and when the 3rd difference during greater than predetermined first reference value, first compensator 296 export from (n-1) once more decompressed data Fd ' (n-1) that (n-1) overdrive compensate decompressed data Fd " (n-1).
For the freeze frame image, each of the first difference DELTA F d (n-2) and the second difference DELTA F d (n-1) equals zero, thus (n-2) once more decompressed data Fd ' (n-2) and (n-1) once more (n-1) each of decompressed data Fd ' equal n frame data F (n).In addition, the 3rd difference equals zero, (n-1) compensation decompressed data Fd that 296 outputs of first compensator are identical with n frame data F (n) " (n-1).
Simultaneously, as (n-1) compensation decompressed data Fd " (n-1) less than second reference value and n frame data F (n) during greater than the 3rd reference value, second compensator 297 produces than (n-1) compensation decompressed data Fd " (n-1) (n-1) of big second offset offset data F ' (n-1).As (n-1) compensation decompressed data Fd " (n-1) greater than second reference value or n frame data F (n) during less than the 3rd reference value, second compensator 297 produces with (n-1) and compensates decompressed data Fd " offset data F ' is (n-1) for (n-1) identical (n-1).
For the freeze frame image, second compensator 297 produces and (n-1) compensation decompressed data Fd " offset data F ' is (n-1) for (n-1) identical (n-1).Because (n-1) compensation decompressed data Fd " (n-1) identical with n frame data F (n), so (n-1) offset data F ' (n-1) equals n frame data F (n).
Similarly, when showing the freeze frame image, each output of first compensator 296 and second compensator 297 both be not compressed does not have decompressed n frame data F (n) yet.Therefore, do not have processed n frame data F (n) to be used to display image, thereby avoid damaging the freeze frame image.
Fig. 6 is the block diagram that illustrates according to another exemplary embodiment of data compensating circuit of the present invention, and Fig. 7 is the internal frame diagram of the compensator shown in Fig. 6.
With reference to Fig. 6, data compensating circuit 900 comprises: first memory 910, second memory 920, scrambler 930, comparer 940, demoder 950, compensator 960 and data selector 970.
In first memory 910, store in advance from (n-1) packed data Fc (n-1) of (n-1) frame data F (n-1) compression, will store in advance the second memory 920 from (n-2) packed data Fc (n-2) of (n-2) frame data F (n-2) compression.Each of first memory 910 and second memory 920 is less than 2m/i (m represents the bit number of (n-1) frame data F (n-1) and (n-2) frame data F (n-2), and i represents the value that obtains divided by the bit number that will be compressed into by with the m bit).
In the present embodiment, comprise under the situation of 24 bits that (n-1) packed data Fc (n-1) comprises 1/3rd 8 bits that are compressed to (n-1) frame data F (n-1) at (n-1) frame data F (n-1).Therefore, the size of each of first memory 910 and second memory 920 is 2 8Similarly, the packed data that will have less than the data volume of the amount of a frame is stored in each of first memory 910 and second memory 920, thereby can reduce the size of first memory 910 and second memory 920.
Scrambler 930 receives n frame data F (n) at n image duration, and with n frame data F (n) boil down to n packed data Fc (n).Read (n-1) packed data Fc (n-1) and (n-2) packed data Fc (n-2) that is stored in respectively in advance in first memory 910 and the second memory 920 image duration at n.
Comparer 940 receives n packed data Fc (n), (n-1) packed data Fc (n-1) and (n-2) packed data Fc (n-2) from scrambler 930, first memory 910 and second memory 920 respectively.When n packed data Fc (n) was identical with (n-2) packed data Fc (n-2) with (n-1) packed data Fc (n-1), comparer 940 outputs had the first State Selection signal S1.In addition, when and (n-1) packed data Fc (n-1) different with (n-2) packed data Fc (n-2) with (n-1) packed data Fc (n-1) was identical with (n-2) packed data Fc (n-2) as n packed data Fc (n), comparer 940 outputs had the second State Selection signal S1.
Demoder 950 comprises: first demoder 951, second demoder 952 and the 3rd demoder 953.First demoder 951 receives n packed data Fc (n) from scrambler 930, and n packed data Fc (n) decompress(ion) is condensed to n decompressed data Fd (n) to export n decompressed data Fd (n).Second demoder 952 receives (n-1) packed data Fc (n-1), and (n-1) packed data Fc (n-1) decompress(ion) is condensed to (n-1) decompressed data Fd (n-1) to export (n-1) decompressed data Fd (n-1).The 3rd demoder 953 receives (n-2) packed data Fc (n-2), and (n-2) packed data Fc (n-2) decompress(ion) is condensed to (n-2) decompressed data Fd (n-2) to export (n-2) decompressed data Fd (n-2).
Compensator 960 receives n decompressed data Fd (n), (n-1) decompressed data Fd (n-1) and (n-2) decompressed data Fd (n-2) from first demoder 951, second demoder 952 and the 3rd demoder 953 respectively.Compensator 960 is based on n decompressed data Fd (n), (n-1) decompressed data Fd (n-1) and (n-2) decompressed data Fd (n-2) output first offset data Fd " (n-1).
Data selector 970 receives the first offset data Fd " (n-1), n frame data F (n) and from the selection signal S1 of comparer 940, (n-1) with output data F '.Particularly, when input had the first State Selection signal S1, data selector 970 output n frame data F (n) as output data F ' (n-1).When input has the second State Selection signal S1, the data selector 970 outputs first offset data Fd " (n-1) (n-1) as output data F '.
As shown in Figure 7, compensator 960 comprises: first compensator 961 and second compensator 962.
First compensator 961 is exported the second offset data Fd ' (n-1) based on (n-1) decompressed data Fd (n-1) and (n-2) decompressed data Fd (n-2).Second compensator 962 (n-1) is exported the first offset data Fd with n decompressed data Fd (n) based on the second offset data Fd ' " (n-1).
When the difference between (n-2) decompressed data Fd (n-2) and (n-1) decompressed data Fd (n-1) during less than predetermined reference value, first compensator, 961 output (n-1) decompressed data Fd (n-1).When described difference during greater than described reference value, increase predetermined backoff value is compared in 961 outputs of first compensator with (n-1) decompressed data Fd (n-1) the second offset data Fd ' (n-1).
Second compensator 962 receive the second offset data Fd ' (n-1) and n decompressed data Fd (n) to export first offset data.As this exemplary embodiment, the first offset data Fd " (n-1) have the second offset data Fd ' (n-1) and the intermediate value between the n decompressed data Fd (n).
According to another embodiment of the present invention, data compensating circuit 900 also comprises having according to the second offset data Fd ' (n-1) and the question blank (LUT, not shown) of the predetermined backoff data of the value of n decompressed data Fd (n).Therefore, second compensator 962 can (n-1) be used as the first offset data Fd with n decompressed data Fd (n) from LUT output offset data based on the second offset data Fd ' " (n-1).
Data selector 970 is exported the first offset data Fd according to the state of selecting signal S1 " (n-1) or n frame data F (n) as output data F ' (n-1).
Therefore, in order to show the freeze frame image, data compensating circuit 900 outputs do not have compressed n frame data F (n), thereby avoid corrupt data.In addition, when the freeze frame image transitions was moving image, data compensating circuit 900 was based on the data output intermediate value from the data of freeze frame image and moving image, thereby avoided corrupt data when conversion.
Fig. 8 is the block diagram that the liquid crystal display with the data compensating circuit shown in Fig. 1 is shown.
With reference to Fig. 8, liquid crystal display 1000 comprises: display unit 300, display image; Gate driver circuit 400, and data drive circuit 500 drive display unit 300; Gray-scale voltage generator 800 is connected to data drive circuit 500; And timing controller 600, the driving of control gate driver circuit 400 and data drive circuit 500.
Gate lines G L1～the GLn of a plurality of receiving grid pole tensions and the data line DL1～DLm of a plurality of reception data voltages are arranged on the display unit 300.Gate lines G L1～GLn and data line DL1～DLm define a plurality of pixel regions with matrix structure, at each pixel region laying out pixel 310.Pixel 310 comprises: thin film transistor (TFT) 311, liquid crystal capacitor (liquid crystal capacitor) C LCAnd holding capacitor (storagecapacitor) C ST
As shown in Figure 8, thin film transistor (TFT) 311 comprises: be connected to first grid polar curve GL1 gate electrode, be connected to the source electrode of the first data line DL1, and be connected to liquid crystal capacitor C LCWith holding capacitor C STDrain electrode.
In the present embodiment, display unit 300 comprises: the upper substrate of infrabasal plate, the substrate that faces down, and place liquid crystal layer between infrabasal plate and the upper substrate.
On infrabasal plate, form gate lines G L1～GLn, data line DL1～DLm, thin film transistor (TFT) 311 and be used as liquid crystal capacitor C LCThe pixel electrode of first electrode.Therefore, thin film transistor (TFT) 311 is applied to pixel electrode in response to grid voltage with data voltage.
On upper substrate, form as liquid crystal capacitor C LCThe common electrode of second electrode, common-battery pressed be applied to common electrode.Place the liquid crystal layer between pixel electrode and the common electrode to be used as dielectric.Thereby, and the electric potential difference correspondent voltage between data voltage and the common-battery pressure is charged into liquid crystal capacitor C LC
Gate driver circuit 400 is electrically connected to the gate lines G L1～GLn that is arranged on the display unit 300, grid voltage is offered gate lines G L1～GLn.Data drive circuit 500 is electrically connected to the data line DL1～DLm that is arranged on the display unit 300, and selects gray-scale voltage from gray-scale voltage generator 800, is used as data voltage gray-scale voltage is offered data line DL1～DLm.
Timing controller 600 receives various control signals, for example: vertical synchronizing signal Vsync, horizontal-drive signal Hsync, major clock MCLK, data enable signal DE etc.Timing controller 600 is based on various control signal output grid control signal CONT1 and data controlling signal CONT2.
Grid control signal CONT1 is offered gate driver circuit 400, with the driving of control gate driver circuit 400.Grid control signal CONT1 comprises: start gate driver circuit 400 the driven vertical enabling signal, determine the gate clock signal of the output time of grid voltage and the output enable signal of the ON pulse width of definite grid voltage.
Gate driver circuit 400 is in response to from the grid control signal CONT1 of timing controller 600 grid voltage being output as grid-forward voltage Von or grid-by voltage Voff.
Data controlling signal CONT2 is offered the signal of data drive circuit 500 as the driving of control data driving circuit 500.Data controlling signal CONT2 comprises: the switching signal of the driven vertical enabling signal of log-on data driving circuit 500, the polarity of translation data voltage, determine the output indicator signal from the output time of the data voltage of data drive circuit 500.
Form timing controller 600, built-in data compensating circuit shown in Figure 1 100 in timing controller 600 with chip form.Particularly, stores compressed data in storer 110 (as shown in Figure 1), thereby can reduce the size of storer 110, and can be in timing controller 600 internal memory 110.
Data compensating circuit 100 receives current frame data F (n) from the external graphics controller (not shown), and during present frame current frame data F (n) is compensated for as current offset data F ' (n).Data drive circuit 500 receives current offset data F ' (n) in response to the data controlling signal CONT2 from timing controller 600, and from from selecting the gray-scale voltage of gray-scale voltage generator 800 corresponding to current offset data F ' gray-scale voltage (n).Then, data drive circuit 500 is converted to data voltage with the gray-scale voltage of selecting, to export this data voltage.
Therefore, display unit 300 is in response to data voltage and grid voltage display image.Particularly, under the situation of freeze frame image, current offset data F ' (n) is changed into the data voltage that does not also have decompressed current frame data F (n) corresponding to both not being compressed, thereby display unit 300 can use and not have impaired data to come display image.
According to top description, compressed frame data also is stored in it in storer, decompressing after the frame data that storer is read, the frame data that decompress is offered compensator.Therefore, can reduce the size of storer, and can be in timing controller internal memory, thereby reduce manufacturing cost, increase productive rate.In addition, under the situation that shows the freeze frame image, both not being compressed does not have decompressed current frame data to be used to display image yet, thereby avoids corrupt data.
Data compensating circuit compares mutually the packed data corresponding to three successive frames, and output does not have compressed current frame data according to comparative result, perhaps exports the intermediate value between the current frame data and first offset data.Therefore, display device can improve response speed, and avoids the corrupt data owing to compress.
Although described exemplary embodiment of the present invention, but should be appreciated that, should not limit the invention to these exemplary embodiments, those of ordinary skill in the art can carry out various changes and modification to it not breaking away from the interior of the desired the spirit and scope of the present invention of claim.

Claims (28)

1. data compensating circuit comprises:
Storer, the previous packed data that the storage frame data is compressed into;
Demoder decompresses to the previous packed data of reading from storer during present frame, to export previous decompressed data;
Scrambler-demoder, during present frame with the current packed data of current frame data boil down to so that current packed data is stored in the storer, and the current packed data that decompresses is to export current decompressed data;
First processor, first difference of the difference between output previous decompressed data of indication and the current decompressed data;
Second processor had been exported before decompressed data once more based on described first difference and current frame data; With
Compensator, based on before once more decompressed data and current frame data compensate current frame data, exporting current offset data,
Wherein, when second difference of the difference between previous decompressed data once more of indication and the current frame data during less than predetermined first reference value, compensator output has the current offset data of the value identical with current frame data, and when described second difference during greater than described first reference value, the current offset data that has increased the predetermined backoff value is compared in compensator output with current frame data
Wherein, when described first difference equals zero, the decompressed data once more before that second processor output is identical with current frame data, and current offset data equals current frame data.
2. data compensating circuit as claimed in claim 1, wherein, previous decompressed data once more be current frame data and described first difference and.
3. data compensating circuit as claimed in claim 1, wherein, the size of storer is less than 2 m, wherein, m represents the bit number of current frame data.
4. data compensating circuit as claimed in claim 3, wherein, the size of storer is 2 M/3
5. data compensating circuit as claimed in claim 4, wherein, demoder is condensed to the previous decompressed data of m bit with the previous packed data decompress(ion) of m/3 bit, and scrambler-demoder is with the current packed data of the current frame data boil down to m/3 bit of m bit.
6. data compensating circuit comprises:
First memory is stored in advance from (n-2) packed data of (n-2) frame data compression, and wherein, n represents present frame;
Second memory is stored in advance from (n-1) packed data of (n-1) frame data compression;
First demoder is at n (n-2) packed data that decompresses image duration, to export (n-2) decompressed data;
Second demoder is at n (n-1) packed data that decompresses image duration, to export (n-1) decompressed data;
Scrambler-demoder, n image duration with n frame data boil down to n packed data, so that the n packed data is offered second memory, and the n packed data that decompresses is to export the n decompressed data;
First processor, first difference of the difference between output indication (n-2) decompressed data and the n decompressed data;
Second processor is exported (n-2) decompressed data once more based on described first difference and n frame data;
The 3rd processor, second difference of the difference between output indication (n-1) decompressed data and the n decompressed data;
Four-processor is exported (n-1) decompressed data once more based on described second difference and n frame data;
Compensator, based on (n-2) once more decompressed data, (n-1) once more decompressed data and n frame data compensate (n-1) decompressed data once more, to export (n-1) offset data.
7. data compensating circuit as claimed in claim 6, wherein, (n-2) once more decompressed data be n frame data and described first difference and, (n-1) once more decompressed data be n frame data and described second difference and.
8. data compensating circuit as claimed in claim 6, wherein, each of first memory and second memory is less than 2 m, wherein, m represents the bit number of n frame data.
9. data compensating circuit as claimed in claim 8, wherein, each size of first memory and second memory is 2 M/3
10. data compensating circuit comprises:
First memory is stored in advance from (n-2) packed data of (n-2) frame data compression, and wherein, n represents present frame;
Second memory is stored in advance from (n-1) packed data of (n-1) frame data compression;
Scrambler is converted to the n packed data with the n frame data at n image duration;
Comparer compares mutually (n-2) packed data, (n-1) packed data and n packed data, selects signal with output;
Demoder is condensed to n decompressed data, (n-1) decompressed data and (n-2) decompressed data with n packed data, (n-1) packed data and (n-2) packed data decompress(ion) respectively;
Compensator is exported first offset data based on n decompressed data, (n-1) decompressed data and (n-2) decompressed data; With
Data selector is in response to selecting signal to export n frame data or first offset data as its output data.
11. data compensating circuit as claimed in claim 10, wherein, compensator comprises:
First compensator is exported second offset data based on (n-1) decompressed data and (n-2) decompressed data; With
Second compensator is exported first offset data based on second offset data and n decompressed data.
12. data compensating circuit as claimed in claim 11, wherein, second compensator is exported intermediate value between second offset data and the n decompressed data as first offset data.
13. data compensating circuit as claimed in claim 11, wherein, when the difference of the difference between indication (n-2) decompressed data and (n-1) decompressed data during less than predetermined reference value, first compensator output (n-1) decompressed data, and when described difference during greater than described predetermined reference value, the output of first compensator is compared second offset data that has increased the predetermined backoff value with (n-1) decompressed data.
14. data compensating circuit as claimed in claim 10, wherein, when the n packed data equals (n-2) packed data and (n-1) packed data, comparer output has the first State Selection signal, when the n packed data different with (n-2) packed data and (n-1) packed data, and (n-1) packed data and (n-2) are when packed data is identical, and comparer output has the second State Selection signal.
15. data compensating circuit as claimed in claim 14, wherein, data selector is exported the n frame data as output data in response to having the first State Selection signal, exports first offset data as output data in response to having the second State Selection signal.
16. data compensating circuit as claimed in claim 10, wherein, the size of each of first memory and second memory is less than 2 m, wherein, m represents the bit number of n frame data.
17. a display device comprises:
Data compensating circuit produces current offset data based on frame data and current frame data;
Data drive circuit is in response to the data voltage of data controlling signal output corresponding to current offset data;
Gate driver circuit is in response to grid control signal output grid voltage; With
Display unit, in response to data voltage and grid voltage display image,
Described data compensating circuit comprises:
Storer is stored in advance from the previous packed data of previous frame data compression;
Demoder decompresses to the previous packed data of reading from storer during present frame, to export previous decompressed data;
Scrambler-demoder, during present frame with the current packed data of current frame data boil down to so that current packed data is stored in the storer, and the current packed data that decompresses is to export current decompressed data;
First processor, first difference of the difference between output previous decompressed data of indication and the current decompressed data;
Second processor had been exported before decompressed data once more based on described first difference and current frame data; With
Compensator, based on before once more decompressed data and current frame data compensate current frame data, exporting current offset data,
Wherein, when second difference of the difference between previous decompressed data once more of indication and the current frame data during less than predetermined first reference value, compensator output has the current offset data of the value identical with current frame data, and when described second difference during greater than described first reference value, the current offset data that has increased the predetermined backoff value is compared in compensator output with current frame data
Wherein, when described first difference equals zero, the decompressed data once more before that second processor output is identical with current frame data, and current offset data equals current frame data.
18. display device as claimed in claim 17, wherein, previous decompressed data once more be current frame data and described first difference and.
19. display device as claimed in claim 17, wherein, the size of storer is less than 2 m, wherein, m represents the bit number of current frame data.
20. display device as claimed in claim 17 also comprises: timing controller in response to external control signal, is applied to data drive circuit and gate driver circuit with data controlling signal and grid control signal respectively.
21. display device as claimed in claim 20 wherein, forms timing controller with chip form, and in timing controller built-in data compensating circuit.
22. display device as claimed in claim 17, wherein, display unit comprises a plurality of pixels of arranging with matrix structure on it, and each of described pixel comprises:
Thin film transistor (TFT) is in response to grid voltage output data voltage; With
Liquid crystal capacitor is charged into the electric potential difference between data voltage and the preset reference voltage.
23. a display device comprises:
Data compensating circuit receives the n frame data at n and be used as output data to compensate the n frame data image duration;
Data drive circuit is converted to data voltage in response to data controlling signal with the data that compensate, to export this data voltage;
Gate driver circuit is in response to grid control signal output grid voltage; With
Display unit, in response to data voltage and grid voltage display image,
Described data compensating circuit comprises:
First memory is stored in advance from (n-2) packed data of (n-2) frame data compression;
Second memory is stored in advance from (n-1) packed data of (n-1) frame data compression;
Scrambler is converted to the n packed data with the n frame data at n image duration;
Comparer compares mutually (n-2) packed data, (n-1) packed data and n packed data, selects signal with output;
Demoder is condensed to n decompressed data, (n-1) decompressed data and (n-2) decompressed data with n packed data, (n-1) packed data and (n-2) packed data decompress(ion) respectively;
Compensator is exported first offset data based on n decompressed data, (n-1) decompressed data and (n-2) decompressed data; With
Data selector is in response to selecting signal to export n frame data or first offset data as output data.
24. display device as claimed in claim 23, wherein, compensator comprises:
First compensator is exported second offset data based on (n-1) decompressed data and (n-2) decompressed data; With
Second compensator is exported first offset data based on second offset data and n decompressed data.
25. display device as claimed in claim 23, wherein, when the n packed data equals (n-2) packed data and (n-1) packed data, comparer output has the first State Selection signal, when the n packed data different with (n-2) packed data and (n-1) packed data, and (n-1) packed data and (n-2) are when packed data is identical, and comparer output has the second State Selection signal.
26. display device as claimed in claim 25, wherein, data selector is exported the n frame data as output data in response to having the first State Selection signal, exports first offset data as output data in response to having the second State Selection signal.
27. display device as claimed in claim 23 also comprises: timing controller in response to external control signal, is applied to data drive circuit and gate driver circuit with data controlling signal and grid control signal respectively.
28. display device as claimed in claim 27 wherein, forms timing controller with chip form, and in timing controller built-in data compensating circuit.
CN2007101091277A 2006-06-12 2007-06-12 Display apparatus having data compensating circuit Expired - Fee Related CN101089940B (en)

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