KR20070115600A - Semiconductor test system - Google Patents

Abstract

A semiconductor testing system is provided to maintain the accuracy of defect detection with respect to a semiconductor device and to reduce a testing time by employing a detection determining unit and a test item deleting unit. A test item managing unit(9) manages a plurality of test items when a test for a semiconductor device is performed. A test performing unit(11) performs a test for the semiconductor device according to the test items. A detection determining unit(21) determines whether a specific defect to be detected by a specific test item of the test items is detected by another test item of the test items, based on the test result of the test performing unit. In case the detection determining unit determines that the specific defect is to be detected by the another test item, a test item deleting unit(13) deletes the specific test item from the test items managed by the test item managing unit.

Description

Semiconductor Test System {SEMICONDUCTOR TEST SYSTEM}

1 is a block diagram showing an example of the electrical configuration of a semiconductor test system.

FIG. 2 is a block diagram showing an example of the electrical configuration of the semiconductor test system shown in FIG. 1.

3 is a flowchart showing an example of a test operation of a semiconductor test system.

It is a figure which shows the example of the one-to-one inclusion comparison image regarding the detection situation by an inspection item.

It is a figure which shows the example of the one-to-one inclusion comparison image regarding the detection situation by an inspection item.

Fig. 6 is a diagram showing one example of a plurality of inclusion comparison images relating to a detection situation by an inspection item.

[Description of the code]

1: semiconductor test system

9: Inspection item storage (inspection item management means)

11: Test execution part (test execution means)

13: Inspection item deletion part (scanning item deletion means)

15: Defective result data (test result)

17: defective detection count counting unit (defect detection count counting means)

19: Judgment unit (judgment means)

21: detection or not judging unit (detection or not judging means)

[Patent Document 1] Japanese Patent Application Laid-Open No. 11-243125 (Figs. 3 and 4)

The present invention relates to a semiconductor test system for testing a plurality of inspection items with respect to a semiconductor device.

Background Art Conventionally, semiconductor test systems (hereinafter referred to as "IC test systems") have been used in the production line of IC (Integrated Circuit) devices. The IC test system includes a test server and an IC tester. An IC tester is installed in the manufacturing line of an IC device. Under the control of the test server, the IC tester tests the manufactured IC device in the order specified for the plurality of inspection items and detects the defective device. When an IC tester tests each inspection item with respect to an IC device, it collects the defect result data as a test result.

In the conventional IC test system, in order to shorten the test time, a test is performed for each inspection item over a predetermined number of times to collect defect result data, and for example, the number of defects for a particular inspection item is determined. When it is less than a predetermined number, the said specific test | inspection item is deleted from the test | inspection item (refer patent document 1).

However, in the conventional semiconductor test system, when determining which inspection item among a plurality of inspection items to delete, only the detection situation (failure result data for the same kind of inspection item) by the same kind of inspection item is considered. Since the correlation of each detection situation by these inspection items is not considered, the inspection item which can be deleted because it is not necessary to test was also tested.

Therefore, an object of this invention is to provide the semiconductor test system which can test in a short time, maintaining the detection accuracy of the defect regarding a semiconductor device.

<First Example>

1 is a block diagram showing an example of the electrical configuration of a semiconductor test system 1 as a first embodiment of the present invention.

The semiconductor test system 1 includes an integrated circuit (IC) tester 3, an external memory device 7, and an arithmetic analyzer 5. The IC tester 3 is a test apparatus provided in the manufacturing line of an IC device. In the IC tester 3, a test program is operating, and the test program controls the execution of the test on the IC device (semiconductor device) manufactured in the manufacturing line, and a defect based on the test result. Whether to generate result data. The IC tester 3 has a function of transmitting the generated defect result data to the external storage device 7.

The external storage device 7 is a storage device of a large capacity such as a hard disk, for example, and is a storage device for accumulating defect result data regarding test results for an IC device. The external storage device 7 is configured to store the defective result data received from the IC tester 3 and to provide the stored defective result data. The external memory device 7 may be configured to be embedded by either the IC tester 3 or the arithmetic analysis device 5.

In the arithmetic analysis device 5, a failure analysis program is in operation, and the failure analysis program performs a failure analysis on the IC device based on the failure result data stored in the external storage device 7. In this embodiment, an IC device in which a defect occurs among IC devices is referred to as a "bad device."

FIG. 2 is a block diagram showing an example of the electrical configuration of the semiconductor test system 1 shown in FIG. 1.

In the semiconductor test system 1, the IC tester 3 includes a test execution unit 11 (test execution means), a detection or not determination unit 21 (detection or not determination means), and an inspection item deletion unit 13 (inspection). And an inspection item storage unit 9 (inspection item management means) used by the test execution unit 11. On the other hand, the external storage device 7 is configured to store the result data 15 of whether or not there is a defect.

The inspection item storage section 9 is a storage section that manages a plurality of inspection items for which an IC device should be tested. The test execution unit 11 is managed in the inspection item storage unit 9 and has a function of testing a semiconductor device by a test program in accordance with the order of the plurality of inspection items.

According to the test result by the test execution part 11, the detection possibility determination part 21 is a defect which can be detected by the specific test | inspection item contained in a some test | inspection item (henceforth "specific defect"). Has a function of judging whether or not it can be detected by other inspection items included in the two inspection items.

Specifically, the detection or not determining unit 21 includes a failure detection count counting unit 17 (defect detection count counting device) and determination unit 19 (determination means). The failure detection count counting unit 17 has a function of counting the number of times that the specific failure is detected in accordance with the failure result data 15 accumulated in the external storage device 7. The determination unit 19 has a function of determining that the specific failure is detectable by the other detection item when the number of times that the specific failure is detected is more than a predetermined number of times.

When the inspection item deletion unit 13 determines that the specific defect is detectable by another inspection item by the detection determination unit 21, the inspection item deletion unit 13 is configured to execute the inspection item deletion unit 13 from the plurality of inspection items managed by the inspection item storage unit 9. It has the function to delete a specific test item.

The semiconductor test system 1 is configured as described above, and will be specifically described below with reference to FIGS. 1 and 2.

3 is a flowchart showing an example of a test operation of the semiconductor test system 1.

4 and 5 are diagrams showing examples of one-to-one inclusion comparison images relating to detection status of bad bits by inspection item X and inspection item Y, respectively, and FIG. 6 shows inspection item X, inspection item Y and inspection item. It is a figure which shows the example of one to several containing comparison image regarding the detection situation of the bad bit by Z. FIG.

In the semiconductor test system 1, the IC tester 3 generates cumulative failure result data (so-called bad bit data) 15 for a plurality of inspection items, and at the same time, for example, each inspection item. The result data 15 about whether the defect is related to each other is generated.

In this embodiment, as an example, it is assumed that the number of IC devices of the same type is m, and the number of inspection items (the number of tests) for one IC device is n. In the IC tester 3, first, the test execution unit 11 performs a test on n inspection items for each of the m IC devices, collects all the defective result data 15, and It stores in the storage device 7 (step S1 in FIG. 3). The plurality of defective result data 15 may be collected by the same IC tester 3 or may be collected by different plurality of IC testers 3.

The detection or not determination unit 21 processes as follows while paying attention to any two inspection items X and inspection items Y among the number of inspection items m, for example. That is, the detection or not determination unit 21 detects the detection situation based on the defect result data 15 relating to the inspection item X shown in FIG. 4A and the inspection item Y shown in FIG. 4B. The detection status based on the defective result data 15 concerning the comparison is compared one-to-one, and the inclusion relation of the defect bits which can be detected by both inspection items X and Y is grasped | ascertained. In the illustrated example, the black bit is a bad bit. The detection or not determination unit 21 can know that an inclusion relationship of "inspection item X 'inspection item Y" is established. The detection or not judging unit 21 performs such a comparison process according to any one combination of each inspection item for one IC device (step S2 in FIG. 3).

The detection or not determination unit 21 executes such a comparison process for each of the m IC devices, and statistically calculates the inclusion relationship of the detection situation between each inspection item. At this time, the detection determination unit 21 determines that the inspection item X is equal to or greater than a prescribed number (for example, m) of IC devices set as the inspection target, and more than a predetermined number (predetermined number) among them. And the inspection item Y, it is judged whether or not the inclusion relationship of "inspection item X-inspection item Y" holds (step S3 in FIG. 3).

The detectable determination unit 21 determines that all the bad bits (specific defects) that can be detected by the inspection item X can be detected by the inspection item Y when such an inclusion relationship is established (step S4 in FIG. 3), It is determined that the test item X is a test item that does not need to be executed (or may be deleted).

On the other hand, the detection whether or not the determination unit 21 determines that all the bad bits detectable by the inspection item X cannot be detected by the inspection item Y when the inclusion relationship of "inspection item X-inspection item Y" does not hold ( In step S5 of FIG. 3, it is determined that the inspection item X should be executed (which should not be deleted).

As shown in FIG. 5, the detection whether or not the determination unit 21 does not hold "inspection item X ⊆ inspection item Y" in the relationship between the inspection item X and the inspection item Y. As shown in Fig. 7, attention is also paid to the inspection item Z. Specifically, the detection determination unit 21 detects the detection situation based on the defect result data 15 concerning the inspection item X shown in FIG. 6A and the inspection item shown in FIG. 6B. The detection situation of the bad bit is determined by the detection situation based on the bad result data 15 concerning Y and the detection condition based on the bad result data 15 concerning the inspection item Z shown in Fig. 6C. Compare.

Specifically, the detection whether or not the determination unit 21 is based on the detection situation by the inspection item Y shown in FIG. 6B and the detection situation by the detection item Z shown in FIG. 6C. When the detection situation by detection item X shown in A) can be included, that is, the bad bit detectable by detection item X is a bad bit detectable by detection item Y or a bad bit detectable by detection item Z. In this case, it is determined as follows. That is, the detection determination part 21 judges that "the inspection item X-inspection item Y-inspection item Z" is satisfied, and it is not necessary to test (you may delete) the inspection item X. .

In this way, when it is determined that the detection or not determining unit 21 does not need to perform a test on the inspection item X (specific inspection item), the inspection item deleting unit 13 is managed by the inspection item storage unit 9. The inspection item X is deleted from the plurality of inspection items X, Y, Z and the like (step S6 in FIG. 3). Since the test execution unit 11 performs a test only on the test items registered in the test item storage 9, the following IC is deleted as the test item X is deleted from the test item storage 9 in this way. When performing a test regarding a device, the test regarding inspection items Y and Z is performed, without performing the test regarding said inspection item X.

The arithmetic analysis apparatus 5 is based on the defect result data 15 regarding each test item accumulated in the external storage device 7, and the defect result data 15 about all the test items accumulated. The device is analyzed for defects bit by bit.

According to the first embodiment, the test execution unit 11 tests the IC device according to the plurality of inspection items X, Y, and Z, and as a result, the detection or not determining unit 21 determines the plurality of inspection items X, Y, and Z. When it is determined that the specific defect can be commonly detected by the combination of, the inspection item deleting unit 13 automatically determines the specific inspection item X from the plurality of inspection items X, Y, and Z managed by the inspection item storage unit 9. Delete it.

Therefore, the test execution part 11 does not test the specific inspection item X after that, but it can reliably detect it by performing a test with respect to the other inspection items Y and Z about the specific defect. Can be. Therefore, in this embodiment, the number of inspection items can be reduced in relation to the relative detection situation with a plurality of inspection items X, Y, and Z, and the test time for each IC device can be shortened while maintaining the detection sensitivity of the defect. have.

In addition, in the first embodiment, when the semiconductor test system 1 is installed in the mass production line of the IC device, the test items can be further reduced as the IC device to be tested is tested, and the IC device can be tested in a short time. Therefore, even a large amount of IC devices can be tested efficiently in a short time.

In addition, in the first embodiment, the detection or not determination unit 21 includes a failure detection count counting unit 17 that counts the number of times a specific failure is detected by each inspection item, and further by another inspection item. When the number of times that a specific failure is detected is equal to or more than a preset number, a determination unit 19 (judgment means) is provided that determines that the specific failure can be detected by another detection item instead of the specific inspection item.

With such a configuration, the detection or not determining unit 21 can more accurately determine whether or not a specific defect can be detected in accordance with other detection items according to a clear judgment standard, so that the inspection item deleting unit 13 It is possible to precisely delete specific inspection items to be deleted from the plurality of inspection items. In addition, even if a defect is detected incorrectly, the detection whether or not determination part 21 does not judge by one detection, and can judge whether a specific defect can be detected correctly by another detection item.

In addition, in the first embodiment, when it is determined that the detection failure unit 21 cannot detect a specific defect even by another inspection item, it is detected by another inspection item included in the plurality of inspection items. And other inspection item determination means for judging whether or not it can be done. In addition, when it is determined by this judgment that the specific defect is detectable, the detection or not judging unit 21 manages the plurality of items managed by the inspection item storage unit 9 with respect to the inspection item deletion unit 13. Instructs to delete a specific inspection item from the inspection item (deletion instruction means).

In this way, even if the detection whether or not the detection unit 21 cannot detect a specific defect even by other inspection items, the detection accuracy of detecting a defect by finding a combination of inspection items that can detect the specific failure is determined. It is possible to reduce the number of inspection items so that the number of inspection items is kept to a minimum, and to minimize the test time of the IC device.

<2nd Example>

Since the semiconductor test system 1a in the second embodiment is configured almost the same as the semiconductor test system 1 in the first embodiment, and all perform almost the same operations, The description will be omitted, and the following description will focus on different points. Incidentally, in the second embodiment, the same configuration and operation as those in the first embodiment will be described, and the same reference numerals as those in the first embodiment are used.

In the second embodiment, the following deletion criteria for inspection items are adopted instead of or in parallel with the deletion criteria for the inspection items in the first embodiment. Specifically, in the second embodiment, the semiconductor test system 1a is configured as follows.

The semiconductor test system 1a is provided with the holding part which hold | maintains the said defect result data, the analysis part which analyzes the said defect result data, the condition table memory, the discrimination part, and the change part. The condition table memory stores a condition table showing conditions for deleting an inspection item and conditions for changing the order of inspection items. The discriminating unit determines whether the inspection item needs to be deleted or replaced based on the analysis result of the analyzing unit and the conditions of the condition table.

The changing unit executes deletion or replacement on the inspection item determined by the determination unit to be deleted or replaced.

In this way, inspection items are automatically deleted or replaced based on the analysis results of the long-term failure result data reached from the start of mass production of the IC device to the present, and the condition table. Accordingly, in the second embodiment, the inspection items can be deleted or replaced without lowering the inspection efficiency, and the judgment errors regarding the deletion of the inspection items can be prevented by the determination based on the defective result data over a long period of time. can do.

In the second embodiment, the failure result data is grouped into inspection categories according to a predetermined theorem, and the failure determination results of the IC device are aggregated into summary data for each inspection item in the category. . In this way, it is possible to delete or replace inspection items automatically by collecting summary data rather than the actual data of the inspection results (bad result data), so that the inspection items can be deleted or replaced efficiently without collecting unnecessary data. Can be.

In addition, in the second embodiment, the semiconductor test system 1a may be provided with the following prediction unit and control unit. The predicting unit has a function of predicting an inspection result when the inspection items are inspected in the existing IC device in the changed order when the inspection items are changed in order. The collation unit has a function of collating the inspection result obtained when the inspection item is actually inspected for the IC device in the changed order and the inspection result obtained from the prediction unit. In this way, it is possible to confirm whether or not the IC tester 3 is operating normally.

In addition, in 2nd Example, the semiconductor test system 1a may be equipped with the following 1st counters and a change part. First, a 1st counter counts the number of defects which generate | occur | produced in the test | inspection item with respect to the test | inspection item which the defect generate | occur | produced. The changing unit has a function of changing an inspection item whose defect number exceeds a predetermined value based on the count of the first counter and the condition of the condition table so as to be in an inspection order before the current inspection order. In this case, since the inspection order is faster as the inspection item having a higher probability of failure occurs, the probability that a defect occurs and the test is terminated increases as the inspection order is faster. Accordingly, inspection of unnecessary inspection items can be omitted.

In addition, in the second embodiment, the semiconductor test system 1a may include a second counter, a third counter, and a deletion unit. The second counter counts the total number of IC devices that were tested. The third counter counts the number of times the test has not been performed for each inspection item. The deleting unit has a function of deleting a test item for which a failure has not occurred continuously for a predetermined number of test times or more, based on the count of the second counter, the count of the third counter, and the condition table. In this way, since inspection items which are always judged to be non-defective items are deleted from the plurality of inspection items, inspection efficiency can be improved. In this manner, as the mass production results of the IC device are accumulated, the inspection items to be examined for deletion continue to increase, thereby increasing the probability that the inspection efficiency is improved by deleting the inspection items.

In the second embodiment, a plurality of IC testers 3 are provided in a mass production line of the IC device, and a form in which the plurality of IC testers 3 are managed by the arithmetic analysis device 5 (tester server) is adopted. When doing so, the IC test system 1a is provided with the following operation state monitoring part. Specifically, the operation status monitoring unit monitors the operation status of each IC tester 3, collects and analyzes the stop factors when the operation is stopped, and gives an instruction to improve the stop factors of the IC tester 3. Have In this way, it is possible to accurately analyze the stop factor of the IC tester 3 and issue an improvement command.

In addition, in the second embodiment, similarly, when a plurality of IC testers 3 are provided in the mass production line of the IC device, and the form of managing the plurality of IC testers 3 by the arithmetic analysis device 5 is adopted. In addition, the IC test system 1a may take the form provided with the determination part. The determination unit has a function of determining whether each IC tester 3 is normal or not, based on the inspection result of each IC tester, or whether the IC device is normally inspected.

As mentioned above, although one Example was described, the Example of this invention is not limited to this. Each structure of the said embodiment can change not only the form as mentioned above but a combination suitably.

In the above embodiment, the test subject by the semiconductor test system 1 is exemplified as a semiconductor memory. However, the test is not limited to such a memory device, but a system on chip IC device is tested. Applicable to In the above embodiment, although the inspection item storage unit 9 manages a plurality of inspection items X, Y, and Z, the present invention is not limited thereto, and the inspection item deletion unit 13 includes these inspection items X, Y. , Z may be managed in any form as long as it can be deleted. In addition, in the said Example, although the structure provided with the test program in the test execution part 11 was shown, the said test execution part 11 may be comprised so that a test program may be read.

The semiconductor test system of this invention can provide the semiconductor test system which can test in a short time, maintaining the defect detection precision regarding a semiconductor device.

Claims (5)

Inspection item management means for managing a plurality of inspection items when a test is to be performed on a semiconductor device; Test execution means for performing a test on the semiconductor device according to the plurality of inspection items; On the basis of the test result by the said test execution means, whether the specific defect which can be detected by the specific test | inspection item contained in the said some inspection item is detectable by the other test | inspection item contained in the said some inspection item. Detection means for determining whether or not; And when the specific defect is determined by the other inspection item to be detected by the detection whether or not by the detection or not judging means, deleting an inspection item for deleting the specific inspection item from the plurality of inspection items managed by the inspection item management means. Way Semiconductor test system comprising a. The method of claim 1, The detection or not determining means, Failure detection count counting means for counting the number of times the specific failure is detected by each of the inspection items; Determination means for determining that the specific failure is detectable by the other detection item instead of the specific inspection item when the number of times the specific failure is detected by the other inspection item is more than a predetermined number; Semiconductor test system comprising a. The method according to claim 1 or 2, The detection or not determining means, Other inspection item determination means for determining whether the specific defect can be detected by another inspection item included in the plurality of inspection items when it is determined that the specific defect cannot be detected even by the other inspection items; And when it is determined by the other inspection item determining means that the specific defect is detectable, causing the inspection item deleting means to delete the specific inspection item from the plurality of inspection items managed by the inspection item managing means. Deletion Instructions Semiconductor test system comprising a. The method according to claim 1 or 2, The semiconductor device is a semiconductor test system, characterized in that the semiconductor memory. The method of claim 3, The semiconductor device is a semiconductor test system, characterized in that the semiconductor memory.

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