KR20070115057A - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided to improve operational characteristics by securing a pin capacitance value without performing an additional process or correcting a mask. A plurality of pads(10) are bonded with pins to be assigned to external signals. An auxiliary capacitance supply unit(14) adds auxiliary capacitance to pin capacitance of the pin connected to the corresponding pad. A selective connecting unit(12) connects selectively the corresponding pad with the auxiliary capacitance supply unit. The selective connecting unit includes at least one fuse which is connected between the corresponding pad and the auxiliary capacitance supply unit. The selective connecting unit connects selectively the corresponding pad with the auxiliary capacitance supply unit in response to a package type identification signal.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

1 is a block diagram of a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a first embodiment of the selective connection part and the auxiliary capacitance providing part of FIG. 1. FIG.

3 is a circuit diagram illustrating a second implementation of the optional connection portion and the auxiliary capacitance providing portion of FIG.

FIG. 4 is a circuit diagram illustrating a third embodiment of the optional connection part and the auxiliary capacitance providing part of FIG. 1. FIG.

FIG. 5 is a circuit diagram illustrating a fourth embodiment of the selective connection part and the auxiliary capacitance providing part of FIG. 1. FIG.

6 illustrates a circuit for generating a package type discrimination signal PACK.

* Explanation of symbols for the main parts of the drawings

10: pad

12: optional connection

14: auxiliary capacitance providing unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to package related techniques, and more particularly, to pin capacitance regulation with package type variations.

In general, semiconductor packages are classified into resin sealing packages, tape carrier packages (TCP), glass sealing packages, and metal sealing packages according to the type of sealing material, and are inserted and surface mounted according to the mounting method (Surface Mount Technology, SMT). Are classified as).

On the other hand, typical examples of the insertable package include DIP (Dual In-Line Package), PGA (Pin Grid Array), and typical surface mount packages include QFP (Quad Flat Package) and BGA (Ball Grid Array).

Recently, surface mount type semiconductor packages have been widely used rather than insert type semiconductor packages in order to increase component mounting of printed circuit boards due to miniaturization of electronic products.

A typical semiconductor package includes a semiconductor chip, a mounting plate on which the semiconductor chip is attached by epoxy, a plurality of leads capable of transmitting a signal of the semiconductor chip to the outside, a wire connecting the semiconductor chip and a lead frame, It consists of a resin encapsulation material wrapped around the outside to protect the semiconductor chip and other peripheral components from external oxidation and corrosion.

As described above, the semiconductor chip and the lead frame are wire-bonded in the packaging process, and the parasitic capacitance components of the bonding wires are different for each package type because the length of the bonding wires is different depending on the package type. For example, when the package type is TOSP-II and FBGA, the RLC component of the bonding wire is different, and the capacitance (C) component has the greatest influence among the RLC components, which is referred to as pin capacitance. .

However, a problem arises from the fact that the pin capacitance allowance margins are different for each package type. Since the margin margin is very small to meet all the pin capacitances of different package types, it is almost impossible to cover multiple package types with fixed pin capacitance considering actual process changes.

Therefore, conventionally, a package type is determined in advance from design time, and pin capacitance corresponding thereto is implemented as a default value, and when a change to another package type is required, a metal option is used to change the pin capacitance.

However, as is well known, the use of metal options involves problems requiring mask changes and additional processing.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device capable of adjusting the pin capacitance according to a package type change without an additional process.

According to an aspect of the present invention to solve the above technical problem, a plurality of pads and wire bonding pads assigned to each external signal; Auxiliary capacitance providing means for adding an auxiliary capacitance to a pin capacitance of a pin connected to the corresponding pad; And an optional connection means for selectively connecting the pad and the auxiliary capacitance providing means.

In the present invention, the auxiliary capacitance for adjusting the pin capacitance can be provided, and the auxiliary capacitance can be added or decreased by using a circuit which can be selectively connected, such as a fuse and a MOS transistor. In this case, the pin capacitance appropriate for each package type can be obtained without additional processing.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 is a block diagram of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 1, in the semiconductor device according to the present embodiment, an auxiliary capacitance is applied to a pin (not shown) assigned to an external signal, a wire bonded pad 10, and a pin capacitance of a pin connected to the pad 10. Auxiliary capacitance providing portion 14 for adding, and an optional connection portion 12 for selectively connecting the pad 10 and the auxiliary capacitance providing portion 14 is provided.

The pad 10 is wire bonded with a pin assigned to an external signal and thus has a unique pin capacitance. The optional connection part 12 adds the auxiliary capacitance to the pin capacitance by connecting the pad 10 and the auxiliary capacitance providing unit 14 as necessary, thereby changing the actual pin capacitance.

FIG. 2 is a circuit diagram illustrating a first embodiment of the optional connection unit 12 and the auxiliary capacitance providing unit 14 of FIG. 1.

Referring to FIG. 2, the selective connection part 12 is implemented by a fuse f0 having one side connected to a pad, and the auxiliary capacitance providing part 14 has a drain connected to the other side of the fuse f0 and an external power supply voltage terminal. The PMOS transistor MP0 has a source and a gate connected to (VDD).

In this case, the auxiliary capacitance providing unit 14 has an auxiliary capacitance corresponding to the junction capacitance of the PMOS transistor MP0. Therefore, when the fuse f0 is connected, the junction capacitance of the PMOS transistor MP0 may be added to the pin capacitance inherent to the pin bonded to the pad. On the other hand, when the fuse f0 is cut, the total pin capacitance is determined as a pin capacitance inherent to the pin bonded with the pad.

3 is a circuit diagram illustrating a second embodiment of the optional connector 12 and the auxiliary capacitance providing unit 14 of FIG. 1.

Referring to FIG. 3, the selective connection part 12 is implemented with a plurality of fuses f1, f2, f3,..., One side of which is connected to a pad, and the auxiliary capacitance providing part 14 includes a plurality of fuses f1, A plurality of NMOS transistors (MN1, MN2, MN3, ...) having drains connected to the other sides of f2, f3, ...) and a source and a gate connected to the ground voltage terminal VSS are implemented.

In this case, since the combination of the junction capacitance that can be provided by the plurality of NMOS transistors (MN1, MN2, MN3, ...) is various, it is possible to provide a variety of auxiliary capacitance compared to the circuit of FIG. There is a wide range of pin capacitance adjustment.

For example, assuming that the number of fuses connected to the pad is three, and that the junction capacitance of each NMOS transistor connected to each fuse is 1 pF, if one of the fuses is cut, the auxiliary capacitance of 2 pF is fused. Cutting two of them adds 1pF of auxiliary capacitance to the pin capacitance value.

4 is a circuit diagram illustrating a third embodiment of the optional connector 12 and the auxiliary capacitance providing unit 14 of FIG. 1.

Referring to FIG. 4, the optional connector 12 corresponds to each of a plurality of pads (eg, an I / O pad, an address pad, a DQ pad, etc.), and uses a package type discrimination signal (PACK) as a gate input to each pad. A plurality of NMOS transistors MN10, MN11, MN12, ... connected to drains are implemented, and the auxiliary capacitance providing unit 14 has a drain connected to a source of each of the plurality of NMOS transistors MN10, MN11, MN12, ... And a plurality of NMOS transistors (MN20, MN21, MN22, ...) whose source and gate are connected to the ground voltage terminal (VSS).

In this case, since the package type discrimination signal PACK is used instead of the fuse, pin capacitance corresponding to each pad can be adjusted without performing a work such as cutting a fuse. That is, when the package type discrimination signal PACK is logic level high, each pad and a plurality of NMOS transistors MN20, MN21, MN22,... Are connected. When the package type discrimination signal PACK is logic level low, the pad and NMOS transistors are connected. (MN20, MN21, MN22, ...) are disconnected.

Of course, the NMOS transistors MN10, MN11, MN12, ... may be replaced with PMOS transistors, and the NMOS transistors MN20, MN21, MN22, ... may also be replaced with PMOS transistors and the external power supply voltage VDD instead of the ground voltage VSS. ) Can be applied.

FIG. 5 is a circuit diagram illustrating a fourth embodiment of the optional connector 12 and the auxiliary capacitance providing unit 14 of FIG. 1.

Referring to FIG. 5, based on one pad, the selective connection unit 12 may include a NMOS transistor MN40 having a drain connected to a pad and a package type discrimination signal PACK on a corresponding pad, and an NMOS transistor ( A plurality of fuses f11, f12, f13, ... connected to one side of the source of the MN40 is implemented, and the auxiliary capacitance providing unit 14 is provided on the other side of each of the plurality of fuses f11, f12, f13, ... A plurality of NMOS transistors MN30, MN31, MN32, ... have their drains connected and their sources and gates connected to the ground voltage terminal VSS.

Although not shown in detail, the NMOS transistors MN41, MN42, ... connected to other pads also have the same connection relationship.

That is, in this embodiment, the MOS transistor and the fuse are used together. In this case, it is possible to secure the pin capacitance optimized for the characteristics of each pad by determining whether to add the auxiliary capacitance by the package type distinguishing signal PACK and performing different fuse cutting for each pad.

6 is a diagram illustrating a circuit for generating a package type distinguishing signal PACK.

Referring to FIG. 6, the package type discrimination signal PACK generating circuit includes a fuse f20 connected between an external power supply voltage terminal VDD and an output node, a drain and a gate thereof connected to an output node, and a ground voltage terminal. An NMOS transistor MN0 having a source connected to VSS and an inverter INV0 for inverting a signal applied to an output node and outputting it as a package type distinguishing signal PACK. Reference numeral 'C' represents the capacitance of the output node.

When the fuse f20 is connected, the output node is charged through the fuse f20. Therefore, the package type distinguishing signal PACK is at a logic level low.

On the other hand, when the fuse f20 is cut, the output node is discharged through the NMOS transistor MN0 so that the package type distinguishing signal PACK transitions to a logic level high.

On the other hand, although the fuse circuit as described above may be used to generate the package type discrimination signal PACK, a pad for the package type discrimination signal PACK may be simply provided, and the pad and the ground voltage VSS pad or an external power supply voltage may be used. Another option is to connect the (VDD) pad with wire bonding.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various changes, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

For example, in the above-described embodiment, the case where the junction capacitance of the MOS transistor is used as an example in implementing the auxiliary capacitance of the auxiliary capacitance providing unit is described, but the present invention is applied even when the capacitance constituting the auxiliary capacitance is implemented in another manner. do.

According to the present invention, the pin capacitance value suitable for the package type can be secured without additional process or mask modification, and thus, the effect of improving the operating characteristics of the semiconductor device can be expected.

Claims (11)

A plurality of pads wire-bonded with pins assigned to each external signal; Auxiliary capacitance providing means for adding an auxiliary capacitance to a pin capacitance of a pin connected to the corresponding pad; And Selective connecting means for selectively connecting the pad and the auxiliary capacitance providing means A semiconductor device comprising a. The method of claim 1, The selective connection means, And at least one fuse connected between the pad and the auxiliary capacitance providing means. The method of claim 1, The selective connection means, And switching means for selectively connecting the pad and the auxiliary capacitance providing means in response to a package type discrimination signal. The method of claim 1, The selective connection means, A switching means connected to a corresponding pad and controlled by a package type distinguishing signal, And at least one first fuse connected between the other side of the switching means and the auxiliary capacitance providing means. The method of claim 3, The switching means, And the MOS transistor having a source-drain path between the pad and the auxiliary capacitance providing means. The method of claim 1, The selective connection means, One end of which is connected to a corresponding pad, the switching means being controlled by a package type distinguishing signal, And a plurality of fuses connected in parallel between the other side of the switching means and the auxiliary capacitance providing means. The method of claim 6, The switching means, And the MOS transistor having a source-drain path between the pad and the plurality of fuses, wherein the package type discrimination signal is a gate input. The method according to any one of claims 1 to 7, The auxiliary capacitance providing means, And an NMOS transistor whose drain is connected to said selective connection means, and whose source and gate are connected to a ground voltage terminal. The method according to any one of claims 1 to 7, The auxiliary capacitance providing means, And a PMOS transistor whose drain is connected to said selective connection means, and whose source and gate are connected to an external power supply voltage terminal. The method according to any one of claims 3 to 7, A second fuse connected between an external power supply voltage terminal and an output node, an NMOS transistor having a drain and a gate connected to the output node, and a source thereof connected to a ground voltage terminal, and a signal applied to the output node by inverting the package And a package type discrimination signal generating circuit including an inverter for outputting as a type discriminating signal. The method according to any one of claims 3 to 7, An external power supply voltage pad; A ground voltage pad; Package type discrimination signal pads; And a bonding wire connecting the package type discrimination signal pad and the external power voltage pad or the ground voltage pad.

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