KR20070108709A - Plasma display panel - Google Patents

Abstract

A plasma display panel is provided to ensure the uniform address discharge over the whole image display by forming a rear dielectric layer having different capacitance. Plural address electrodes(220) are formed on a rear substrate(210), and a rear dielectric layer(230) is formed on the address electrodes. Plural pairs of sustain electrodes(160) are formed on a front substrate(110) to intersect the address electrodes, and a front dielectric layer(170) is formed on the sustain electrodes. Barrier ribs(240) are formed between the rear and front substrates to define plural discharge cells. The rear dielectric layer has first capacitance at a portion of an edge of an image display, and second capacitance at a center portion of the image display.

Description

Plasma display panel {Plasma display panel}

1 is a plan view illustrating a plasma display apparatus including an AC plasma display panel having a surface discharge structure having three electrodes in the related art.

2 is a perspective view illustrating a plasma display panel according to an embodiment of the present invention.

FIG. 3 is a graph showing the thickness of the back dielectric layer according to the position of the plasma display panel shown in FIG. 2.

Explanation of symbols on the main parts of the drawings

100: plasma display panel 110: front substrate

120, 130: bus electrode 140, 150: branch electrode

160: sustain electrode pair 170: front dielectric layer

180: protective film 210: back substrate

220: address electrode 230: back dielectric layer

240: partition 250: phosphor layer

D _ij : discharge cell

The present invention relates to a plasma display panel, and more particularly, to a plasma display panel in which the display quality of an image is improved by improving the structure of the dielectric layer.

Recently, development of flat panel displays such as a liquid crystal display (LCD), a field emission display (FED), and a plasma display panel has been actively performed. These flat panel displays are rapidly replacing conventional cathode ray tubes (CRTs) through steadily improving resolution, brightness, contrast and viewing angle. In particular, the plasma display panel has been actively studied because it is possible to implement a large-area display device having a high resolution.

The plasma display panel may be classified into an alternating current type and a direct current type according to a discharge type. In the dual alternating current plasma display panel, at least one electrode is surrounded by a dielectric layer, and discharge is performed by an electric field of wall charge instead of direct charge transfer between the corresponding electrodes. On the other hand, in the DC plasma display panel, since the electrode is exposed to the discharge space and the electrode is damaged, and thus the life is reduced, the AC plasma display panel, in particular, three electrodes, for example, addresses An AC plasma display panel having a surface discharge structure having an electrode, a scan electrode and a sustain electrode is generally adopted.

1 is a plan view illustrating a plasma display apparatus including an AC plasma display panel having a surface discharge structure having three electrodes in the related art.

Referring to FIG. 1, the plasma display apparatus 60 is connected to the address electrodes A ₁ , A ₂ ,..., A _M of the plasma display panel 50 to selectively supply a driving pulse. 10); An X driver 20 connected to the scan electrodes X ₁ , X ₂ ,..., X _N to supply a driving pulse; And a Y driver connected to the sustain electrodes Y ₁ , Y ₂ ,..., Y _N to supply a driving pulse. The plasma display panel includes M address electrodes A ₁ , A ₂ ,..., A _M , N scan electrodes X ₁ , X ₂ ,..., X _N , and sustain electrodes Y ₁ ,. Y _2, ..., Y _N) of discharge cells constituting the M × N matrix structure formed on the junction of the sustain electrode pair consisting of (D _11, ..., includes a D _MN).

In addition, the plasma display device 60 digitizes an analog image signal input from the outside to output a digital image signal, and the digital image signal, various external inputs (CLK), a horizontal synchronization signal (HS), and the like. The system control unit 40 generates a control signal and a driving pulse according to the vertical synchronization signal VS, and supplies the control signal and the driving pulse to the address driver 10, the X driver 20, and the Y driver 30. It may further include.

In order to achieve gray levels, the plasma display panel 50 receives a driving pulse divided into several subfields having different discharge times to represent one image frame. For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second may be divided into eight subfields, and each subfield may be divided into the entire plasma display panel 50 again. It can be divided into a reset period for making the discharge uniformly, an address period for selecting the discharge cells, and a sustain period for implementing gradation according to the number of discharges. The reset period and the address period may be the same for each subfield, but the sustain period is increased at a rate of 2n (n = 0, 1, 2, 3, ..., 7) to implement gradation in each subfield. .

For example, when driving a plasma display panel having a VGA (video graphic array) resolution, it may be assumed that eight subfields are included within one frame period (16.67 ms). In addition, if the plasma display panel is driven by a selective writing method having excellent contrast, the scan electrodes X ₁ , X ₂ ,..., X _N are applied to the scan electrodes X ₁ , X _{2 ,.} The width of the driving pulse supplied can be set to about 2 to 3 μS. First, the address period required to implement one frame requires 11.52 ms calculated as 2 to 3 μS (width of driving pulse) × 480 lines (row resolution of VGA) × 8 (number of subfields) per frame. Typically has a value in the range 7.68 to 11.52 ms. In comparison, the sustain period is one reset period of 0.3 ms per frame, an address period in the range of 7.68 to 11.52 ms, an erasing period of 100 μS × 8 (number of subfields), and 1, considering the vertical synchronization signal VS. It may have a value ranging from 3.05 to 6.89 ms, minus the margin of the vertical synchronization signal VS of ms.

From the above results, the retention period of 3 ms or more can be secured in the case of VGA resolution, but if the resolution exceeds the VGA level, for example, if the HD (high density) level or the FHD (full high density) level is scanned, The number of electrodes is increased, and a sufficient holding period cannot be secured. In particular, since the sustain discharge starts immediately after the address discharge in the final discharge cells D _{1 N} , D _{2 N} ,..., D _{i N} ,..., D _{M N} , the driving margin for stable address discharge is reduced. There is a problem. As a result, in the plasma display panel having a resolution of HD or FHD, discharge in the edge regions (E ₁ region and E ₂ region) in which a sufficient sustain period cannot be secured as compared with the discharge cells in the center region (C region). It is difficult to obtain stable discharge and sufficient brightness in the cell.

In addition, in the plasma display panel having a high resolution of HD class or FHD class, due to the voltage drop caused by the load effect of the discharge cells formed on each address electrode, the address pulse is the first discharge cell D _{1 1} on the address electrode. _{, D 2 10, ..., D} 1, ... D M 1) end the discharge cell _{(D 1 N, D 2 N} , ..., D i N, ..., D M N) from to It is not uniformly transmitted, and the longer the distance, the lower the voltage of the address pulse. As a result, the address discharge does not occur sufficiently, the edge including a plasma display panel 50, the final discharge cells of the _(N D _1, D _{2 N,} ..., _N D _i, ..., D _{M N)} In the discharge cells of the region (E ₂ region), sustain discharge does not occur well, and thus the image quality may deteriorate.

Accordingly, a technical object of the present invention is to provide a plasma display panel capable of improving display quality degradation such as luminance due to reduction of an address period, and improving non-uniformity of display quality due to load effects. It is.

Plasma display panel according to the present invention for achieving the above technical problem, the rear substrate; A plurality of address electrodes extending on the rear substrate; A back dielectric layer formed on the address electrodes; A front substrate disposed opposite the rear substrate; A plurality of storage electrode pairs formed on the front substrate and crossing the address electrodes; A front dielectric layer formed on the sustain electrode pairs; And a partition wall formed between the back substrate and the front substrate to define a plurality of discharge cells, wherein the back dielectric layer has a first capacitance in at least a portion of an edge region of the image display portion, and in the central region of the image display portion. It has a second capacitance different from the said 1st capacitance.

In the present invention, the back dielectric layer having the first capacitance is an area corresponding to 10% of all the discharge cell rows on the address electrode in the direction of the center region from the first discharge cell on the address electrode to which the address pulse is first input. On the address electrode). Further, the back dielectric layer having the first capacitance has a region (second region) within 10% of all the discharge cell rows on the address electrodes from the last discharge cell on the address electrode to which the address pulse is finally input, from the last discharge cell on the address electrode toward the center region. It is formed on the address electrode. More preferably, the back dielectric layer having the first capacitance is an area corresponding to 10% of all discharge cell rows on the address electrode in the direction of the center region from the first discharge cell on the address electrode to which the address pulse is first input. Region) and an address pulse may be formed on an address electrode of a region (second region) corresponding to within 10% of all discharge cell rows on the address electrode from the last discharge cell on the address electrode to which the address pulse is finally input. .

The difference between the first and second capacitances may be determined by the difference in thickness of the back dielectric layer. In this case, the thickness of the back dielectric layer having the first capacitance is 8 to 13 μm, the thickness of the back dielectric layer having the second capacitance is 10 to 15 μm, and the thickness of the back dielectric layer having the first capacitance is the first thickness. Smaller than the thickness of the back dielectric layer with 2 capacitances. Alternatively, the thickness of the back dielectric layer having the first capacitance is 10 to 15 μm, the thickness of the back dielectric layer having the second capacitance is 8 to 13 μm, and the thickness of the back dielectric layer having the first capacitance is the second capacitance. It is larger than the thickness of the back dielectric layer with capacitance.

The partition wall may be a stripe type formed in one direction along the address electrode, or may be a closed partition wall formed by crossing partitions in different directions. The plasma display panel of the present invention may be applied to a plasma display device having a resolution of HD level or more in which the number of address electrode lines is 3072 or more and the number of sustain electrode pairs is 768 or more.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements.

2 is a perspective view illustrating a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 2, M address electrodes A ₁ , A ₂ ,..., A _i ,..., A _M ; 220 are disposed on the rear substrate 210. The address electrode 220 is coated by the back dielectric layer 230. On the rear dielectric layer 230, a partition wall 240 is formed to partition the discharge cells and seal the discharge gas. In FIG. 2, only the stripe-shaped partition wall formed of only one partition member in one direction is illustrated, but the partition wall 240 is not limited thereto, and partition walls of various patterns formed by crossing partition members in different directions, for example, a waffle, a matrix, It may be a matrix partition wall of a delta-like pattern. The phosphor layer 250 is formed inside the discharge cell to generate visible light by ultraviolet rays generated during discharge.

N storage electrode pairs Z ₁ , Z ₂ , ..., Z _j , ..., Z _N disposed on the front substrate 110 opposite to the rear substrate 210 to be orthogonal to the address electrode 220. 160 is disposed. Each of the sustain electrode pairs 160 may include branch electrodes 140 and 150 made of a transparent conductive material and bus electrodes 120 and 130 made of a metal material to compensate for resistance components of the branch electrodes 140 and 150, respectively. have. Each storage electrode pair 160 may function as a scan electrode Xj and a storage electrode Yj for driving the plasma display panel 100. The storage electrode pairs 160 are coated by the passivation layer 19 covering the front dielectric layer 170 and the front dielectric layer 170.

The plasma display panel 100 according to the present invention includes M address electrodes A ₁ , A ₂ ,..., A _i ,..., A _M ; 220 and N storage electrode pairs by the partition wall 240. Discharge cells D ₁₁ , ..., D _ij , ... forming an M × N matrix structure formed on the intersection of Z ₁ , Z ₂ , ..., Z _j , ..., Z _N ; 160. , D _MN ). In the case where the resolution of the plasma display panel of the present invention is HD, M is 1024 × 3, N is 768. If the resolution is FHD, M is 1920 x 3 and N is 1080.

The discharge cells D ₁₁ ,..., D _ij ,..., D _{MN of the} plasma display panel 100 have an addressing discharge according to the capacitance of the back dielectric layer 230 coating the address electrode 220. The addressing discharge characteristics such as the driving voltage for the same are different. Therefore, when other conditions such as the size of the discharge space determined by the height of the partition wall 240 and the width of the partition wall in the plasma display panel 100 are constant, the driving voltage for the addressing discharge may be reduced. It can depend on the capacitance.

Since the capacitance of the back dielectric layer 230 is determined by the thickness of the back dielectric layer 230, the thickness of the back dielectric layer 230 may be adjusted to affect addressing discharge characteristics. For example, when the thickness of the back dielectric layer 230 decreases to increase the capacitance, wall charges are more easily formed and address discharge is better performed. As a result, in one display panel, by varying the thickness of the back dielectric layer 230, it is possible to improve non-uniformity of display quality such as luminance deviation.

The back dielectric layer 230 of the plasma display panel 100 has a first capacitance in an edge region (eg, an E ₁ region, an E ₂ region) of at least a portion of the M × N matrix structure, and has a M × N matrix structure. In the central region (C region), the second region has a second capacitance different from the first capacitance. That is, the plasma display panel 100 according to the present invention includes a back dielectric layer 230 having capacitances different according to positions in an M × N matrix structure. In this case, the first capacitance may be larger or smaller than the second capacitance depending on the driving method of the plasma display panel 100, that is, the selective writing method or the selective erasing method.

An address pulse is the first discharge cells on the address electrode 220, which is the first input and the nearest (D _11, D _21, ..., D _i1, D ... _M1), that is, an address driver (10 in Fig. 1) All discharges on the address electrode 220 in the direction of the center region (region C) from the discharge cells D ₁₁ , D ₂₁ ,..., D _i1 ,... D _M1 on the end of the address electrode 220 to be connected. The back dielectric layer 230 formed in the discharge cell on the region (first region; E ₁ region) corresponding to 10% of the cell rows may have a first capacitance. Further, the final discharge cells D _1N , D _2N ,..., D _iN ,..., D _MN on the address electrode 220, that is, an address that is connected farthest from the address driver 10 of FIG. 1. The discharge cells D _1N , D _2N ,..., D _iN ,..., D _MN on the other end of the electrode 220 are arranged in a row of all the discharge cells on the address electrode 220 in the direction of the center region (C region). The back dielectric layer 230 formed in the discharge cells of the region (second region; E ₂ region) corresponding to within 10% may have a first capacitance. Alternatively, the back dielectric layer 230 formed in all of the discharge cells of the first region (E ₁ region) and the second region (E ₂ region) may have a first capacitance.

Meanwhile, the back dielectric layer 230 having different capacitances may be provided by adjusting the thickness t of the back dielectric layer 230. The back dielectric layer 230 having different thicknesses t may be formed by adjusting process variables of a screen printing method as is well known in the art.

FIG. 3 is a graph showing the thickness of the back dielectric layer according to the position of the plasma display panel shown in FIG. 2.

Referring to FIG. 3, for example, in an HD-class plasma display panel, a column of discharge cells disposed on the address electrode 220 includes 768 discharge cells, and among the discharge cells, an address driver (10 of FIG. 1). ) and the first discharge cell (D _{1 1,} D ₂ closest to the connected _{1, ..., D i 1,} ... D M from the _first), the discharge cells corresponding to not more than 10% of the discharge cell (D _{1 1} D _{1 77} ; D _{1 1} ..., D _{i 77} ; D _{M 1} , ..., D _{M 77} ) and the back dielectric 230 of the first capacitance having a thickness t ₁ . Can be formed. In addition, from the last discharge cells D _{1 N} , D _{2 N} ,..., D _{N N} ..., D _MN , which are connected farthest from the address driver, among the discharge cells, 10% or less of the total discharge cells. the corresponding discharge cell _{(D 1 692, ..., D} 1 768; D i 692, ..., D i 768; D M 692, ..., D M 768) the thickness (t ₁₎ in the A back dielectric layer 230 having a first capacitance having the same may be formed. If necessary, the first region (E ₁ region) and the second region (E ₂ region) in which the back dielectric cell having the first capacitance is formed may be smaller than the 10%, and are formed on the address electrode 220. First (D _{1 1} , D _{2 1} , ..., D _{i 1} , ... D _{M 1} ) and / or final discharge cells (D _{1 N} , D _{2 N} , ..., D _{i N} , .. ., D _MN) only it may be a rear dielectric layer 230 of the first capacitance has a thickness (t ₁₎ is formed.

The thickness t ₁ of the back dielectric layer 230 having the first capacitance may have a difference of about 1 μm to 3 μm from the thickness t ₂ of the back dielectric layer 230 having the second capacitance. For example, in the case of the selective writing method (I mode), the thickness t ₁ of the back dielectric layer 230 having the first capacitance is smaller than the thickness t ₂ of the back dielectric layer 230 having the second capacitance. Can be. On the other hand, in the selective erasing method (II mode), the thickness t ′ ₁ of the back dielectric layer 230 having the first capacitance may be greater than the thickness t ₂ of the back dielectric layer 230 having the second capacitance. have.

For example, in the selective writing method (I mode), the thickness t ₁ of the back dielectric layer 230 having the first capacitance is 8 to 13 μm and the thickness t ₂ of the back dielectric layer 230 having the second capacitance. ) Is 10 to 15 μm, wherein the thickness t ₁ of the back dielectric layer 230 having the first capacitance is smaller than the thickness t ₂ of the back dielectric layer 230 having the second capacitance. On the other hand, in the selective erasing method (II mode), the thickness t ′ ₁ of the back dielectric layer 230 having the first capacitance is 10 to 15 μm, and the thickness of the back dielectric layer 230 having the second capacitance ( t ₂ ) is 8 to 13 μm, wherein the thickness t ′ ₁ of the back dielectric layer 230 having the first capacitance is greater than the thickness t ₂ of the back dielectric layer 230 having the second capacitance.

As described above, in the selective writing method (I mode), since the larger the capacitance, the easier the address discharge occurs, the first discharge cell D having the back dielectric layer 230 having the first capacitance on the first region (E ₁ region) is formed. _The discharge cells including _{1 1} , D _{2 1} , ..., D ₁ , ... D _{M 1} ) are primed discharges to facilitate the address discharge of the discharge cells arranged in the center region (C region). Can act as a cell Similarly, the discharge cell in which the back dielectric layer 230 having the first capacitance on the second region (E ₂ region) is formed is used for the sustain discharge by the increased capacitance even if the voltage of the applied address pulse is weakened by the load effect. The address discharge can be sufficiently secured. As a result, the back dielectric layer 230 having the first capacitance on the first region (E ₁ region) and / or the second region (E ₂ region) can obtain uniform address discharge over the entire plasma display panel 100. Make sure

Similarly, in the selective erasing method (II mode), the first capacitance can be made smaller than the second capacitance, thereby improving the nonuniformity of the address discharge of the plasma display panel 100. Therefore, the plasma display panel of the present invention can improve the display quality unevenness due to the reduced address period and load effect due to the increase in resolution, and thus, the plasma display panel has a resolution of HD or FHD or higher resolution. Can be applied.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and alterations are possible within the scope without departing from the technical spirit of the present invention, which are common in the art. It will be apparent to those who have knowledge.

The plasma display panel of the present invention comprises a back dielectric layer having a first capacitance in at least some of the edge regions of the image display portion, and a back dielectric layer having a second capacitance different from the first capacitance in the central region of the image display portion. Uniform address discharges can be ensured throughout to provide an extended drive margin for uniform display quality and faithful address discharges.

In addition, since the plasma display panel of the present invention can be driven in a single scan at a high resolution by an extended driving margin, an additional driving circuit can be omitted, thereby providing a plasma display device having a simpler structure.

Claims (9)

Back substrate; A plurality of address electrodes extending on the rear substrate; A back dielectric layer formed on the address electrodes; A front substrate disposed opposite the rear substrate; A plurality of storage electrode pairs formed on the front substrate and crossing the address electrodes; A front dielectric layer formed on the sustain electrode pairs; And A barrier rib formed between the rear substrate and the front substrate to define a plurality of discharge cells, And the back dielectric layer has a first capacitance in at least a portion of an edge region of the image display portion, and has a second capacitance different from the first capacitance in a central region of the image display portion. The method of claim 1, The back dielectric layer having the first capacitance is an address electrode of a region (first region) corresponding to within 10% of all the discharge cell rows on the address electrode from the first discharge cell on the address electrode to which the address pulse is first input from the first discharge cell on the address region toward the center region. Plasma display panel formed on. The method of claim 1, The back dielectric layer having the first capacitance is an address electrode of a region (second region) corresponding to within 10% of all discharge cell rows on the address electrode from the last discharge cell on the address electrode to which an address pulse is finally input, toward the center region. Plasma display panel formed on. The method of claim 1, The back dielectric layer having the first capacitance includes an area (first area) and an address pulse corresponding to within 10% of all discharge cell rows on the address electrode from the first discharge cell on the address electrode to which the address pulse is first input, toward the center area. A plasma display panel formed on an address electrode of a region (second region) corresponding to within 10% of all discharge cell rows on the address electrode from the last discharge cell on the address electrode to which the terminal is finally input. The method of claim 1, The difference between the first and second capacitances is determined by the difference in the thickness of the back dielectric layer. The method of claim 5, The thickness of the back dielectric layer having the first capacitance is 8 to 13 μm, the thickness of the back dielectric layer having the second capacitance is 10 to 15 μm, and the thickness of the back dielectric layer having the first capacitance is the second capacitance. And a plasma display panel smaller than the thickness of the back dielectric layer. The method of claim 5, The thickness of the back dielectric layer having the first capacitance is 10 to 15 μm, the thickness of the back dielectric layer having the second capacitance is 8 to 13 μm, and the thickness of the back dielectric layer having the first capacitance is the second capacitance. And a plasma display panel larger than the thickness of the back dielectric layer. The method of claim 1, The partition wall may be a stripe type formed in one direction along the address electrode or a closed type partition wall formed by crossing partitions in different directions. The method of claim 1, And the number of address electrodes is 3072 or more, and the number of sustain electrode pairs is 768 or more.

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