KR20070105240A - Wiring substrate, display device and manufacturing method thereof - Google Patents

Abstract

A wiring substrate, a display device and a fabrication method thereof are provided to improve covering and a pressure-resistant by providing a line with a stacked structure, which is formed in a desired sectional shape. A first metal layer including aluminum is coated on a substrate(110). A second metal layer including molybdenum is coated on the first metal layer. A resist pattern is coated on the second metal layer. The first metal layer and the second metal layer are etched via the resist pattern for side-etching to be performed on the first metal layer and the second metal layer. After the etching process, an ashing process is performed to retreat the resist pattern to expose a surface of a end side of the second metal layer. After the ashing process, etching is performed through the retreated resist pattern for the second metal layer to be a cross-section which is tapered forwardly.

Description

Wiring board, display device and manufacturing method thereof {WIRING SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF}

1 is a plan view showing the structure of a TFT array substrate according to an embodiment of the present invention.

2 is a plan view showing the TFT structure of the TFT array substrate according to the embodiment of the present invention.

3 is a cross-sectional view showing the TFT structure of the TFT array substrate according to the embodiment of the present invention.

4 is a flowchart showing a manufacturing process of the TFT array substrate according to the embodiment of the present invention.

Fig. 5 is a cross sectional view showing a configuration in an etching step of a TFT array substrate according to the embodiment of the present invention.

Fig. 6 is a cross sectional view showing a configuration in an etching step of a TFT array substrate according to the embodiment of the present invention.

7 is a cross-sectional view showing the configuration of an TFT array substrate in an etching process according to an embodiment of the present invention.

Fig. 8 is a cross-sectional view showing the construction of the TFT array substrate in the etching step of the embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a configuration in an etching process of a TFT array substrate according to an embodiment of the present invention. FIG. 9A is a diagram schematically showing a solid angle Ω _B at which an etchant is allowed to enter at point _B. FIG. 9B. Is a diagram schematically showing solid angle Ω _D at which an etchant is allowed to enter at point _D. FIG.

10 is a cross-sectional view showing another configuration in the etching step of the TFT array substrate according to the embodiment of the present invention.

11 is a cross-sectional view showing another configuration in the etching step of the TFT array substrate according to the embodiment of the present invention.

12 is a cross-sectional view showing another configuration in the etching step of the TFT array substrate according to the embodiment of the present invention.

Fig. 13 is a sectional view showing the structure of a conventional TFT.

Explanation of symbols on the main parts of the drawings

11: source wiring 12: pixel electrode

13: gate wiring 14: gate insulating film

15: semiconductor layer 16: source electrode

17: drain electrode 18: interlayer insulating film

19: contact hole 31: lower layer

32: upper layer 33: resist pattern

34: laminated structure 35: bounce radical

36: radical 110: substrate

111: display area 112: boundary area

115: scan signal driver circuit 116: display signal driver circuit

117: pixel 118: external wiring

119: external wiring 120: pixel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, a display device, and a manufacturing method thereof, and more particularly, to a wiring board having wiring in which a metal film is laminated, a display device using the same, and a manufacturing method thereof.

Recently, as a display device replacing a CRT display, a flat display device has been widely used. In particular, liquid crystal displays and organic EL (electroluminescence) displays have attracted attention from the advantages of light weight, ultra-thin, and low power consumption. As one of driving methods of a liquid crystal display device and an organic EL display device, there is an active matrix type using a switching element. In the active matrix type, for example, a TFT, which is a switching element, is electrically connected to each pixel electrode. That is, in the active matrix display device, a TFT array substrate in which TFTs are arranged in an array form is used. Therefore, in an active matrix liquid crystal display device or the like, good display without crosstalk between adjacent pixels is realized. In current flat display devices, the active matrix type is the mainstream.

In order to reduce the manufacturing cost of a flat panel display device, the reduction of the manufacturing cost of a TFT array substrate is also a big subject. Techniques for producing a TFT array substrate in a smaller number of patterns have been considered. That is, the technique of simplifying a manufacturing process is considered by reducing the frequency | count of the exposure process by a photomask.

On the other hand, with the miniaturization of display devices, aluminum or alloys thereof (hereinafter, Al or the like) have been used as the wiring material. That is, wiring resistance can be reduced by using Al etc. as a material of signal wiring. However, in the metal thin film which consists of Al etc., a hillock arises by the heating in a manufacturing process. Therefore, there exists a problem of reducing the insulation of a coating insulating film. Therefore, the technique which makes wiring the laminated structure which laminated | stacked the molybdenum (Mo) layer on Al etc. is proposed.

However, at Al and Mo, the rate (etching rate) to be etched is very different. Therefore, a big difference occurs in the degree of side etching. A recess, an overhang, or the like is formed in the side end surface of the metal wiring pattern obtained by etching. Therefore, the problem that the coating | cover property by an insulating film falls is produced.

13, a TFT having a lamination structure of Al and Mo will be described. Fig. 13 is a sectional view showing the structure of a conventional TFT. 12 is a pixel electrode, 13 is a gate wiring, 14 is a gate insulating film, 15 is a semiconductor film, 16 is a source electrode, 17 is a drain electrode, 18 is an interlayer insulating film, and 19 is a contact hole. Here, the gate wiring 13 has the laminated structure of the lower layer 31 which consists of Al etc., and the upper layer 32 which consists of Mo.

As shown in Fig. 13, the overhang shape of the upper layer 32 made of Mo causes a gap due to variations in the wet etching process or the like. As shown in part E of FIG. 13, when the overhang protruding portion is large, the covering property of the gate insulating film 14 is deteriorated. As a result, defects such as disconnection occur in the drain electrode 17 thereon. In addition, even in a location where there is no problem in the coating property as shown in the F portion, the tip portion of the upper layer 32 becomes an acute angle. Therefore, there is a problem that electric field concentration occurs, and a voltage drop failure occurs.

A technique for such a problem is disclosed. (See Patent Documents 1 and 2)

[Patent Document 1] Japanese Patent Application Laid-Open No. 2001-166336

[Patent Document 2] Japanese Patent Application Laid-Open No. 2001-311954

In patent document 1, the liquid composition of an etchant is prescribed | regulated, and the etching rate is made to the same grade. On the other hand, in patent document 2, elements, such as chromium and a zirconium, are added to molybdenum, and the etching rate is made to the same grade. However, in the above technique, there is a problem that it is difficult to process the wiring into a desired cross-sectional shape. That is, when the film thickness or composition is changed, overhangs and recesses are formed on the side surfaces. Moreover, the cross-sectional shape of a wiring may change with the state of the base film of wiring. In addition, the range of material selection may be significantly narrowed.

As mentioned above, in the conventional wiring board, when there exists a metal film containing Mo on the metal film containing Al, there existed a problem that a coating property and insulation fell.

This invention is made | formed in view of such a problem, and an object of this invention is to provide the wiring board which has wiring of the laminated structure formed in desired cross-sectional shape, a display apparatus, and those manufacturing methods.

The manufacturing method of the wiring board which concerns on the 1st aspect of this invention is a manufacturing method of the wiring board which uses the laminated structure which consists of at least a 1st metal film and a 2nd metal film as wiring, Comprising: Aluminum is included on a board | substrate. Forming a first metal film; forming a second metal film containing molybdenum on the first metal film; forming a resist pattern on the second metal film; A first etching step of etching the first metal film and the second metal film through the resist pattern to side-etch the first metal film and the second metal film, and the first etching step After, the ashing step of retracting the resist pattern so as to expose the surface of the side end of the second metal film, and after the ashing step, the cross section of the second metal film is in a forward tapered shape. Via a retracted resist pattern is provided with a process of etching the second etching.

EXAMPLE

In the following, embodiments to which the present invention is applicable are described. The following description describes the embodiments of the present invention, and the present invention is not limited to the following embodiments. For clarity of explanation, the following descriptions are omitted and simplified as appropriate. Moreover, those skilled in the art will be able to easily change, add, and convert each element of the following embodiments within the scope of the present invention. Under the present circumstances, the same code | symbol is shown in each figure, and the same element is shown, and description is abbreviate | omitted suitably.

A display device according to an embodiment of the present invention will be described with reference to FIG. 1 is a front view showing the configuration of a substrate used in the display device according to the present embodiment. As the display device according to the present embodiment, a flat panel display (flat panel display) such as a liquid crystal display device or an organic EL display device may be mentioned.

The liquid crystal display device according to the present embodiment has a substrate 110. The substrate 110 is, for example, a wiring substrate such as a thin film transistor (TFT) array array substrate. The substrate 110 is provided with a display region 111 and a boundary region 112 provided to surround the display region 111. In this display area 111, a plurality of gate wirings (scanning signal lines) 13 and a plurality of source wirings (display signal lines) 11 are formed. The plurality of gate wirings 13 are provided in parallel. Similarly, the plurality of source wirings 11 are provided in parallel. The gate wiring 13 and the source wiring 11 are formed to cross each other. The gate wiring 13 and the source wiring 11 are orthogonal to each other. The pixel 117 is an area surrounded by the adjacent gate wiring 13 and the source wiring 11. Therefore, in the substrate 110, the pixels 117 are arranged in a matrix form.

In addition, the scan signal driving circuit 115 and the display signal driving circuit 116 are provided in the boundary region 112 of the substrate 110. The gate wiring 13 extends from the display region 111 to the boundary region 112. The gate wiring 13 is connected to the scan signal driving circuit 115 at the end of the substrate 110. Similarly, the source wiring 11 extends from the display region 111 to the boundary region 112. The source wiring 11 is connected to the display signal driving circuit 116 at the end of the substrate 110. The external wiring 118 is connected in the vicinity of the scan signal driving circuit 115. In addition, the external wiring 119 is connected near the display signal driving circuit 116. The external wirings 118 and 119 are wiring boards, such as flexible printed circuits (FPC), for example.

Various signals from the outside are supplied to the scan signal driver circuit 115 and the display signal driver circuit 116 via the external wirings 118 and 119. The scan signal driver circuit 115 supplies a gate signal (scan signal) to the gate wiring 13 based on an external control signal. The gate wiring 13 is sequentially selected by this gate signal. The display signal driver circuit 116 supplies the display signal to the source wiring 11 based on an external control signal or display data. Accordingly, the display voltage according to the display data can be supplied to each pixel 117. At this time, the scan signal driver circuit 115 and the display signal driver circuit 116 are not limited to the configuration disposed on the substrate 110. For example, you may connect a drive circuit by TCP (Tape Carrier Package).

At least one thin film transistor (TFT) 120 is formed in the pixel 117. The TFT is disposed near the intersection of the source wiring 11 and the gate wiring 13. For example, this TFT supplies a display voltage to the pixel electrode. That is, the TFT which is a switching element is turned on by the gate signal from the gate wiring 13. As a result, a display voltage is applied from the source wiring 11 to the pixel electrode connected to the drain electrode of the TFT. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. At this time, an alignment film (not shown) is formed on the surface of the substrate 110.

Moreover, the opposing board | substrate is arrange | positioned facing the board | substrate 110. As shown in FIG. The counter substrate is, for example, a color filter substrate and is disposed on the viewer side. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed. In addition, the counter electrode may be disposed on the substrate 110 side. The liquid crystal layer is sandwiched between the substrate 110 and the counter substrate. That is, the liquid crystal is injected between the substrate 110 and the counter substrate. In addition, a polarizing plate, a retardation plate, and the like are provided on the outer surface of the substrate 110 and the counter substrate. In addition, a backlight unit or the like is disposed on the side opposite to the liquid crystal display panel.

The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode. That is, the orientation direction of the liquid crystal between substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarized state of the light passing through the polarizing plate and becoming linearly polarized light is changed by the liquid crystal layer. Specifically, the light from the backlight unit is linearly polarized by the polarizing plate on the array substrate side. The polarization state changes by passing the linearly polarized light through the liquid crystal layer.

Therefore, the amount of light passing through the polarizing plate on the opposite substrate side changes depending on the polarization state. That is, the amount of light passing through the polarizing plate on the viewing side of the transmitted light passing through the liquid crystal display panel from the backlight unit changes. The orientation direction of a liquid crystal changes with the display voltage applied. Therefore, by controlling the display voltage, the amount of light passing through the polarizing plate on the viewing side can be changed. That is, the desired image can be displayed by changing the display voltage for each pixel.

In the present invention, the substrate 110 is described as a TFT array substrate having a bottom gate type structure used for a liquid crystal display device. The configuration of the substrate 110 according to the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a plan view schematically showing the configuration of the TFT portion of the substrate 110, and FIG. 3 is a cross-sectional view taken along line A-A of FIG. 2, and schematically shows the configuration of the TFT portion of the substrate 110. As shown in FIG.

11 is a source wiring, 12 is a pixel electrode, 13 is a gate wiring, 14 is a gate insulating film, 15 is a semiconductor film, 16 is a source electrode, 17 is a drain electrode, 18 is an interlayer insulating film, and 19 is a contact hole.

On the substrate 110, a gate wiring 13 having a gate electrode is formed. Here, although the gate electrode of the TFT 120 is contained in the gate wiring 13, it is good also as a structure which extends a gate electrode from the gate wiring 13. FIG. The gate wiring 13 has a laminated structure of the lower layer 31 and the upper layer 32. Here, the lower layer 31 is comprised from aluminum (Al) or an aluminum alloy (henceforth collectively called Al etc.). That is, the lower layer 31 is a conductive metal layer containing aluminum. Thus, as the lower layer 31, an alloy containing Al or Al as a main component can be used. On the lower layer 31, the upper layer 32 is provided. The upper layer 32 includes molybdenum (Mo). For the upper layer 32, Mo or an alloy containing Mo as a main component can be used. On the lower layer 31, the upper layer 32 is directly formed. That is, the upper surface of the lower layer 31 and the bottom surface of the upper layer 32 are in contact with each other.

The gate insulating film 14 is formed on the gate wiring 13. The gate insulating film 14 is formed to cover the gate wiring 13. That is, the gate wiring 13 is covered with the gate insulating film 14.

Here, the gate wiring 13 is patterned by the etching process mentioned later, or the like. Thereby, the gate wiring 13 which consists of a laminated structure of the lower layer 31 containing Al and the upper layer 32 containing Mo can be made into a forward taper shape. Thereby, the covering property of the gate wiring 13 can be improved. Therefore, disconnection of the conductive layer on the gate insulating film 14 and occurrence of breakdown voltage failure can be prevented. Thus, the gate wiring 13 can be made into a desired cross-sectional shape. This etching process etc. are demonstrated in detail later.

The semiconductor film 15 is formed on the gate insulating film 14. The semiconductor film 15 is composed of, for example, an a-Si layer or a p-Si layer. In addition, for example, impurities such as phosphorus (P) are injected into the semiconductor film 15. The semiconductor film 15 is composed of, for example, a semiconductor active layer and an ohmic contact layer. Here, in the channel of the TFT 120, the ohmic contact layer is removed and the semiconductor active layer is exposed. Sources and drains of the TFTs 120 are formed on both sides of this channel.

The source electrode 16 and the drain electrode 17 are formed on the ohmic contact layer of the semiconductor film 15. This source electrode 16 extends from the source wiring 11. Here, the source electrode 16 and the drain electrode 17 are provided with the same metal thin film as the source wiring 11. Specifically, the source electrode 16 and the drain electrode 17 have a three-layer structure of Mo / Al / Mo in the following order. Of course, you may use other materials. The source electrode 16 is provided at one end of the pattern of the semiconductor film 15, and the drain electrode 17 is provided at the other end. That is, the source electrode 16 and the drain electrode 17 face each other via the channel.

In addition, an interlayer insulating film 18 is formed on the source electrode 16 and the drain electrode 17. The interlayer insulating film 18 is formed to cover the channel portion, the source electrode 16, the drain electrode 17, and the source wiring 11 of the semiconductor film 15. In addition, a contact hole 19 for connecting to the drain electrode 17 is formed in the interlayer insulating film 18.

The pixel electrode 12 is formed on the interlayer insulating film 18. The pixel electrode 12 is embedded in the contact hole 19. Therefore, the pixel electrode 12 is connected to the drain electrode 17 via the contact hole 19. As a result, the display voltage from the source wiring 11 is supplied to the pixel electrode 12 via the TFT. The pixel electrode 12 is formed of, for example, a transparent conductive film such as ITO. At this time, in the reflective or semi-transmissive liquid crystal display device, the pixel electrode 12 is formed of a reflective electrode such as a metal film. This pixel electrode 12 is provided in approximately the entire pixel, for example. When the display voltage is applied, the pixel electrode 12 generates an electric field for driving the liquid crystal between the counter electrode (not shown).

Next, the manufacturing process of the above-mentioned TFT array substrate is explained using FIG. 4 is a flowchart illustrating a manufacturing process of the substrate 110. First, the gate wiring 13 is formed (step S10l). Specifically, the lower layer 31 and the upper layer 32 are successively formed on the insulating substrate 110 by the sputtering method. Here, an AlCu alloy film is used as the metal film of the lower layer 31, and a MoNb alloy film is used as the metal film of the upper layer 32. At this time, the composition ratio of each layer is not particularly limited. The film thickness of the lower layer 31 is determined by the wiring resistance, and can be, for example, 200 nm. In addition, the film thickness of the upper layer 32 is made into 100 nm in consideration of the film | membrane reduction amount by the contact hole etching of a post process. Then, a resist film is applied on the lower layer 31 and the upper layer 32. This resist film is exposed using the photomask in which the predetermined | prescribed mask pattern was formed. When the exposed resist film is developed, a resist pattern according to the pattern of the gate wiring 13 is formed on the substrate 110. At this time, the storage capacitor electrode or the like may be formed in the same process as the formation of the gate wiring 13.

The upper layer 32 and the lower layer 31 are etched through this resist pattern. That is, the gate wiring 13 provided in the substantially whole surface of the board | substrate 110 is patterned. When the resist pattern is removed, the gate wiring 13 is formed. The process of etching the upper layer 32 and the lower layer 31 will be described later in detail. In this embodiment, the cross section of the gate wiring 13 is in a forward tapered shape. In other words, the pattern width of the gate wiring 13 is widened as it approaches the substrate 110. Thereby, coating property and pressure resistance can be improved.

Next, a gate insulating film 14 is formed (step S102). Then, the semiconductor film 15 is formed (step S103). Specifically, the gate insulating film 14 and the semiconductor film 15 are successively formed by the CVD method. For example, as the gate insulating film 14, an inorganic insulating film such as SiNx or SiO ₂ can be used. The gate wiring 13 is covered by the gate insulating film 14. Here, since the gate wiring 13 has a forward taper shape in cross section, the covering property is good. As the semiconductor film 15, an a-Si film or a p-Si film can be used. Then, the semiconductor film 15 is patterned using a photolithography process. That is, resist coating, exposure, development, etching, and resist peeling are performed. Thereby, the semiconductor film 15 can be processed into a desired pattern. Impurities are implanted into this semiconductor film 15. The impurity implantation step is not particularly limited.

Then, from above the patterned semiconductor film 15, the source electrode 16, the source wiring 11, and the drain electrode 17 are formed (step S104). Specifically, a metal thin film is formed by sputtering on the semiconductor film 15 and the gate insulating film 14. Then, patterning is performed by a photolithography process. That is, resist coating, exposure, development, etching, and resist peeling are performed. Thereby, the metal thin film can be processed into a desired pattern. For etching, for example, wet etching using a predetermined etchant can be used. The source wiring 11, the source electrode 16, and the drain electrode 17 can be formed. Here, the source wiring 11, the source electrode 16, and the drain electrode 17 can have a three-layer structure composed of Mo / Al / Mo in the following order.

In addition, an interlayer insulating film 18 is formed over the source wiring 11, the source electrode 16, and the drain electrode 17 (step S105). As the interlayer insulating film 18, a SiNx film can be used. For example, a nitride film of 100 to 400 nm is formed by CVD. Then, the nitride film is patterned by a photolithography process. Accordingly, the interlayer insulating film 18 having the contact hole 19 formed on the drain electrode 17 can be formed. As the interlayer insulating film 18, an organic insulating film or another inorganic insulating film may be used. Moreover, you may laminate | stack the insulating film of another material. Thereby, the short circuit by the occurrence of a pinhole etc. can be reliably prevented.

Next, the pixel electrode 12 is formed over the interlayer insulating film 18. Specifically, a transparent conductive film such as an ITO film is formed by sputtering or the like. Then, patterning is performed by a photolithography process. As a result, the pixel electrode 12 is formed. The pixel electrode 12 is provided in approximately the entire pixel, for example. The drain electrode 17 and the pixel electrode 12 come into contact with each other via the contact hole 19, and the TFT 120 and the pixel electrode 12 are connected. TFT and a pixel are formed by the above process. By arranging these pixels in an array, a TFT array substrate is formed.

Next, the formation process S10l of the gate wiring 13 is demonstrated in detail using FIGS. 5-10 is a process cross-sectional view which shows the cross-sectional shape in the pattern formation process of the gate wiring 13. FIG. 5 to 10, the configuration near the side cross section of the gate wiring 13 is shown. Here, an upper layer (Mo layer) 32 is provided on the lower layer (Al layer) 31. Here, the two-layer structure of the lower layer 31 and the upper layer 32 is a laminated structure 34. In addition, a resist pattern 33 is formed on the upper layer 32. The resist pattern 33 is formed by going through a resist film coating, exposure, and developing process. The resist pattern 33 is in the form of a forward taper, as shown in FIG.

Subsequently, a first etching is performed using a chemical liquid (etchant) containing phosphoric acid + nitric acid + acetic acid as a component. As a result, the Mo / Al stack structure 34 including the lower layer 31 and the upper layer 32 is collectively etched. The first etching is performed through the resist pattern 33 after development. Therefore, the lower layer 31 and the upper layer 32 of the opening of the resist pattern 33 are removed by wet etching. As a result, the configuration shown in FIG. 6 is obtained. In the opening of the resist pattern 33, the lower layer 31 and the upper layer 32 are removed, and the substrate 110 serving as the base is exposed. Here, 100% overetching is performed on the just etching time of the laminated structure 34. That is, wet etching is performed in twice the time of just etch time. Thereby, the etching residue of the lower layer 31 by the gap of an etching rate can be prevented.

At this time, the side etch amount of the lower layer 31 is 0.5 micrometer, for example. In wet etching, the etching rate of the upper layer 32 decreases due to the battery effect between Mo and Al. Therefore, the side end surface of the laminated structure 34 becomes an inverse taper shape in the upper layer 32, and becomes a forward taper shape in the lower layer 31. As shown in FIG. Therefore, the cross-sectional shape of the laminated structure 34 becomes the shape which entered most in the interface of the upper layer 32 and the lower layer 31. As shown in FIG. Thus, the laminated structure 34 has the cross-sectional shape which was narrow at the interface of the upper layer 32 and the lower layer 31. As shown in FIG. In addition, the side end part of the upper layer 32 becomes a lid shape. The tip of the lid portion of the upper layer 32 is acute. In addition, by side etching of the laminated structure 34, the side end surface of the laminated structure 34 exists inside the side end surface of the resist pattern 33. Therefore, the cover shape A which the side end part of the resist pattern 33 protruded from the edge of the upper layer 32 is formed.

Next, the resist pattern 33 is half ashed by an inductively coupled plasma generator. Specifically, the resist pattern 33 retreats by exposing the resist pattern 33 to the O ₂ plasma. For example, radicals 36 and the like of oxygen generated in the O ₂ plasma collide with the surface of the resist pattern 33. For this reason, ashing advances in the surface side of the resist pattern 33. FIG. As a result, the resist pattern 33 is reduced in thickness. Therefore, part of the resist pattern 33 is removed, and the film thickness becomes thin. 7 shows the shape during this ashing process.

Specifically, the process time can be 60 seconds at O ₂ = 2.54 × 10 ⁻¹ Pa · m ³ / sec (= 150 sccm), RF power = 800 W, and processing pressure = 6.0 Pa. At this time, as shown in FIG. 7, the cover shape A of the resist pattern 33 is ashed from the bottom surface by the bounce radicals 35 from the substrate 110. In other words, the radicals 36 generated in the oxygen plasma retreat from the upper surface of the substrate 110 or the upper layer 32. The returned radicals 35 collide with the resist pattern 33 on the bottom surface side. Thereby, the radical 35 which collides with the surface (bottom surface) of the upper layer 32 side of the resist pattern 33 collides, and ashing advances also in the bottom surface side of the resist pattern 33. FIG. Thereby, the side end part of the resist pattern 33 retreats from a bottom face side. Therefore, the portion protruding from the end of the upper layer 32 of the resist pattern 33 is removed.

Here, the ashing time is adjusted so that the recessed amount of the resist pattern is equal to the side etching amount of the lower layer 31. Here, the retraction amount of the resist pattern 33 is 0.5 µm. Thereby, the resist pattern 33 becomes thin by the thickness of 0.5 micrometer in the surface side. Therefore, when ashing is finished, the side end surface of the resist pattern 33 has retracted inward rather than the side end surface of the upper layer 32, as shown in FIG. That is, at the side end of the resist pattern 33, in addition to the collision of the radicals 36 on the upper surface side, there is a collision of the bounce radicals 35. Therefore, the retraction amount of the side end portion of the resist pattern 33 is larger than that of other portions. Here, the point which is widest among the side surfaces of the resist pattern 33 is set as the tip portion C of the side end surface of the resist pattern 33. That is, the location where the resist pattern 33 is widest is taken as the tip C of the side end surface.

As mentioned above, since ashing advances from the bottom face side, the front-end | tip part C of the side end surface of the resist pattern 33 is in the middle of a film thickness direction. Therefore, the side end D of the bottom face side of the resist pattern 33 has retracted inward from the front end part C of the side end face. In other words, from the bottom of the resist pattern 33 to the height of the tip portion C, the cross section of the resist pattern 33 becomes an inverse tapered shape. In this way, the cross section of the bottom surface side of the resist pattern 33 has an inverse tapered shape.

The side end D of the bottom face side of the resist pattern 33 is located inside the front end part C of the side end face. That is, a part of the bottom face side among the side cross sections of the resist pattern 33 has an inverse taper shape. At this time, the retraction amount of the resist pattern 33 may be a value different from the side etching amount of the lower layer 31. Here, it is preferable that the tip part C of the side surface of the resist pattern 33 retreats from the tip part B of the lid | cover of the upper layer 32. FIG. That is, it is preferable to adjust the ashing time so that the pattern width of the resist pattern 33 becomes narrower than the pattern width of the upper layer 32. Thus, by making the retreat amount of the resist pattern 33 larger than the side etching amount, the laminated structure 34 can be simply made into a desired shape.

Subsequently, a second etching is performed by the same plasma generating apparatus. Here, the upper layer 32 is etched through the recessed resist pattern 33. Thus, the cover portion of the upper layer 32 can be removed. And the upper layer 32 is etched according to the quantity with which the resist pattern 33 retreated. Specifically, SF ₆ / O ₂ = 1.01 × 10 ⁻¹ /6.76×10 ⁻² Pa · m ³ / sec (60/40 sccm), RF power 800W, and process pressure = 1.5 Pa. That is, the substrate 110 is exposed in the plasma generated by the mixed gas of SF ₆ and O ₂ . The etchant (reactive species contributing to etching) in the plasma is incident on the upper layer 32, so that the upper layer 32 is etched. Since SF ₆ is used, a typical etchant becomes a fluorine radical. In the second etching step, an isotropic etching mode is used in which no substrate bias power is applied. That is, etching is performed in a state where the bias voltage is not applied to the stage on which the substrate 110 is placed. As a result, the upper layer 32 is isotropically etched. In addition, since no bias power is applied, wear of the substrate can be suppressed and cloudiness of the substrate can be prevented. As a result, the transmittance of the substrate 110 is improved, and light utilization efficiency can be increased.

The etching time is set to 20 seconds corresponding to the just etching time of the upper layer 32 having a thickness of 100 nm. Since the isotropic etching mode is used, the incident direction of the etchant is random. In isotropic etching, the progress of etching is changed by the solid angle at which the etchant is allowed to enter. That is, the larger the solid angle of the region not blocked by the resist pattern 33, the higher the incident frequency of the etchant, and the faster the etching. When the position of the side end D on the bottom side of the resist pattern 33 and the position of the tip B of the upper layer 32 are compared, the solid angle Q _B at the point _B is D as shown in FIGS. 9 and 9B. It becomes larger than the solid angle Ω _{D at the} point. At this time, FIG. 9A is a view showing a solid angle Ω _B at which an etchant is allowed to enter at the position of the tip portion B of the upper layer 32. 9B is a view showing solid angle Ω _D at which an etchant is allowed to enter at the side end D on the bottom side of the resist pattern 33. That is, the solid angles Ω _B and Ω _D show solid angles in which etchants can be incident with respect to the positions. Therefore, the etching of the upper layer 32 proceeds faster toward the position of the tip portion B of the cross section of the upper layer 32 than the position of the side end D on the bottom surface side of the resist pattern 33. In addition, in the upper layer 32, the portion of the resist pattern 33 removed by ashing and exposed, the amount of etchant decreases toward the inside. That is, at the end of the upper layer 32, the etching rate is gradually reduced from the position of the front end B of the side end face of the upper layer 32 to the position of the front end D of the bottom of the resist pattern 33. Thus, by the 2nd etching process, the upper layer 32 which was an inverse taper shape can be processed into a forward taper shape.

When the resist pattern 33 is peeled off, the structure shown in Fig. 10 is obtained. As described above, the upper layer 32 is etched into a forward tapered shape. That is, the cover shape which existed at the front-end | tip part B of the upper layer 32 is removed. As a result, the pattern width gradually decreases as the upper layer 32 faces the upper surface layer from the bottom surface side.

In addition, in etching using a fluorine-based gas, A1 is not etched. In other words, by supplying a gas containing fluorine or a compound of fluorine and performing a second etching in the plasma generating apparatus, the lower layer 31 maintains the forward taper shape formed in the first etching. Accordingly, the upper layer 32 and the lower layer 31 both have a forward tapered shape. Moreover, the whole laminated structure 34 also becomes a forward taper shape. Thus, in the second etching step, etching with a gas containing fluorine or a compound of fluorine is preferable.

Thus, by processing the substrate 100 in the order of the first etching step, the ashing step, and the second etching step, the laminated structure 34 constituting the gate wiring 13 is processed into a forward tapered shape. Therefore, the disconnection of the source wiring 11 provided through the gate insulating film 14 above the gate wiring 13 can be prevented. In the cross-sectional shape described above, the covering property of the gate insulating film 14 can be improved. Therefore, disconnection of the source wiring 11 arranged to cross the gate wiring 13 can be prevented from above. In addition, the withstand voltage failure of the gate insulating film 14 generated by the electric field concentration can be reduced. By using such a substrate 110 as a wiring board of a display device, display quality can be improved.

In particular, when there are two wirings intersecting on the substrate, it is preferable to apply the above-described laminated structure 34 to the wiring below. Thereby, the disconnection of the upper wiring can be prevented. For example, in the case where the lower side is the source wiring and the upper side is the gate wiring, it is preferable to apply the above-described laminated structure 34 to the source wiring. Of course, the laminated structure 34 may be applied to the storage capacitor wiring.

In the above description, the etching time of the second etching step is a time corresponding to the just etching time, but the etching may be performed for a longer time than the just etching time. That is, the etching time may be further extended from the just etching state. In this case, the side etching of the upper layer 32 further advances from the state shown in FIG. Therefore, the structure after a 2nd etching process is shown in FIG. Then, the resist pattern 33 is peeled off to form the structure shown in FIG. In this case, the tip of the bottom face of the upper layer 32 comes inward from the tip of the top face of the lower layer 31. The side end on the bottom side of the upper layer 32 is a position away from the side end on the upper side of the lower layer 31. Therefore, the laminated structure becomes stepped. Also in this case, the laminated structure 34 becomes a forward taper shape. Therefore, it can process into a desired cross-sectional shape.

In addition, the same plasma generating apparatus can be used for an ashing process and a 2nd etching process. That is, two processes can be performed only by placing the board | substrate 110 after the 1st etching process of the substrate stage provided in the chamber of the same plasma generating apparatus, and switching supply gas. Therefore, ashing and a second etching can be performed continuously. Thereby, the fall of productivity can be reduced. Moreover, it can implement without adding an ashing apparatus and an etching apparatus newly. Therefore, installation cost can be reduced. For example, ashing and a second etching may be performed using an inductively coupled dry etcher. At this time, the plasma generating apparatus is not limited to the inductive coupling type, and the same process can be performed even if a parallel plate type (capacitive coupling type) is used. Of course, ashing and a second etching may be performed using a dry asher which can switch supply gas.

At this time, the material of the lower layer 31 is not limited to AiCu, Pure Al may be sufficient, Moreover, the alloy which has Al, such as AlNd as a main component, may be sufficient as it. The supply gas in the ashing step was oxygen, but nitrogen may be added.

By patterning a wiring by the above-mentioned process, it can process to desired cross-sectional shape, regardless of the additive or concentration of Mo of the upper layer 32. FIG. Therefore, the degree of freedom of material selection of wiring can be expanded. Therefore, a display device with high display quality can be easily manufactured. In addition, the upper layer 32 can use the alloy which added Nb to Mo. By using the material which added Nb to Mo, water resistance can be improved. For example, water resistance can be improved by using MoNb. Of course, other metal may be added to MoNb. By adding Nb, generation | occurrence | production of the defect in a washing | cleaning process etc. can be reduced, for example.

At this time, the laminated structure 34 may be applied to the wirings of the EL display device such as an organic EL display device or an inorganic EL display device, without being limited to the liquid crystal display device. In the EL display device, for example, a self-luminous material and a counter electrode are stacked on the pixel electrode 12 described above. When a current flows through the pixel electrode 12 and the counter electrode, the self-luminous material emits light according to the current. In the organic EL display device, the self-luminous material is made of an organic material, and in the inorganic EL display device, it is made of an inorganic material. In the case of the EL display device, the above-described laminated structure 34 may be applied to the power supply voltage wiring for supplying the power supply voltage. Moreover, you may apply to another display apparatus. In particular, the wiring board using the laminated structure 34 as the wiring is suitable for a flat panel display (flat panel display).

Furthermore, the present invention is not limited to the active matrix type but may be applied to the display device in the form of a passive matrix. That is, the above-described stacked structure 34 can be applied to the wiring of the array substrate in which the pixels are arranged in an array shape. In addition, the present invention can be applied not only to signal wiring in the display region 111 but also to wiring provided in the boundary region 112. For example, it is possible to apply to the above-mentioned gate wiring 13 or the routing wiring for supplying a signal from outside to the source wiring 11. In this case, it is possible to form simultaneously with the signal wiring in the display area 111.

According to the present invention, it is possible to provide a wiring board, a display device, and a manufacturing method thereof having wirings of a laminated structure formed in a desired cross-sectional shape.

Claims (9)

A manufacturing method of a wiring board having as a wiring a laminated structure composed of at least a first metal film and a second metal film, Forming a first metal film containing aluminum on the substrate; Forming a second metal film containing molybdenum on the first metal film; Forming a resist pattern on the second metal film; A first etching step of etching the first metal film and the second metal film via the resist pattern to side-etch the first metal film and the second metal film; An ashing step of retreating the resist pattern so as to expose the surface of the side end of the second metal film after the first etching step; And a second etching step of etching through the recessed resist pattern so that a cross section of the second metal film is in a forward taper shape after the ashing step. The method of claim 1, The said 1st metal film is processed to become a forward taper shape, and the said 2nd metal film becomes a reverse taper shape, The manufacturing method of the wiring board characterized by the above-mentioned. The method according to claim 1 or 2, In the ashing step, the amount of the resist pattern retreating is equal to or greater than the side etching amount of the first metal film in the first etching step. The method according to claim 1 or 2, In the ashing step, the resist pattern is retracted such that the side end on the bottom side of the resist pattern is inward even at the tip end of the side surface of the resist pattern. The method according to claim 1 or 2, The first metal film is an aluminum alloy, and the second metal film is an alloy obtained by adding niobium to molybdenum. The method according to claim 1 or 2, In the first etching step, wet etching is performed. In the ashing step, dry ashing is performed, In the second etching step, isotropic dry etching is performed. A method of manufacturing a display device comprising the step of manufacturing an array substrate by the method of manufacturing a wiring board according to claim 1. A wiring board having as a wiring a laminated structure composed of at least a first metal film and a second metal film, A first metal film comprising aluminum provided on the substrate, A second metal film including molybdenum provided on the first metal film, The second metal film has a forward tapered shape. A display device comprising the wiring board according to claim 8 as an array substrate.

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