KR20070095660A - Liquid crystal display and method of manufacturing thereof - Google Patents

Abstract

An LCD and a fabrication method thereof are provided to remove the height difference between a storage electrode line and a pixel electrode, thereby preventing the generation of texture of liquid crystal molecules when an electric field is formed at the LCD. A storage electrode line is formed on a substrate. A pixel electrode(191) at least partially overlaps the storage electrode line. A passivation layer(180) is formed between the storage electrode line and the pixel electrode. The passivation layer includes a first area overlapping the storage electrode line and a second area which does not overlap the storage electrode line. An upper surface of the first area is on the level identical to or lower than that of an upper surface of the second area. The passivation layer includes an organic insulating material.

Description

Liquid crystal display device and its manufacturing method {LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THEREOF}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a layout view of a thin film transistor array panel for the liquid crystal display of FIG. 3.

FIG. 5 is a layout view of a common electrode display panel for the liquid crystal display of FIG. 3.

6 and 7 are cross-sectional views of the liquid crystal display shown in FIG. 3 taken along the lines VI-VI and VIII-VIII, respectively.

8A and 8B are cross-sectional views showing the operation of liquid crystal molecules in the liquid crystal display device according to the prior art.

9A and 9B are cross-sectional views illustrating the operation of liquid crystal molecules in a liquid crystal display according to an exemplary embodiment of the present invention.

10A to 10G are cross-sectional views sequentially illustrating a process of manufacturing a liquid crystal display device according to an embodiment of the present invention.

11 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention.

12A and 12B are cross-sectional views illustrating the operation of liquid crystal molecules in a liquid crystal display according to another embodiment of the present invention.

13A and 13B are cross-sectional views each illustrating part of the process of manufacturing a liquid crystal display device according to another embodiment of the present invention.

<Description of Drawing>

11, 21: alignment film 12, 22: polarizer

71, 72a, 72b, 73a, 73b, 74a, 74b: common electrode incision

81, 82: contact auxiliary member

91, 92, 93a, 93b, 94a, 94b: pixel electrode cutout

110 and 210: insulated substrate 121: gate line

131: sustain electrode line 137: sustain electrode

154: semiconductor 161, 165: ohmic contact member

171: data line 175: drain electrode

180: protective film 181, 182, 185: contact hole

191: pixel electrode 220: light blocking member

230: color filter 250: overcoat

270: common electrode 300: liquid crystal panel assembly

400: gate driver 500: data driver

600: signal controller 800: gray voltage generator

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

The liquid crystal display is one of the flat panel display devices most widely used. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode.

The plurality of signal lines may be formed to overlap the pixel electrode. However, a step occurs at a portion where the signal line and the pixel electrode overlap. As a result, an electric field generated in the liquid crystal layer may be changed in the stepped portion, thereby causing a texture in which the alignment of the liquid crystal molecules is disturbed.

The technical problem to be achieved by the present invention is to prevent the generation of texture by eliminating the step between the sustain electrode line and the pixel electrode.

The liquid crystal display device of the present invention for solving the above technical problem is formed on a substrate, a storage electrode line formed on the substrate, a pixel electrode at least partially overlapping the storage electrode line, and between the storage electrode line and the pixel electrode. A protective film, wherein the protective film includes a first region overlapping the storage electrode line and a second region not overlapping the storage electrode line, and an upper surface of the first region is equal to or lower than an upper surface of the second region.

The passivation layer may include an organic insulator.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including forming a gate line and a storage electrode line on a substrate, stacking a gate insulating film on the substrate, forming a semiconductor layer on the gate insulating film, and forming the gate insulating film. Forming a data line and a drain electrode thereon; stacking an organic film on the data line; and an upper surface of the first region overlapping the storage electrode line of the organic film, wherein the top surface of the organic film does not overlap the storage electrode line of the organic film. And equal to or lower than an upper surface of the second region.

Removing the step may include partially exposing the organic layer.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes a thin film transistor array panel 100 and a common electrode panel 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the i-th (i = 1, 2, ..., n) gate line G _i and the j-th (j = 1, 2, ..., m) data line D _The pixel PX connected to _j ) includes a switching element Q connected to the signal lines G _i and D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. . Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element such as a thin film transistor provided in the thin film transistor array panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the thin film transistor array panel 100 and the common electrode 270 of the common electrode display panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270. Functions as a dielectric. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the entire surface of the common electrode display panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the thin film transistor array panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary role of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided in the thin film transistor array panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to this separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the common electrode display panel 200 corresponding to the pixel electrode 191 as an example of spatial division. . Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the thin film transistor array panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Next, an example of a liquid crystal panel assembly according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 7.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a layout view of a thin film transistor array panel for the liquid crystal display of FIG. 1, and FIG. 5 is a view of the common electrode display panel for the liquid crystal display of FIG. 1. 6 and 7 are cross-sectional views of the liquid crystal display of FIG. 1 taken along a line VI-VI and VIII-VIII.

3 to 7, a liquid crystal display according to an exemplary embodiment of the present invention includes a thin film transistor array panel 100 and a common electrode panel 200 facing each other and between the two display panels 100 and 200. The liquid crystal layer 3 is included.

First, the thin film transistor array panel 100 will be described with reference to FIGS. 1, 2, 6, and 7.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding upwards and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage and almost extends in parallel with the gate line 121. Each storage electrode line 131 is positioned between two adjacent gate lines 121 and is substantially equal to the two gate lines 121. The storage electrode line 131 includes a storage electrode 137 extending up and down. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, or molybdenum ( It may be made of molybdenum-based metals such as Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta) and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop. In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Good examples of such a combination include a chromium bottom film, an aluminum (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to 80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

On the gate insulating layer 140, a plurality of island semiconductors 154 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated as a-Si), polycrystalline silicon, or the like are formed. The semiconductor 154 is positioned on the gate electrode 124 and includes an extension covering the boundary of the gate line 121. A plurality of island type ohmic contacts 163 and 165 are formed on the semiconductor 154. The ohmic contacts 163 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus are heavily doped, or may be made of silicide. The ohmic contacts 163 and 165 are paired and disposed on the semiconductor 154.

Side surfaces of the semiconductor 154 and the ohmic contacts 163 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 163 and 165 and the gate insulating layer 140.

The data line 171 transmits a data voltage and mainly extends in the vertical direction to cross the gate line 121 and the storage electrode line 131. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and a wide end portion 179 for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data voltage is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 has one wide end portion 177 and the other end having a rod shape. The wide end portion 177 overlaps the sustain electrode 137 and the rod-shaped end portion is partially surrounded by the U-shaped bent source electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 are preferably made of a refractory metal such as molybdenum, chromium, tantalum, and titanium, or an alloy thereof, and include a refractory metal film (not shown) and a low resistance conductive film. It may have a multilayer structure including (not shown). Examples of the multilayer structure include a double layer of chromium or molybdenum (alloy) lower layer and an aluminum (alloy) upper layer, and a triple layer of molybdenum (alloy) lower layer and aluminum (alloy) interlayer and molybdenum (alloy) upper layer. However, the data line 171 and the drain electrode 175 may be made of various other metals or conductors.

It is preferable that the side surfaces of the data line 171 and the drain electrode 175 are inclined at an inclination angle of about 30 to 80 degrees with respect to the surface of the substrate 110.

The ohmic contacts 163 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, thereby lowering the contact resistance. An extension of the semiconductor 154 positioned on the gate line 121 may soften the profile of the surface to prevent the data line 171 from being disconnected. The semiconductor 154 includes portions exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 151. The passivation layer 180 may be made of an inorganic insulator or an organic insulator, and may have a flat surface. Examples of the inorganic insulator include silicon nitride and silicon oxide. The organic insulator may have photosensitivity and the dielectric constant is preferably about 4.0 or less. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

The upper surface of the passivation layer 180 is flat over the entire display panel 300. In particular, even in a portion where the storage electrode line including the storage electrode 137 is formed, the upper surface of the passivation layer 180 is formed flat without a step.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. A plurality of contact holes 181 exposing the end portion 129 of the gate line 121 are formed at 140.

A plurality of pixel electrodes 191 and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum or silver alloy.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied is generated between the two electrodes 191 and 270 by generating an electric field together with the common electrode 270 of the other display panel 200 to which the common voltage is applied. The direction of the liquid crystal molecules 30 of the liquid crystal layer 3 is determined. The polarization of light passing through the liquid crystal layer 3 varies according to the direction of the liquid crystal molecules 30 determined as described above. The pixel electrode 191 and the common electrode 270 form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrode 137. A capacitor formed by the pixel electrode 191 and the drain electrode 175 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

Each pixel electrode 191 has a substantially rectangular shape in which four corners are chamfered, and the chamfered hypotenuse forms an angle of about 45 ° with respect to the gate line 121.

First and second central cutouts 91 and 92, lower cutouts 93a and 94a, and upper cutouts 93b and 94b are formed in the pixel electrode 191, and the pixel electrode 191 includes these cutouts. The parts 91 to 94b are divided into a plurality of partitions. The cutouts 91 to 94b have almost inverted symmetry with respect to the sustain electrode line 131.

The lower and upper cutouts 93a to 94b extend obliquely from the right side of the pixel electrode 191 to the left side, the upper side, or the lower side. The lower and upper cutouts 93a to 94b are positioned at the lower half and the upper half with respect to the storage electrode line 131, respectively. The lower and upper cutouts 93a to 94b extend perpendicular to each other at an angle of about 45 ° with respect to the gate line 121.

The first central cutout 91 extends along the storage electrode line 131 and has an inlet at the left side. The inlet of the first central cutout 91 has a pair of hypotenuses that are substantially parallel to the lower cutouts 93a and 94a and the upper cutouts 93b and 94b, respectively. The second central cutout 92 includes a central horizontal section and a pair of diagonal lines. The second central horizontal portion extends from the right side of the pixel electrode 191 to the left along the storage electrode line 131, and the pair of diagonal portions respectively extend toward the left side of the pixel electrode 191 at the end of the central horizontal portion. It extends almost parallel to the upper incisions 93a-94b.

Therefore, the lower half of the pixel electrode 191 is divided into four regions by the second central cutout 92 and the lower cutouts 93a and 9a, and the upper half also includes the second central cutout 92 and The upper cutouts 93b and 94b are divided into four regions. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side to the vertical side of the pixel electrode, and the type or characteristics of the liquid crystal layer 3.

The present invention is not limited to the shape of the pixel electrode 191 described above, and may be applied in various forms in which the storage electrode line 131 and the pixel electrode 191 overlap each other.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

Next, the common electrode display panel 200 will be described with reference to FIGS. 3, 5, 6, and 7.

A light blocking member 220 is formed on an insulating substrate 210 made of transparent glass, plastic, or the like. The light blocking member 220 is also called a black matrix and prevents light leakage. The light blocking member 220 includes a linear portion 221 corresponding to the data line 171 and a planar portion 222 corresponding to the thin film transistor, and prevents light leakage between the pixel electrodes 191 and prevents the pixel electrode 191. Define the facing opening area. However, the light blocking member 220 may have a plurality of openings (not shown) facing the pixel electrode 191 and having substantially the same shape as the pixel electrode 191.

A plurality of color filters 230 is also formed on the substrate 210. The color filter 230 is mostly present in an area surrounded by the light blocking member 230, and may extend in the vertical direction along the column of the pixel electrodes 191. Each color filter 230 may display one of primary colors such as three primary colors of red, green, and blue.

An overcoat 250 is formed on the color filter 230 and the light blocking member 220. The overcoat 250 may be made of an (organic) insulator, which prevents the color filter 230 from being exposed and provides a flat surface. The overcoat 250 may be omitted.

The common electrode 270 is formed on the overcoat 250. The common electrode 270 is made of a transparent conductor such as ITO or IZO.

The plurality of cutouts 71, 72a, 72b, 73a, 73b, 74a, and 74b are formed in the common electrode 270.

One set of cutouts 71 to 74b faces the pixel electrode 191 and forms the central cutout 71, the lower cutouts 72a, 73a, and 74a and the upper cutouts 72b, 73b, and 74b. Include. Each of the cutouts 71 to 74b is disposed between adjacent cutouts 91 to 94b of the pixel electrode 191 or between the cutouts 91 to 94b and the chamfered hypotenuse of the pixel electrode 191. In addition, each cutout 71 to 74b includes at least one diagonal branch extending in parallel with the lower cutouts 93a and 94a or the upper cutouts 93b and 94b of the pixel electrode 191.

Each of the lower and upper cutouts 72a to 74b includes diagonal branches, horizontal branches and vertical branches. The oblique branches extend substantially parallel to the lower or upper cutouts 93a to 94b of the pixel electrode 191 from the right side of the pixel electrode 191 to the left, upper or lower side thereof. The horizontal and vertical branches extend from each end of the diagonal branch along the sides of the pixel electrode 191 and form an obtuse angle with the diagonal branch.

The central cutout 71 includes a central transverse branch, a pair of oblique branches and a pair of longitudinal longitudinal branches. The central horizontal branches extend from the right side of the pixel electrode 191 to the left along the horizontal center line of the pixel electrode 191, and the pair of diagonal lines extend from the end of the central horizontal branch toward the left side of the pixel electrode 191, respectively. It extends almost parallel to the lower and upper incisions 72a and 72b. The vertical longitudinal branches extend along the left side of the pixel electrode 191 from each end of the diagonal branches and form an obtuse angle with the diagonal branches.

The branches of the central incision 71 meet each other to form an intersection. The intersection is located inside the pixel electrode 191 and is wider than the branch. The incision 71 further includes a protrusion 32 towering at the center of this intersection. As shown in FIG. 4, the protruding portion 32 rises higher than the branch and almost contacts the upper panel 200.

The number and direction of the cutouts 71 to 74b may also vary depending on design elements.

Alignment layers 11 and 21 are coated on inner surfaces of the display panels 100 and 200.

Polarizers 12 and 22 are provided on the outer surfaces of the display panels 100 and 200, and the transmission axes of the two polarizers 12 and 22 are perpendicular to each other, and one of the transmission axes is parallel to the gate line 121. desirable. In the case of a reflective liquid crystal display, one of the two polarizers 12 and 22 may be omitted.

The liquid crystal display may include a polarizer 12 and 22, display panels 100 and 200, and a backlight unit (not shown) that supplies light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 30 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels 100 and 200 in the absence of an electric field. . Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the pixel electrode 191, an electric field (electric field) substantially perpendicular to the surfaces of the display panels 100 and 200 is generated. The liquid crystal molecules 30 change their direction in response to the electric field such that their major axis is perpendicular to the direction of the electric field. From now on, the pixel electrode 191 and the common electrode 271 will be referred to as an electric field generating electrode.

On the other hand, the incisions 91 to 94b of the pixel electrodes of the field generating electrodes 191 and 270 and the incisions 71 to 74b of the common electrode and the hypotenuse of the pixel electrode 191 parallel to them distort the electric field to form a liquid crystal. Create horizontal components that determine the direction of the molecules' oblique directions. The horizontal component of the electric field is perpendicular to the hypotenuse of the cutouts 91 to 94b and 71 to 74b and the hypotenuse of the pixel electrode 191.

Referring to FIG. 1, one common electrode cutout set 71 to 74b and pixel electrode cutout set 91 to 94b divide the pixel electrode 191 into a plurality of sub-areas. The region has two major edges that form an oblique angle with the peripheral side of the pixel electrode 191. Most of the liquid crystal molecules on each subregion are inclined in a direction perpendicular to the periphery thereof, and thus, the inclination directions are approximately four directions. As described above, when the liquid crystal molecules are inclined in various directions, the reference viewing angle of the liquid crystal display increases.

The common electrode cutout sets 71 to 74b and the pixel electrode cutout sets 91 to 94b may be replaced with protrusions (not shown) or depressions (not shown).

The shapes and arrangements of the common electrode cutout sets 71 to 74b and the pixel electrode cutout sets 91 to 94b may be modified.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 400, 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or may be a flexible printed circuit film (not shown). It may be mounted on the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 400, 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m and the thin film transistor switching element Q. It may be. In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display device will be described in detail with reference to FIGS. 1 and 2.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 applies the input image signals R, G, and B to the operating conditions of the liquid crystal panel assembly 300 and the data driver 500 based on the input image signals R, G, and B and the input control signal. After appropriately processing and generating the gate control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are processed. ) Is output to the data driver 500. The output video signal DAT has a predetermined number (or gradation) as a digital signal.

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH indicating the start of image data transmission for one row of pixels, a load signal LOAD and a data clock signal for applying a data signal to the liquid crystal panel assembly 300. HCLK). The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for one row of pixels, and the gray scale voltage corresponding to each digital image signal DAT. By converting the digital video signal DAT into an analog data signal, it is applied to the corresponding data line.

The gate driver 400 applies a gate-on voltage Von to the gate line according to the gate control signal CONT1 from the signal controller 600 to turn on the switching element connected to the gate line. Then, the data signal applied to the data line is applied to the corresponding pixel through the turned-on switching element.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, the motion of the liquid crystal molecules of the liquid crystal display according to the present invention will be described with reference to FIGS. 8A to 9B.

8A and 8B are cross-sectional views illustrating the operation of the liquid crystal molecules 30 when the liquid crystal display according to the prior art is driven with positive (+) and negative (-) driving, respectively. It is a cross-sectional view showing how the liquid crystal molecules 30 operate when driving the positive (+) and the negative (-) driving the liquid crystal display according to the present invention.

8A and 8B, the common electrode 270 has a constant voltage, for example, a voltage of 6.5V. The voltage of the pixel electrode 191 of FIG. 8A is lower than the voltage of the common electrode 270, for example, 0V, and the voltage of the pixel electrode 191 of FIG. 8B is higher than the voltage of the common electrode 270, for example, 13V. to be. Accordingly, the voltage of the pixel electrode 191 of FIG. 8A is lower than that of the common electrode 270 and is negative, and the voltage of the pixel electrode 191 of FIG. 8B is lower than the voltage of the common electrode 270. Meanwhile, a step is formed on the upper surface of the passivation layer 180 in the portion SA in which the storage electrode 137 is formed under the passivation layer 180. That is, the upper surface of the protective film 180 is convex toward the liquid crystal layer 3. A step is formed in the pixel electrode 191 due to the step of the passivation layer 180.

Looking at the movement of the liquid crystal molecules 30 according to the electric field formation, the liquid crystal molecules 30 in a circle indicated by dotted lines between the cutout 90 of the pixel electrode 191 and the cutout 70 of the common electrode 270. ) Loses horizontal orientation to the substrate and distorted texture occurs. This occurs both when the pixel electrode 191 is negative (-) as shown in FIG. 8A and when the pixel electrode 191 is positive (+) as shown in FIG. 8B.

In contrast, in the liquid crystal display of FIGS. 9A and 9B, a step is not formed on the upper surface of the passivation layer 180 at the portion SA in which the sustain electrode 137 is formed under the passivation layer 180. That is, the upper surface of the passivation layer 180 is flat, and thus the pixel electrode 191 is also flat. 9A and 9B, the common electrode 270 has a constant voltage, for example, a voltage of 6.5 V, and the voltage of the pixel electrode 191 of FIG. 9A is lower than the voltage of the common electrode 270, for example. For example, the voltage of the pixel electrode 191 of FIG. 9B is higher than the voltage of the common electrode 270, for example, 13V. Accordingly, the voltage of the pixel electrode 191 of FIG. 9A is lower than that of the common electrode 270 and is negative, and the voltage of the pixel electrode 191 of FIG. 9B is lower than the voltage of the common electrode 270.

Referring to the movement of the liquid crystal molecules 30 of FIGS. 9A and 9B, the liquid crystal molecules in a circle indicated by a dotted line between the cutout 90 of the pixel electrode 191 and the cutout 70 of the common electrode 270 ( 30 maintains directionality horizontal to the substrate. Therefore, the representation of the image can be made smooth.

A method of manufacturing the liquid crystal display according to the present exemplary embodiment will now be described in detail with reference to FIGS. 10A to 10F and FIGS. 3 to 7.

10A to 10F are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array panel illustrated in FIGS. 3, 4, 6, and 7.

First, referring to FIG. 10A, a plurality of gate lines 121 including a gate electrode 124 and an end portion 129 may be sequentially stacked on a substrate 110 by sputtering and photo etching. A plurality of sustain electrode lines 131 including the sustain electrodes 137 are formed.

Next, as shown in FIG. 10B, the gate insulating layer 140 is stacked, an intrinsic amorphous silicon layer and an impurity amorphous silicon layer are sequentially stacked, and the two layers are patterned to form a plurality of islands. The impurity semiconductor 160 and the island semiconductor 150 are formed.

Referring to the following 10c, a metal film is deposited by sputtering, and then photoetched to form a plurality of data lines 171 and a plurality of drain electrodes 175 including a source electrode 173 and an end portion 179. .

Subsequently, the island-type resistive contact members 163 and 165 are completed by removing portions of the impurity semiconductor 164 that are not covered by the data line 171 and the drain electrode 175, while the intrinsic semiconductor 154 thereunder. Expose the part. It is preferable to carry out oxygen plasma in order to stabilize the surface of the exposed intrinsic semiconductor portion.

Thereafter, as shown in FIG. 10D, the photosensitive organic insulator is coated by chemical vapor deposition to form the passivation layer 180.

Thereafter, as shown in FIG. 10E, the passivation layer 180 is partially exposed and developed through the mask 30. The transmittance of light passing through the mask 30 is greatest in the first portion 31 and weaker in the rest. Therefore, in the first portion 31, all of the passivation layers 180 are etched to form contact holes 185. In the portion where the storage electrode 137 is formed and the portion where the gate electrode 124 and the semiconductor layer 153 are formed, a step is formed in the passivation layer 180. In this portion, light passing through the mask 30 is formed. Since the protective layer 180 is exposed twice by being reflected from the sustain electrode 137 or the gate electrode 124, the etching amount is larger than that of other portions. Therefore, the step of the passivation layer 180 may be removed from the portion where the sustain electrode 137 is formed and the portion where the gate electrode 124 and the semiconductor layer 153 are formed. As a result, the entire surface of the passivation layer 180 is flat except for a portion where the contact hole 185 is formed. To this end, the mask 30 may employ various techniques such as using a mask having slits at different intervals depending on the position, a mask having different transmittances, or a double mask through which different exposure energy is transmitted.

Next, as shown in FIG. 10F, an ITO or IZO film is stacked and photo-etched to form a plurality of pixel electrodes 191 and a plurality of contact auxiliary members 81 and 82, align a mask (not shown), and then expose And develop to form cutouts 92, 94a and 94b. Next, the alignment film 11 is formed.

A liquid crystal display according to another exemplary embodiment of the present invention will now be described with reference to FIG. 11.

11 is a cross-sectional view of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 11, the liquid crystal panel assembly according to the present exemplary embodiment includes a lower panel 100, an upper panel 200, and a liquid crystal layer 3 therebetween.

The layered structure of the liquid crystal panel assembly according to the present embodiment is usually the same as the layered structure of the liquid crystal panel assembly shown in Figs.

Referring to the lower panel, a gate conductor including a gate line (not shown) and a storage electrode line (not shown) is formed on the insulating substrate 110. The gate line includes a gate electrode 124 and an end portion (not shown), respectively, and the storage electrode line includes the storage electrode 137. The gate insulating layer 140 is formed on the gate conductor. A plurality of semiconductors 154 are formed on the gate insulating layer 140, and a plurality of ohmic contacts 163 and 165 are formed thereon. A data conductor including a plurality of data lines (not shown) and a drain electrode 175 is formed on the ohmic contacts 163 and 165. The data line includes a source electrode 173 and an end portion (not shown), and the drain electrode 175 includes a wide end portion 177. A passivation layer 180 is formed on the data conductor and the exposed semiconductor 154, and a plurality of contact holes 185 are formed in the passivation layer 180 and the gate insulating layer 140. The pixel electrode 191 and a plurality of contact auxiliary members (not shown) are formed on the passivation layer 180. An alignment layer 11 is formed on the pixel electrode 191, the contact assistant member, and the passivation layer 180.

Referring to the upper panel, the common electrode 270 having the light blocking member 220, the plurality of color filters 230, the overcoat 250, and the cutouts 71, 72a, 73a, and 74a on the insulating substrate 210. ) And an alignment film 21 are formed.

However, in the liquid crystal display according to the present exemplary embodiment, unlike the liquid crystal display illustrated in FIGS. 3 to 7, the recess 180a is formed in the passivation layer 180 at the portion where the sustain electrode 137 is formed. Accordingly, the pixel electrode 191 on the passivation layer 180 is also recessed along the recess 180a.

Next, movements of liquid crystal molecules of the liquid crystal display according to the present exemplary embodiment will be described with reference to FIGS. 12A and 12B and FIGS. 8A and 8B.

12A and 12B are cross-sectional views illustrating the operation of liquid crystal molecules when driving a positive (+) and a negative (-) drive of the liquid crystal display according to the present embodiment.

12A and 12B, the common electrode 270 has a constant voltage, for example, a voltage of 6.5V. The voltage of the pixel electrode 191 of FIG. 12A is lower than the voltage of the common electrode 270, for example, 0V, and the voltage of the pixel electrode 191 of FIG. 12B is higher than the voltage of the common electrode 270, for example, 13V. to be. Accordingly, the voltage of the pixel electrode 191 of FIG. 12A is lower than that of the common electrode 270 and is negative, and the voltage of the pixel electrode 191 of FIG. 12B is lower than the voltage of the common electrode 270. Meanwhile, the recess 180a is formed on the upper surface of the passivation layer 180 at the portion SA in which the storage electrode 137 is formed under the passivation layer 180. The pixel electrode 191 is also recessed along the recess 180a of the passivation layer 180.

Looking at the movement of the liquid crystal molecules of FIGS. 12A and 12B, unlike the above-described FIGS. 8A and 8B, a dotted line is formed between the cutout 90 of the pixel electrode 191 and the cutout 70 of the common electrode 270. The liquid crystal molecules 30 in the circle shown keep the orientation horizontal to the substrate. Therefore, there is no disturbance in the operation of the liquid crystal molecules 30 in the entire liquid crystal layer 3 except near the cutouts 70 and 90, so that an image can be smoothly represented.

Next, a method of manufacturing the liquid crystal display according to the present exemplary embodiment will be described with reference to FIGS. 13A and 13B.

13A and 13B are cross-sectional views illustrating a step of manufacturing the thin film transistor array panel of the liquid crystal display shown in FIG. 11.

First, the same as in FIGS. 10A to 10D described above. That is, the gate line 121, the storage electrode line 131, the gate insulating layer 140, the semiconductor 154, the ohmic contacts 163 and 165, the data line 171, and the drain electrode 175 are disposed on the substrate 110. And a photosensitive organic insulator are applied to form the passivation layer 180.

Thereafter, as shown in FIG. 12A, the passivation layer 180 is partially exposed and developed through the mask 40. The transmittance of light passing through the mask 30 is greatest in the first portion 41, and is reduced in the order of the second portion 42 and the third portion 43. Accordingly, in the first portion 41, all of the passivation layers 180 are etched to form contact holes 185. In the second portion 42 corresponding to the portion where the storage electrode 137 is formed, only a portion of the passivation layer 180 may be removed to form the recessed portion 180a. For this purpose, the mask 40 may employ various techniques such as using a mask having slits at different intervals depending on the position, a mask having different transmittances, or a double mask through which different exposure energy is transmitted.

Subsequently, as described above with reference to FIGS. 10F and 10G, the ITO or IZO film is stacked and photo-etched to form a plurality of pixel electrodes 191 and a plurality of contact auxiliary members 81 and 82, and a mask (not shown). ), And then exposed and developed to form cutouts 92, 94a, 94b. Next, the alignment film 11 is formed.

According to the present invention, it is possible to prevent the texture of the liquid crystal molecules from occurring when an electric field is formed in the liquid crystal display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (4)

Board, A storage electrode line formed on the substrate, A pixel electrode at least partially overlapping the sustain electrode line, and A protective film formed between the sustain electrode line and the pixel electrode. Including, The passivation layer includes a first region overlapping the storage electrode line and a second region not overlapping the storage electrode line, The upper surface of the first region is the same as or lower than the upper surface of the second region. Liquid crystal display. In claim 1, The protective film includes an organic insulator. Forming a gate line and a storage electrode line on the substrate, Stacking a gate insulating film on the substrate; Forming a semiconductor layer on the gate insulating film, Forming a data line and a drain electrode on the gate insulating layer; Stacking an organic film on the data line, and Making an upper surface of the first region overlapping the storage electrode line in the organic film equal to or lower than an upper surface of the second region in the organic film not overlapping the storage electrode line. Method of manufacturing a liquid crystal display comprising a. In claim 3, The removing the step may include partially exposing the organic layer.

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