KR20070091470A - Method of manufacturing a memory device - Google Patents

Abstract

A gas distribution plate for uniform injection of gas is provided to improve a process nonuniformity phenomenon where the center part of a substrate becomes thicker than the peripheral part of the substrate, by increasing the fluid conductance in the peripheral part of a gas distribution plate as compared with the center part of the gas distribution plate. A predetermined reaction space is formed in a chamber, and a plurality of injection holes for injecting gas over a substrate placement table are formed in a gas distribution plate(100). A first region is formed in the center of the gas distribution plate. A second region is formed outside the first region. The fluid conductance in the first region is lower than that in the second region. The density of the injection hole in the first region can be lower than that in the second region.

Description

Method of manufacturing a memory device

1 to 3 are cross-sectional views illustrating a method of manufacturing a memory device according to Embodiment 1 of the present invention.

4 to 6 are cross-sectional views illustrating a method of manufacturing a memory device according to a second exemplary embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

100,200: single crystal silicon substrate 102,202: gate oxide film

104,204: gate spacer 106,206: gate electrode

110,210 Source / drain region 120: Opening

122,222 Interlayer insulating film pattern 124,250 Cleaning liquid

130 and 230: first silicon film pattern 240: photoresist pattern

242: second opening 244: insulating film pattern

260: second silicon film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a memory device, and more particularly, to a method of manufacturing a memory device in which a silicon film is formed by selective epitaxial growth inside an opening exposing a substrate of an interlayer insulating film pattern.

In general, depending on the crystal structure, materials can be classified into single crystal, poly crystal, and amorphous. The single crystal material has a single crystal structure, the polycrystalline material has a plurality of crystal structures, and the amorphous material has an irregular atomic arrangement instead of a crystal.

The polycrystalline material has many grain boundaries because it consists of a plurality of crystal structures. Therefore, the polycrystalline material does not expect excellent electrical properties because the movement and control of carriers such as free electrons or holes are disturbed by the grain boundaries. However, since the single crystal material is composed of one crystal structure, it has almost no grain boundaries. Therefore, the single crystal material can expect excellent electrical properties compared to the polycrystalline material because the movement and control of the carrier is relatively less disturbed.

Therefore, a memory device in which semiconductor unit devices such as MOS transistors are stacked on a substrate uses a structure made of the single crystal material as a contact structure. In particular, it is most preferable to form a single crystal silicon film as a contact structure of the multilayer transistor in the memory device.

The single crystal silicon film forms an opening exposing the single crystal silicon substrate in a region to be provided as a contact between the source / drain region and the gate electrode of the substrate, and then fills the inside of the opening to selectively epitaxial growth. SEG, hereinafter referred to as 'SEG'), may be obtained by a damascene method of performing a process. Here, the single crystal silicon film is an epitaxial silicon film pattern close to the crystal structure of the single crystal.

However, in order to form the epitaxial silicon film pattern by the SEG method, it is necessary to design a dummy pattern according to the pattern dependence of thin film growth rate and thickness uniformity, and have to undergo an appropriate pre-cleaning process before growing the silicon by the SEG In addition, it is necessary to overcome the problem of deterioration of the characteristics of the short channel transistor according to the epitaxial silicon growth temperature. In addition, in the opening forming process, when the damaged film or the etching residue remains on the gate electrode and the source / drain region which are the contact regions by anisotropic etching, a bad contact is caused. When the crystallinity of the silicon film formed by the bad contact is lowered, the contact resistance is increased, which causes a problem that the transistor operating current is reduced.

Meanwhile, a single crystal silicon film is also used as a channel layer of the memory device in which semiconductor unit devices are stacked. In the pattern of the single crystal silicon film, an interlayer insulating film is formed on a substrate, an amorphous silicon film is formed on a seed film made of epitaxial silicon close to the single crystal silicon, and then heat-treated to form the crystal structure of the amorphous silicon film as a single crystal. It can be obtained by a solid phase epitaxy (SPE, hereinafter referred to as "SPE") method of switching.

However, even in the above-described solid-state epitaxy method, the epitaxial silicon film pattern is formed by chemical mechanical polishing (CMP, hereinafter referred to as 'CMP') for forming and planarizing a seed film made of the epitaxial silicon. An etching residue is formed on the substrate, which causes deterioration of the crystalline characteristics of the single crystal silicon film.

Therefore, before the epitaxial silicon film pattern, which is a contact structure, and the single crystal silicon film used as the channel layer, a dry cleaning process is performed in order to form a complete ohmic contact, but it is damaged by the dry cleaning process. A film is formed or previous etching residues remain. That is, in the fabrication of the memory device subjected to the dry cleaning process, there is still a problem that the epitaxial silicon film pattern due to the SEG growth and the crystalline characteristics of the single crystal silicon film by the SPE method are deteriorated.

Accordingly, an object of the present invention for solving the above problems is to provide a method of manufacturing a memory device comprising the step of curing the surface of the exposed silicon film using a cleaning solution containing hydrofluoric acid and ozone water.

A method of manufacturing a memory device according to an embodiment of the present invention for achieving the object of the present invention to form transistors including a source / drain region and a gate electrode on a single crystal silicon substrate. An interlayer insulating film filling the transistors is formed. The interlayer insulating layer is etched to form an interlayer insulating layer pattern including an opening through which the silicon substrate exposes a surface. The surface of the substrate exposed by the opening is cleaned by using a cleaning liquid containing ozone water (O ₃ ) and hydrofluoric acid (HF) to cure the surface of the substrate. Silicon is grown from the cured substrate to form a silicon film pattern in which the opening is completely embedded.

The interlayer insulating layer may include at least one material selected from the group consisting of BOSG (Boro Phospho Silicate Glass), PSG (Phospho Silicate Glass), TEOS (Tetra Ethyl Ortho Silicate), and HDP (High Density Plasma) oxide film. It is preferable.

The curing process forms an oxide film by oxidizing the surface of the silicon substrate with ozone water contained in the cleaning liquid, and forms a substrate having a substantially uniform surface by removing the oxide film with hydrofluoric acid included in the cleaning liquid. It is desirable to.

At this time, the ozone water used in the cleaning liquid has an ozone concentration of 10 to 20 ppm, the hydrofluoric acid is preferably hydrofluoric acid diluted in deionized water having a concentration of 0.05 to 0.1%.

A method of manufacturing a memory device according to another embodiment of the present invention for achieving the object of the present invention to form transistors including a source / drain region and a gate electrode on a single crystal silicon substrate. An interlayer insulating film filling the transistors is formed. The interlayer insulating layer is etched to form an interlayer insulating layer pattern including an opening exposing a surface of the silicon substrate. An optional epitaxial process is performed on the substrate exposed to the opening to form a first silicon film covering the interlayer insulating layer pattern while filling the opening. The first silicon layer is chemically mechanically polished to expose the surface of the interlayer insulating layer pattern to form a first silicon layer pattern. The upper surface of the first silicon film pattern is cleaned using a cleaning solution containing ozone water (O ₃ ) and hydrofluoric acid (HF). A second silicon film used as a channel layer is formed on the interlayer insulating film pattern and the first silicon film pattern.

In this case, the second silicon film is preferably formed by a solid state epitaxy method.

According to the present invention, the surface of the substrate exposed by the opening can be cleaned with a cleaning solution containing ozone water (O ₃ ) and hydrofluoric acid (HF) to cure excessive etching of the surface of the substrate when the opening is formed. Accordingly, the crystallinity of the silicon film pattern formed by SEG growth from the substrate may be improved.

In addition, according to the present invention, the cleaning liquid comprises ozone water (O ₃ ) and hydrofluoric acid (HF) on the surfaces of the first silicon film pattern and the interlayer insulating film pattern CMP of the first silicon film pattern exposed through the second opening. When the CMP and the second opening are formed, excessive etching of surfaces of the first silicon layer pattern and the interlayer insulating layer pattern may be cured. As a result, in the second silicon film formed by the SPE method inside the second opening, the crystal surface having the (100) alignment crystal structure is increased. Accordingly, when the memory device including the first silicon layer pattern and the second silicon layer having improved crystallinity is manufactured, an improvement in operating speed may be expected.

Hereinafter, a method of manufacturing a memory device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, patterns or structures are shown in greater detail than actual for clarity of the invention. In the present invention, when referred to as being formed "on", "upper" or "under", "lower" of the object, it may be formed while directly contacting the upper or lower surface of the object, It may be formed on the upper or lower portion of the object in addition to the other structures formed on the object.

Example 1

1 to 3 are cross-sectional views illustrating a method of manufacturing a memory device according to Embodiment 1 of the present invention.

Referring to FIG. 1, a substrate 100 having an upper surface of single crystal silicon is prepared. The substrate 100 may be a silicon substrate, a silicon-on-insulator substrate, or the like. The gate oxide film 102 is formed on the substrate 100 by thermal oxidation. Subsequently, after the transistors including the gate spacer 104 and the gate electrode 106 are formed on the single crystal silicon substrate 100, the source / drain regions as contact regions are applied by applying the gate electrode 106 as an ion implantation mask. Form 110.

Thereafter, an interlayer insulating layer (not shown) filling the transistors is formed on the substrate 100 on which the gate electrode 106 and the gate spacer 104 are formed. The interlayer insulating film may be formed by depositing silicon oxide by Chemical Vapor Deposition (CVD).

Specifically, the interlayer insulating layer may be formed of low pressure chemical vapor deposition (Low Pressure CVD) or plasma by using a BOSG (Boro Phospho Silicate Glass), PSG (Phospho Silicate Glass), TEOS (Tetra Ethyl Ortho Silicate), HDP (High Density Plasma) oxide film, or the like. It may be formed by depositing using an enhanced chemical vapor deposition (Plasma Enhanced CVD). Here, the interlayer insulating film is preferably formed to fully bury the gate electrode 106 formed on the single crystal silicon substrate 100. Further, after forming the interlayer insulating film, it is more preferable to perform a process of planarizing an upper surface of the interlayer insulating film.

Subsequently, a photoresist pattern (not shown) having a predetermined shape for patterning the interlayer insulating film is formed to expose the surface of the single crystal silicon substrate 100. Subsequently, the interlayer insulating layer is etched using the photoresist pattern as an etching mask to form an interlayer insulating layer pattern 122 including an opening 120 to selectively expose the surface of the single crystal silicon substrate 100. The opening 120 exposes a source / drain region 110 connected to both sides of the structure including the gate electrode 106 and the gate spacer 104. At this time, the surface of the single crystal silicon substrate 100 is damaged by an overetch process during the etching process for forming the opening 120. As a result, the surface of the substrate 100 exposed by the opening 120 has a damaged and rough surface.

Referring to FIG. 2, the substrate 100 may be cleaned by using a cleaning liquid 124 including ozone water (O ₃ ) and hydrofluoric acid (HF) on the surface of the substrate 100 exposed by the opening 120. ) Curing the surface.

The cleaning process is performed to complete the formation of the opening 120 by anisotropic etching, and to form an ohmic contact between the conductive material and the single crystal silicon substrate 100 that are applied in a subsequent process, and are damaged by excessive etching. The surface of the single crystal silicon substrate 100 exposed by the opening 120 having a cured surface is cured. In addition, it also serves to remove etching residues such as organic substances and particles, which are pollutants existing on the single crystal silicon substrate 100, and native oxide formed on the substrate 100.

Specifically, the cleaning process uses a mixed solution containing ozone water (O ₃ ) and hydrofluoric acid (HF) as the cleaning liquid 124, the ozone water (O ₃ ) has an ozone concentration of 10 to 20 ppm, Hydrofluoric acid (HF) is preferably hydrofluoric acid diluted in deionized water having a concentration of 0.05 to 0.1%. At this time, the ozone concentration of the ozone water (O ₃ ) can be adjusted while injecting ozone gas into the dilute hydrofluoric acid (HF) as described above.

The ozone (O ₃ ) in the cleaning liquid 124 is a material having an excellent ability to remove contaminants on the surface of the substrate, has an excellent ability to remove organic substances and metal oxides, and has excellent oxidizing power and environmentally friendly characteristics. Hydrofluoric acid (HF), on the other hand, has the ability to oxidize and remove silicon as it is etched. Therefore, when applied in combination, the surface of the single crystal silicon substrate 100 having an uneven surface can be formed as the silicon substrate 100 having a uniform surface.

That is, the curing of the surface of the silicon substrate 100 is performed by oxidizing the surface of the single crystal silicon substrate 100 by ozone (O ₃ ) contained in the cleaning liquid 124 to form an oxide film (SiO ₂ ). After the blocking of the damaged portion due to the anisotropic etching during the formation of 120 or at the same time, the oxide film (SiO ₂ ) by the hydrofluoric acid (HF) contained in the cleaning solution (124). As a result, a single crystal silicon substrate 100 having a substantially uniform surface is formed.

Referring to FIG. 3, a silicon film (not shown) is formed on the interlayer insulating layer pattern 122 while completely filling the opening 120 with selective epitaxial growth (SEG) seeded from the cured single crystal silicon substrate 100. Not formed).

Specifically, if the process temperature during the SEG process is less than about 750 ° C., since the growth of single crystal silicon is not easy, it is not preferable. If the process temperature exceeds about 1,250 ° C., the process control according to the growth of the single crystal silicon is It is not preferable because it is not easy. Therefore, the SEG process is preferably performed at a temperature of 750 to 1,250 ° C, and more preferably at a temperature of 800 to 900 ° C.

Preferably, the reaction gas used in the SEG process includes silicon gas. Examples of the silicon gas include silicon tetrachloride (SiCl ₄ ), silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), trichlorochloride silane (SiHCl ₃ ), and the like. It is preferable to use these individually, and you may mix and use two or more as needed.

Subsequently, a chemical mechanical polishing (CMP) process is performed to expose the surface of the interlayer insulating layer pattern 122 to the silicon layer to form a silicon layer pattern 130 in which the opening 120 is completely embedded. The silicon film pattern 130 is used as a contact between the single crystal silicon substrate 100 and the channel layer formed in a subsequent process.

After the cleaning process is performed with the cleaning solution 124 including ozone water (O ₃ ) and hydrofluoric acid (HF) as described above, the surface of the single crystal silicon substrate 100 is uniformed, and then the silicon film pattern 130 is subjected to the SEG process. By forming, the crystallinity of the silicon film pattern 130 used as a contact can be improved. Thus, a memory device having a reduced contact resistance can be manufactured.

Example 2

4 to 6 are cross-sectional views illustrating a method of manufacturing a stacked memory device in accordance with a second embodiment of the present invention.

The method of manufacturing a memory device described below is the same as that of the first embodiment except for the step of forming a second silicon film to be provided as a channel layer. Therefore, duplicate description is omitted.

First, by performing the same process as described with reference to FIGS. 1 to 3 in Example 1, as shown in FIG. 3, the interlayer insulating film pattern 222 and the first silicon film pattern on the single crystal silicon substrate 200 are shown. To form 230. The first silicon film pattern 230 is the silicon film pattern 130 of the first embodiment. At this time, although not shown, the interlayer insulating film pattern 222 and the first silicon film pattern 230 on which the CMP process is performed have a partially damaged surface due to overpolishing.

Referring to FIG. 4, an insulating film (not shown) is formed on the interlayer insulating film pattern 222 and the first silicon film pattern 230. The insulating film can be formed by depositing silicon oxide by a CVD method. The insulating film is provided in a template pattern for forming a second silicon film through a subsequent process.

Subsequently, a photoresist pattern 240 for selectively exposing the first silicon film pattern 230 and the insulating film facing the portion adjacent to the first silicon film pattern 230 is formed. The portion exposed by the photoresist pattern 240 is used as a channel layer by forming a second silicon film through a subsequent process.

A second preliminary opening (not shown) is formed by first etching the insulating layer so that the first silicon layer pattern 230 is not exposed using the photoresist pattern 240. More specifically, the first etching may be achieved by a dry etching process using CHF ₃ and oxygen gas.

Next, a portion of the insulating layer, the interlayer insulating layer pattern 222, and the first silicon layer pattern 230 positioned on the bottom surface of the second preliminary opening is etched to form a second opening 242. The depth of the second opening 242 is equal to the thickness of the second silicon film formed subsequently. As the second opening 242 is formed, the insulating film is converted into the insulating film pattern 244. In addition, the interlayer insulating layer pattern 222 and the first silicon layer pattern 230 exposed by the second opening 242 may have a damaged and rough surface by continuing the damaged surface in the CMP process after the etching process.

Although not shown, the photoresist pattern 240 is removed by ashing after the insulating film pattern 244 is formed.

Referring to FIG. 5, after the second opening 242 is formed, the upper surfaces of the exposed interlayer insulating film pattern 222 and the first silicon film pattern 230 may be ozone water (O ₃ ) and hydrofluoric acid ( A cleaning process is performed using the cleaning liquid 250 including HF).

The cleaning process is to complete the formation of the second opening 242 formed through the CMP process and the etching process, and to make an ohmic contact between the conductive material and the lower first silicon film pattern 230 applied in a subsequent process. The surface of the interlayer insulating film pattern 222 and the first silicon film pattern 230 exposed by the second opening 242 damaged by excessive etching and having a rough surface are cured. In addition, etching residues such as organic materials and particles, which are pollutants existing on the interlayer insulating film pattern 222 and the first silicon film pattern 230, and the natural oxide film are removed.

The cleaning liquid 250 used to clean the second opening 242 and the cleaning process using the cleaning liquid 250 are the same as the cleaning liquid 124 and the process described with reference to FIG. 2 of the first embodiment. Therefore, duplicate description is omitted.

Curing of the surfaces of the interlayer insulating film pattern 222 and the first silicon film pattern 230 is performed by using the cleaning liquid 250 as described above. That is, the surfaces of the interlayer insulating film pattern 222 and the first silicon film pattern 230 are oxidized by the ozone water (O ₃ ) to form an oxide film (SiO ₂ ) to block damage due to polishing and anisotropic etching. And later or at the same time, the interlayer insulating film pattern 222 and the first silicon film pattern having a substantially uniform surface by removing the oxide film SiO ₂ by the hydrofluoric acid (HF) contained in the cleaning liquid 250. To form 230.

Accordingly, the bottom surface of the second opening 242 cleaned by the cleaning liquid 250 may be cured so that the crystallinity of the second silicon film formed by the solid state epitaxy (SPE) method may be improved.

Referring to FIG. 6, a channel layer is formed on a portion of the interlayer insulating layer pattern 222 and the first silicon layer pattern 230 exposed to a bottom surface of the second opening 202 by a solid state epitaxy (SPE) method. A second silicon film 260 to be used is formed.

Specifically, an amorphous silicon film (not shown) is formed on the interlayer insulating film pattern 222 and the first silicon film pattern 230 by a CVD method while completely filling the inside of the second opening 242. Subsequently, an SPE method is performed to heat the amorphous silicon film at a temperature of 500 to 700 ° C. to convert the amorphous silicon film into a crystalline silicon film (not shown) having increased monocrystallinity.

Subsequently, a process for planarizing the surface of the crystalline silicon film is further performed. The planarization process includes a CMP process. The planarization process may be performed until the insulating layer pattern 244 is exposed, and a portion of the upper surface of the insulating layer pattern 244 may be further removed. As the planarization process proceeds, the crystalline silicon film is converted to the second silicon film 260.

As described above, the crystallinity of the second silicon film 260 formed by the SPE method and the cleaning process was confirmed by using an Electron BackScattering Diffraction apparatus. As a result, the crystallinity of the second silicon film 260 is increased by about 10% compared to the case where the conventional cleaning process is not performed. At this time, the comparison of the crystallinity was made in most of the amount of the crystal plane having the (100) orientation to confirm the identity with the single crystal silicon substrate 200 having a (100) orientation crystal structure.

According to the above process, the first silicon film pattern 230 having improved crystallinity may be formed in the opening by curing the etching damage by performing the cleaning process, and the crystallinity may be improved by performing the cleaning process. The second silicon film 260 may be formed as a channel layer. Accordingly, the stack type memory device including the first silicon layer pattern 230 and the second silicon layer 260 may have improved contact resistance due to improved crystallinity, thereby improving operation speed of the device.

As described above, in the method of manufacturing the memory device according to the preferred embodiment of the present invention, the surface of the substrate exposed by the opening is cleaned with a cleaning solution containing ozone water (O ₃ ) and hydrofluoric acid (HF) to form the opening. Excessive etching of the substrate surface can be cured. Therefore, the crystallinity of the silicon film formed by SEG growth from the substrate may be improved.

In addition, according to the present invention, the cleaning liquid comprises ozone water (O ₃ ) and hydrofluoric acid (HF) on the surfaces of the first silicon film pattern and the interlayer insulating film pattern CMP of the first silicon film pattern exposed through the second opening. When the CMP and the second opening are formed, excessive etching of surfaces of the first silicon layer pattern and the interlayer insulating layer pattern may be cured. As a result, in the second silicon film formed by the SPE method inside the second opening, the crystal surface having the (100) alignment crystal structure is increased. Accordingly, when the memory device including the first silicon layer pattern and the second silicon layer having improved crystallinity is manufactured, an improvement in operating speed may be expected.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (7)

Forming transistors comprising a source / drain region and a gate electrode on the single crystal silicon substrate; Forming an interlayer insulating film filling the transistors; Etching the interlayer insulating film to form an interlayer insulating film pattern including an opening exposing a surface of the silicon substrate; Curing the substrate surface by cleaning the surface of the substrate exposed by the opening with a cleaning liquid including ozone water (O ₃ ) and hydrofluoric acid (HF); And Growing silicon from the cured substrate to form a silicon film pattern in which the opening is completely buried. The method of claim 1, wherein the interlayer insulating layer is formed of at least one material selected from the group consisting of Boro Phospho Silicate Glass (BPSG), Phospho Silicate Glass (PSG), Tetra Ethyl Ortho Silicate (TEOS), and High Density Plasma (HDP) oxide. Method of manufacturing a memory device comprising a. The method of claim 1, wherein the curing is Oxidizing the surface of the silicon substrate with ozone water contained in the cleaning liquid to form an oxide film; And Forming a substrate having a substantially uniform surface by removing the oxide film by hydrofluoric acid contained in the cleaning liquid. The method of claim 1, wherein the ozone water is ozone water having an ozone concentration of 10 to 20 ppm. The method of claim 1, wherein the hydrofluoric acid is hydrofluoric acid diluted in deionized water having a concentration of 0.05 to 0.1%. Forming transistors comprising a source / drain region and a gate electrode on the single crystal silicon substrate; Forming an interlayer insulating film filling the transistors; Etching the interlayer insulating film to form an interlayer insulating film pattern including an opening exposing a surface of the silicon substrate; Performing a selective epitaxial process on the substrate exposed to the opening to form a first silicon film covering the interlayer insulating film pattern while filling the opening; Chemical mechanical polishing the first silicon film to expose a surface of the interlayer insulating film pattern to form a first silicon film pattern; Cleaning the upper surface of the first silicon film pattern using a cleaning solution including ozone water (O ₃ ) and hydrofluoric acid (HF); And And forming a second silicon film to be used as a channel layer on the interlayer insulating film pattern and the first silicon film pattern. 7. The method of claim 6, wherein the second silicon film is formed by a solid state epitaxy method.

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