KR20070089346A - Semiconductor memory device of hybrid type having single cell and twin cell - Google Patents

Abstract

A semiconductor memory device is provided to control effectively a refresh cycle by using a hybrid type cell structure composed of single cells and twin cells. A semiconductor memory device includes a single cell array(SB0 to SB3), a twin cell array(TB0 to TB3), and a refresh signal generating portion. The refresh signal generating portion is used for generating a first refresh signal for the single cell array and a second refresh signal for the twin cell array in response to single and twin cell array modes. The cycle of the second refresh signal is larger than that of the first refresh signal. The semiconductor memory device further includes a control portion for controlling the supplies of the first and second refresh signals in response to the single and twin cell array standby modes.

Description

Semiconductor memory device of mixed cell structure {Semiconductor memory device of hybrid type having single cell and twin cell}

1 is a diagram of a refresh related functional block of a general semiconductor memory device;

2 is a block diagram of a memory cell structure in a bank of FIG. 1;

3 is a block diagram illustrating a configuration of a general semiconductor memory device, schematically showing a portion related to self refresh;

4 is a view of a self refreshing device according to a first embodiment of the present invention;

5 is a view of a self refreshing apparatus according to a second embodiment of the present invention;

6 is a diagram of an automatic refresh apparatus according to a third embodiment of the present invention;

7 is a diagram of a twin cell structure applied to embodiments of the present invention.

The present invention relates to refreshing a semiconductor memory device, and more particularly, to a semiconductor memory device having a mixed cell structure.

In general, a semiconductor memory device such as a dynamic random access memory (DRAM) or the like is composed of a collection of unit cells composed of a transistor and a capacitor, and stores data in the capacitor.

However, since the capacitor formed on the semiconductor substrate cannot be completely electrically separated from the surroundings, leakage current occurs and data stored in the capacitor, that is, the charge is discharged over time, and thus the data stored in the cell disappears. do.

Therefore, in order to prevent such a phenomenon, the semiconductor memory device continuously performs an operation of rewriting information stored in a cell at a predetermined cycle, which is called self refresh.

The self refresh is performed by selecting a word line at least once within a retention time of each cell existing in a memory cell array of a memory, sensing the data, and then amplifying the data. At this time, the retention time means a time after which data is recorded in the cell and the data can be maintained in the cell without refreshing.

That is, when the self refresh operation command is input, the row address is sequentially increased at regular intervals, and the row address is sequentially increased to select the word line of the memory cell. At this time, the charge stored in the capacitor corresponding to the word line is amplified by the sense amplifying means and stored in the capacitor again. Through this series of self refresh processes, the stored data is preserved intact.

1 is a block diagram of a refresh related functional block of a general semiconductor memory device. Referring to FIG. 1, a control unit selects a cycle of bank self refresh pulses in four banks B0 to B3, outputs a refresh signal to the bank according to the pulse period, and an oscillator that outputs the refresh pulse.

FIG. 2 is a block diagram of a memory cell structure in the bank of FIG. 1. Referring to FIG. 2, one memory cell includes one transistor and one capacitor, and has a folded bit line sense amplifier structure.

3 is a block diagram showing the structure of a conventional semiconductor memory device, and schematically shows a portion related to self refresh.

Referring to FIG. 3, a conventional semiconductor memory device includes a basic pulse generator 10 generating a basic pulse generator, a self refresh counter 20 performing a count according to a self refresh cycle, a basic pulse generator 10, The self refresh pulse generator 30 outputs a self refresh pulse having a predetermined period using the self refresh counter 20, and the self refresh pulses output from the self refresh pulse generator 30 are counted to count each bank 61. And a row address counter 40 for outputting a signal for row address selection of the channels 62, 63, and 64, and a signal transmitted from the row address counter 40 to decode the corresponding banks 61, 62, 63, and 64. Four row decoders 51, 52, 63, 54 for selecting a row, and four memory banks 61, 62, 63, for performing self refresh according to the selection of the row decoders 51, 52, 63, 54, Consists of 64) The.

In this case, since the self refresh periods of the memory banks 61, 62, 63, and 64 are different from each other, the periods of the self refresh pulses are set in four banks 61, 62, 63, to prepare for the worst case considering the process. In the 64), the self refresh characteristic is generated in accordance with the self refresh period of the bank having the shortest period.

Recently, a DRAM having a twin cell structure in which one memory cell is composed of two transistors and two capacitors has been developed instead of a DRAM having a single cell structure in which one memory cell is composed of one transistor and one capacitor.

Compared to the single cell structure, the twin cell structure increases the refresh time of the cell, thereby reducing the activation recovery, that is, the cell data rewrite time, and reducing the standby current by increasing the refresh period. The active current can also be reduced by dividing the cell array to allow partial operation.

Such a twin cell structure is recognized to be suitable for a portable device because the refresh cycle does not have to be fast.

Therefore, there is a demand for a technique of applying a twin cell structure semiconductor memory device to a portable device device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and an object of the present invention is to provide a semiconductor memory device having a mixed cell structure in which specific cell banks of the semiconductor memory device are configured in a twin cell structure and the remaining portions are formed in a general single cell.

In accordance with another aspect of the present invention, a semiconductor memory device having a mixed cell structure includes a single cell array; Twin cell arrays; And a refresh signal generator for generating a single cell array refresh signal and a twin cell array refresh signal in response to the modes of the single cell array and the twin cell array.

Preferably, the period of the refresh signal for the twin cell array is longer than the period of the refresh signal for the single cell array.

A semiconductor memory device having a mixed cell structure according to a second aspect of the present invention for achieving the above object is a single cell array; Twin cell arrays; A self refresh signal generator for generating the self refresh signal; And supplying the self refresh signal to the single cell array as a first refresh signal in a single cell array standby mode in response to the standby mode of the single cell array and the twin cell array, and in the twin cell array standby mode, And a controller for dividing the period to supply a signal having a period longer than the self refresh signal to the twin cell array as a second refresh signal.

In addition, the semiconductor memory device of the mixed cell structure according to the third aspect of the present invention for achieving the above object is a single cell array; Twin cell arrays; And a first self refresh signal having a first period in the single cell array standby mode in response to the standby mode of the single cell array and the twin cell array, and having a period longer than the first period in the twin cell array standby mode. And a self refresh generator for generating a second self refresh signal.

In addition, a single cell array according to a fourth aspect of the present invention for achieving the above object; Twin cell arrays; And an automatic refresh counter configured to generate a first automatic refresh signal for every single cell command in the single cell array operation mode, and generate a second automatic refresh signal for a plurality of twin cell commands in the operation mode of the twin cell array. Include.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

The semiconductor memory device of the present invention basically configures a specific cell bank as a twin cell and configures the remaining banks as a single cell.

The self-refreshing single cell refresh period is set as the basic period, and the twin cell refresh period is longer than the single cell refresh period to reduce the refresh power consumption.

4 is a diagram of a self refreshing apparatus according to a first embodiment of the present invention. Referring to FIG. 4, the self-refreshing device according to the first embodiment of the present invention configures a specific cell bank in the twin cell banks TB0 to TB3, and the remaining cell banks in the single cell banks SB0 to SB3. The refresh generation clock is provided from the self refresh oscillator 120 so that the controller 110 can transfer the clock by the corresponding refresh period.

The control unit 110 applies the basic clock period applied from the self-refreshing oscillator 120 to the single cell banks SB0 to SB3, and applies a periodic signal slightly longer than the basic clock period to the twin cell banks TB0 to TB3. Is applied.

After the precharging of the bit line pairs, the word lines are sequentially activated in accordance with the trigger signal generated by the refresh oscillator 120 that defines the interval of self-refresh operation, and the sense amplifier is activated by activating the sense amplifier activation signal. The activated sense amplifier is refreshed by amplifying and rewriting the data of the memory cells appearing in the bit line pair.

5 is a view of a self refreshing apparatus according to a second embodiment of the present invention. Referring to FIG. 5, the control unit that is the same as the configuration of the first embodiment but provides a refresh cycle is omitted. Therefore, the self-refreshing oscillator 210 outputs different clock cycle signals to the single cell banks SB0 to SB3 and the twin cell banks TB0 to TB3. This can be configured by adding a divider to the self refresh oscillator 210.

6 is a diagram of an automatic refresh apparatus according to a third embodiment of the present invention. Referring to FIG. 6, the configuration of the second embodiment is the same, but when an auto refresh command is generated from the outside, one row is refreshed per command to the single cell banks SB0 to SB3, and the twin cell banks TB0 to TB3. The automatic refresh counter generator 310 which generates one refresh per one or more commands is configured.

The automatic refresh counter generator 310 applies a clock to the single cell banks SB0 to SB3 for counting the clock provided from the basic oscillator to perform the refresh for one command, and refreshes for one or more commands. The clock to perform the operation is applied to the twin cell banks TB0 to TB3.

7 is a diagram illustrating a twin cell structure applied to embodiments of the present invention. The twin cell banks TB0 to TB3 applied to the first, second, and third embodiments are one memory cell including two transistors and two capacitors, and the refresh time of the cell is increased compared to the single cell structure. Recovery, that is, cell data rewrite time can be reduced, and the standby current can be reduced by increasing the refresh period. The active current can also be reduced by dividing the cell array to allow partial operation.

The present invention can achieve the maximum effect when applied to a device in which the refresh cycle is important, such as a portable device. By applying a single cell and twin cell hybrid structure, the twin cell structure is applied to blocks that handle functions that require frequent refresh, and the single cell structure is applied to blocks that handle functions that do not require frequent refresh. When applied, the refresh cycle can be effectively controlled.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be practiced with modification. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the present invention, the refresh cycle can be effectively controlled by applying a single cell and twin cell mixed structure to a device in which a refresh cycle is important, such as a portable device.

Claims (5)

Single cell array; Twin cell arrays; And And a refresh signal generator for generating a single cell array refresh signal and a twin cell array refresh signal in response to the modes of the single cell array and the twin cell array. The semiconductor memory device of claim 1, wherein a cycle of the refresh signal for the twin cell array is longer than a cycle of the refresh signal for the single cell array. Single cell array; Twin cell arrays; A self refresh signal generator for generating the self refresh signal; And In response to the standby mode of the single cell array and the twin cell array, in the single cell array standby mode, the self refresh signal is supplied to the single cell array as a first refresh signal, and in the twin cell array standby mode, the main of the self refresh signal is supplied. And a controller for dividing a group and supplying a signal having a period longer than a self refresh signal to the twin cell array as a second refresh signal. Single cell array; Twin cell arrays; And A first self refresh signal having a first period is generated in the single cell array standby mode in response to the standby mode of the single cell array and the twin cell array, and has a period longer than the first period in the twin cell array standby mode. 2. A semiconductor memory device having a mixed cell structure, comprising: a self refresh generator for generating a self refresh signal. Single cell array; Twin cell arrays; And The single cell array operation mode includes an automatic refresh counter that generates a first automatic refresh signal for every single cell command, and generates a second automatic refresh signal for each of the plurality of twin cell commands generated in the operation mode of the twin cell array. A semiconductor memory device having a mixed cell structure, characterized in that.

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