KR20070084698A - Array substrate - Google Patents

Abstract

An array substrate is provided to form the third shielding electrode extended from the first and second shielding electrodes, thereby preventing the open of the first and second shielding electrodes from being generated. A gate line(GL) is formed on a base substrate. A data line(DL) is insulated and crossed with the gate line and defines a pixel area. A switching device is equipped within the pixel area and electrically connected with the gate and data lines. A passivation layer covers the switching device and the data line. A pixel electrode(PE) is formed on the passivation layer and electrically connected with the switching device. A shielding member(SP) is formed on the passivation layer and electrically insulated with the pixel electrode. The shielding member comprises the first shielding electrode(SE1) formed correspondingly to the formation area of the data line. The second shielding electrode(SE2) is correspondingly formed at the formation area of the gate line and branched from the first shielding electrode at the crossing area of the gate and data lines. The third shielding electrode(SE3) is extended from the first and second shielding electrodes at the corner contacting with the first and second shielding electrodes.

Description

Array board {ARRAY SUBSTRATE}

1 is a plan view of an array substrate according to an embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a process of manufacturing an array substrate at portions cut along lines II ′ and II-II ′ of FIG. 1.

3 to 5 are diagrams illustrating the first opening illustrated in FIG. 2B.

* Description of the symbols for the main parts of the drawings *

100: array substrate 110: base substrate

120: thin film transistor 121: gate electrode

123: source electrode 124: drain electrode

130: gate insulating film 140: protective film

150 electrode layer 160 photoresist

170: mask

The present invention relates to an array substrate, and more particularly, to an array substrate capable of improving productivity and improving display quality.

BACKGROUND ART In general, a liquid crystal display device includes an liquid crystal display panel configured to display an image including an array substrate, a color filter substrate coupled to face the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate.

The array substrate is provided with a gate line and a data line that crosses the gate line insulated from the gate line. The pixel area is defined by the gate line and the data line in the array substrate, and the thin film transistor and the pixel electrode are provided in the pixel area. The gate and source electrodes of the thin film transistor are electrically connected to the gate line and the data line, respectively, and the pixel electrode is connected to the drain electrode of the thin film transistor.

Meanwhile, the common electrode facing the pixel electrode is formed on the color filter substrate. Therefore, an electric field is formed between the two substrates by the pixel voltage applied to the pixel electrode and the common voltage applied to the common electrode. Therefore, the light transmittance of the liquid crystal molecules included in the liquid crystal layer is controlled by the electric field so that an image may be displayed on the screen of the liquid crystal display panel.

However, since the pixel electrode is not formed in the region where the gate line and the data line are formed, the light transmittance of the liquid crystal molecules cannot be controlled and light leakage occurs.

In order to eliminate such light leakage, a structure of overlapping the pixel electrode and the gate line and overlapping the pixel electrode and the data line has been proposed. However, in such a structure, a signal applied to the pixel electrode is distorted due to parasitic capacitance occurring between the pixel electrode and the gate line and between the pixel electrode and the data line.

Accordingly, it is an object of the present invention to provide an array substrate for improving productivity and improving display quality.

The array substrate according to the present invention includes a base substrate, a gate line, a gate insulating film, a data line, a switching element, a protective film, a pixel electrode, and a shielding portion.

The gate line is formed on the base substrate, and the gate insulating layer covers the gate line. The data line is provided on the gate insulating layer and intersects with the gate line to define a pixel area. The switching element is provided in the pixel area and is electrically connected to the gate line and the data line. The passivation layer covers the switching element and the data line. The pixel electrode is formed on the passivation layer in the pixel region and is electrically connected to the switching element.

The shielding part includes first to third shielding electrodes and is electrically insulated from the pixel electrode. The first shielding electrode is formed on the passivation layer corresponding to the first region where the data line is formed. The second shielding electrode is formed on the passivation layer corresponding to the second region in which the gate line is formed, and is branched from the first shielding electrode in a region where the gate line and the data line cross each other. The third shielding electrode extends from the first and second shielding electrodes at corners where the first and second shielding electrodes contact each other.

According to the array substrate, the third shielding electrode extending from the first and second shielding electrodes is formed at an edge where the first and second shielding electrodes contact each other, whereby the data line and the gate line cross each other. The opening of the first and second shielding electrodes can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of an array substrate according to an embodiment of the present invention.

Referring to FIG. 1, the array substrate 100 is a substrate on which pixels are formed on the base substrate 110. The pixel includes the thin film transistor 120 and the pixel electrode PE.

The array substrate 100 is used in a liquid crystal display panel (not shown) for displaying an image. In particular, the liquid crystal display panel includes a color filter substrate (not shown) coupled to the array substrate 100, the array substrate 100, and a liquid crystal layer interposed between the array substrate and the color filter substrate. Not shown). Here, an electric field is formed between the two substrates by the pixel voltage applied to the pixel electrode PE and the common voltage applied to the common electrode provided on the color filter substrate. Accordingly, the light transmittance of the liquid crystal molecules included in the liquid crystal layer is controlled by the electric field so that the image may be displayed on the screen of the liquid crystal display panel.

On the base substrate 110 of the array substrate 100, a gate line GL and a data line DL intersecting the gate line GL to be insulated from each other are provided. The gate line GL extends in a first direction D1, and the data line DL extends in a second direction D2 orthogonal to the first direction D1. Although not shown in the figure, a gate insulating film is interposed between the gate line GL and the data line DL.

The thin film transistor 120 is electrically connected to the gate line GL and the data line DL. Specifically, the gate electrode 121 of the thin film transistor 120 is branched from the gate line GL, the source electrode 124 is branched from the data line DL, and the drain electrode 125 is the source. The electrode 124 is spaced apart at predetermined intervals and electrically connected to the pixel electrode PE.

The gate electrode 121 is covered by the gate insulating layer, and an active layer 122 and an ohmic contact layer are formed on the gate insulating layer corresponding to a region where the gate electrode 121 is formed. Accordingly, the source electrode 124 and the drain electrode 125 face the gate electrode 121 with the gate insulating layer, the active layer 122, and the ohmic contact layer interposed therebetween.

The thin film transistor 120 is covered by a protective film (not shown). A contact hole CT is formed in the passivation layer to expose the drain electrode 125 of the thin film transistor 120. The pixel electrode PE is formed on the passivation layer and is electrically connected to the drain electrode 125 through the contact hole CT.

The array substrate 100 further includes a shielding part SP formed on the passivation layer. The shielding part SP includes first to third shielding electrodes SE1, SE2, and SE3, and is electrically insulated from the pixel electrode PE at predetermined intervals. The common voltage is applied to the first to third shielding electrodes SE1 to SE3 of the shielding part SP. Accordingly, the shielding part SP may prevent light leakage by controlling the transmittance of liquid crystals in a region where the pixel electrode PE is not formed. In addition, the shielding part SP reduces parasitic capacitance generated between the pixel electrode PE and the data line DL and between the pixel electrode PE and the gate line GL. .

As illustrated in FIG. 1, the first shielding electrode SE1 extends in parallel to the data line DL in a region where the data line DL is formed, and the second shielding electrode SE2 is formed on the gate. The line GL extends in parallel with the gate line GL. The second shielding electrode SE2 is branched from the first shielding electrode SE1 in a region where the gate line GL and the data line DL intersect each other.

The third shielding electrode SE3 extends from the first and second shielding electrodes SE1 and SE2 in a region where the gate line GL and the data line DL cross each other. For example, the third shielding electrode SE3 extends in a triangular shape from an edge where the first and second shielding electrodes SE1 and SE2 meet.

As such, when the third shielding electrode SE3 is formed at the corner where the first and second shielding electrodes SE1 and SE2 meet, the first and second shielding electrodes SE1 and SE2 are opened to each other. Can be prevented.

2A to 2C are cross-sectional views illustrating a process of manufacturing an array substrate at portions cut along lines II ′ and II-II ′ of FIG. 1. 3 to 5 illustrate the shape of the first light blocking pattern illustrated in FIG. 2B.

Referring to FIG. 2A, a passivation layer 140 is formed on the base substrate 110 on which the gate line GL, the data line DL, and the thin film transistor 120 are formed. The electrode layer 150 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 140. The photoresist 160 is formed on the electrode layer 150.

As shown in FIG. 2B, a mask 170 is disposed on the photoresist 160. The mask 170 has a first light blocking pattern 171 corresponding to a region where the first to third shielding electrodes SE1 to SE3 are formed, and a second light blocking pattern corresponding to a region where the pixel electrode PE is to be formed. 172 is formed. Therefore, the mask 170 transmits UV light only in regions where the first and second light blocking patterns 171 and 172 are not formed.

As illustrated in FIG. 3, the first light blocking pattern 171 may include a first shielding pattern 171a corresponding to the first shielding electrode SE1 and a second shielding pattern corresponding to the second shielding electrode SE2. 171b and a third shielding pattern 171c corresponding to the third shielding electrode SE3.

Thereafter, when the photoresist 610 is exposed after being irradiated with UV light, the photoresist 160 remains only in regions corresponding to the first and second light blocking patterns 171 and 172.

Here, the first light blocking pattern 171 is formed to have a width larger than an intersection area where the gate line GL and the data line DL intersect each other. Therefore, the UV light is blocked from entering the data line DL. Therefore, after the UV light is reflected by the data line DL, a phenomenon of exposing the photoresist 160 provided on the data line DL is prevented. As a result, the opening of the first and second shielding electrodes SE1 and SE2 in the region where the gate line GL and the data line DL intersect can be prevented.

3 illustrates a third shielding pattern 171c having a triangular shape. However, the first light shielding pattern 171 of the mask 170 may include a fourth shielding pattern 171d having a hypotenuse in a staircase shape and a fifth shielding pattern 171e having a hypotenuse in a round shape.

Referring to FIG. 2C, when the exposed electrode layer 150 is etched and the photoresist 160 remaining on the electrode layer 150 is stripped, first to third shielding electrodes may be formed on the passivation layer 140. SE1 to SE3) and the pixel electrode PE are formed.

According to the array substrate, the third shielding electrode extending from the first and second shielding electrodes is formed at an edge where the first and second shielding electrodes contact each other, whereby the data line and the gate line cross each other. The opening of the first and second shielding electrodes can be prevented. As a result, the productivity of the array substrate can be improved.

In addition, by controlling the transmittance of liquid crystals in a region where the pixel electrode is not formed, light leakage can be prevented, and parasitic capacitance generated between the pixel electrode and the data line and between the pixel electrode and the gate line is reduced. Let's do it. As a result, the display quality of the liquid crystal display device employing the above-described array substrate can be improved.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (5)

A base substrate; A gate line formed on the base substrate; A data line crossing the gate line and insulated from the gate line to define a pixel area; A switching element provided in the pixel region and electrically connected to the gate line and the data line; A passivation layer covering the switching element and the data line; A pixel electrode formed on the passivation layer in the pixel region and electrically connected to the switching element; And A shielding part formed on the passivation layer and electrically insulated from the pixel electrode; The shielding unit, A first shielding electrode formed corresponding to a region where the data line is formed; A second shielding electrode formed corresponding to a region where the gate line is formed and branched from the first shielding electrode in a region where the gate line and the data line cross each other; And And a third shielding electrode extending from the first and second shielding electrodes at a corner portion where the first and second shielding electrodes are in contact with each other. The array substrate of claim 1, wherein the third shielding electrode has a triangular shape. The array substrate of claim 2, wherein the hypotenuse of the third shielding electrode has a step shape. The array substrate of claim 2, wherein the hypotenuse of the third shielding electrode has a round shape. The array substrate of claim 1, wherein the first to third shielding electrodes are made of the same material as the pixel electrode.

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