KR20070081309A - Synchronous memory device generating additive latency using cas latency - Google Patents

Abstract

A synchronous memory device is provided to minimize the usage of a flip flop and reduce the number of used latches by comprising an additive latency generation circuit of generated additive latency using CAS latency. A CAS latency generation circuit(32) latches a plurality of addresses in synchronization with a mode register signal, and generates a plurality of CAS latency by decoding the latched addresses. A mode register generates the mode register signal by receiving the addresses and internal commands. An additive latency generation circuit(34) generates at least one additive latency by decoding the CAS latency.

Description

Synchronous Memory Device generating Additive Latency using CAS Latency

1 shows a block for data output of a synchronous memory device according to the present invention.

2 shows a specification for cas latency generation of a synchronous memory device.

3 is an embodiment of implementing a cas latency generation circuit of the synchronous memory device according to the present invention.

4 illustrates a specification for additive latency generation of a synchronous memory device.

5 is an embodiment of implementing a passive latency generation circuit of a synchronous memory device according to the present invention.

FIG. 6 is an embodiment of implementing a circuit that generates an active latency from the cascade latencies generated from FIGS. 3 and 5.

* Description of the symbols for the main parts of the drawings *

32: CL generation circuit

34: AL generation circuit

The present invention relates to a synchronous semiconductor memory device, and more particularly to an output buffer of a synchronous semiconductor memory device.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and the operation speed thereof. In order to improve the operation speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from an external memory chip has been introduced. The first proposed synchronous memory device is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of a clock from the outside.

However, SDR synchronous memory devices are also insufficient to meet the speed of systems requiring high speed operation. Accordingly, a double data rate (DDR) synchronous memory device that processes two data in one clock cycle has been proposed. Two data are inputted and outputted in synchronization with the rising and falling edges of the clock inputted from the external data input and output pins of the DDR synchronous memory device, even though the clock frequency is not increased. At least twice the bandwidth of the SDR synchronous memory device can be realized. Therefore, high speed operation can be realized.

However, a DDR synchronous memory device must send or receive two data in one clock cycle. Therefore, in order to perform data input / output effectively, the data access method used in the conventional DDR synchronous memory device cannot be used.

If the clock cycle is about 10 nsec, subtracting the rising and falling time (approximately 0.5 × 4 = 2) and the time to meet other specifications, etc., the two data are continuous for about 6 nsec or less. Should be dealt with. This process is difficult to perform in a DDR synchronous memory device. The DDR synchronous memory device inputs and outputs data at the rising edge and the falling edge of the clock only when data is sent to or received from the outside, and processes two data that are synchronized to one edge of the clock substantially inside the memory device.

In the DDR synchronous memory device, data or commands may be input and output in synchronization with the clock at the rising edge of the clock as well as the falling edge of the clock. Therefore, a data rate corresponding to a 200 MHz clock can be obtained with a 100 MHz clock. To do this, the duty of the clock must be 50%.

DDR synchronous memory devices are further divided into DDR1 SDRAM, DDR2 SDRAM, and DDR3 SDRAM. The DDR1 synchronous memory device performs two-bit prefetch at the time of input / output, so that the burst length BL of data is two. The DDR2 synchronous memory device performs 4-bit prefetch so that the burst length BL of data is four. The synchronous memory device performs 8-bit prefetch so that the burst length BL of data is eight. Here, the burst length BL of 8 means that 8 data synchronized with the clock are continuously inputted and outputted through one input / output terminal.

The synchronous memory device supports a read leveling operation. The read leveling operation is an operation for adjusting the skew of the DQS between the chip set and the memory chip by transferring a data pattern predefined in a register in the memory chip to the chip set. Here, the operation of reading the data pattern stored in the register is performed independently of the normal data stored in the memory cell. Hereinafter, this operation is referred to as a special read operation to distinguish it from a normal read operation.

Therefore, the DDR synchronous memory device needs a new data access method to receive data and transfer the data to the internal core area or to output the data transmitted from the core area to the outside. DDR synchronous memory devices, on the other hand, use some different concepts from previous asynchronous memory devices. Among them are additive latency (AL) and cas latency (CL).

The additive latency (AL) refers to the number of clock signals (iclk) from the DDR synchronous memory device to the RAS to CAS timing (tRCD) time after the read command is input. Here, the tRCD time refers to the time from the row address input to the timing at which the column address is input. The DDR synchronous memory device becomes active at the timing at which the row address is input. Thereafter, a read command is input before timing of inputting a column address. At this time, the moment from when the read command is input, the column address is input, and the timing at which the actual read command is executed is called the additive latency AL.

The CAS latency CL refers to the number of clocks after the read command is input until the data is output from the DDR synchronous memory device. For example, CL = 3 means that after a read command is input to a DDR synchronous memory device, data is output to the outside after three clock cycles. Therefore, the cascade latency mode value determines the timing of outputting data. The DDR synchronous memory device detects the CL value set during initial operation and uses the data to access and output the data.

Accordingly, the DDR synchronous memory device delays the operation clock cycle by the set cascade latency CL of the signal generated in response to the read command, and then generates a data output enable signal. The data output enable signal is activated to output the accessed data to the outside in response to the read command.

Conventional synchronous memory devices are configured to generate additive latency (AL) coded according to an external address.

An object of the present invention is to provide a synchronous semiconductor memory device that implements the additive latency AL using the cascade latency CL.

In accordance with another aspect of the present invention, a synchronous memory device includes: a cascade latency generation circuit configured to generate a plurality of cas latency by decoding a plurality of addresses in synchronization with a mode register signal and decoding the latched plurality of addresses; A mode register configured to receive the plurality of addresses and internal commands and generate the mode register signal; And a additive latency generation circuit configured to generate the plurality of additive latency by decoding the plurality of cas latencys.

In this embodiment, at least one additive latency among the plurality of additive latency is generated directly by the cas latency generating circuit.

In this embodiment, the synchronous memory device is a DDR3 synchronous memory device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 illustrates blocks for data output in a synchronous memory device according to the present invention. Referring to FIG. 1, a synchronous memory device receives a command signal (/ CS, / RAS, / CAS, / WE), receives an input buffer and outputs a buffer, and outputs a command signal buffered and output to an input buffer 10. Decoded (/ CS, / RAS, / CAS, / WE) output from the command decoder 20, the command decoder 20 for outputting a signal corresponding to the current command state (for example, read signal (rd)) The read operation timing controller 30 which generates and outputs a read command execution signal casp_rd after the clock period of the clock signal iclk corresponding to the additive latency AL to execute the read operation corresponding to the read signal rd. ), Through the CAS latency generation circuit 32 and CAS latency information, which receives the address information and command signals (/ CS, / RAS, / CAS, / WE) to generate the CAS latency (CL). The additive latency generating circuit 34 which generates the creative latency AL and the read execution signal casp_rd. Memory core block 80 that outputs the corresponding data to the data output buffer 50 in response to the < RTI ID = 0.0 > 1), and < / RTI > After receiving the delay lock loop 70 that outputs the clocks fclk_dll and rclk_dll with the time delay fixed, and the read command execution signal casp_rd, and delaying the clock corresponding to the cascade latency CL, the data output enable signal ( The data output controller 40 which generates and outputs ROUTEN and FOUTEN, and externally transmits the data Data transmitted from the memory core block in response to the data output enable signals ROUTEN and FOUTEN through the data output pad DQ pad. It includes a data output buffer 50 for outputting.

Therefore, the read operation timing controller 30 receives the read command rd, delays the cycle of the clock signal iclk by the additive latency AL, and then generates and outputs the read execution signal casp_rd.

Meanwhile, when the read execution signal casp_rd is input, the memory core block 80 outputs data corresponding to the input address to the data output buffer 50.

Here, the delay locked loop 70 outputs delayed fixed signals fclk_dll and rclk_dll obtained by delaying the clock signal iclk for a predetermined time. The delay locked signals fclk_dll and rclk_dll are clock signals generated by the delay locked loop 70 to output data to the outside of the memory device in synchronization with the rising edge and the falling edge of the external clock, respectively.

The data output controller 40 generates a signal internally synchronized with the clock signal iclk using the read execution signal casp_rd, and then outputs the delayed fixed signals fclk_dll and rclk_dll output from the delay locked loop 70. The data output enable signals ROUTEN and FOUTEN are outputted to the data output buffer 50 in synchronization with the clock latency CL and delayed by a clock cycle of the clock signal iclk. The data output enable signals ROUTEN and FOUTEN are signals for synchronizing and outputting data to the rising edge and the falling edge of the clock signal iclk, respectively.

The data output buffer 50 outputs data output from the memory core block 80 in response to the data output enable signals ROUTEN and FOUTEN, and the transferred data is transmitted through the data output pad DQ pad. Output to the outside.

2 illustrates a specification of a synchronous memory device for cascading CL generation. FIG. 3 is an embodiment of implementing a cas latency generating circuit of the synchronous memory device according to the specification of FIG. 2.

Referring to FIG. 3, the cas latency generating circuit includes an address latch 110, a latency decoder 120, and a mode register 130.

The address latch 110 includes latches 110, 112, 114, and 116. The latches 110, 112, 114, and 116 latch the values of the input addresses A2, A4, A5, and A6, and synchronize the address information signals PA2, PA4, PA5, PA6, / in synchronization with the mode register signal MR0. PA2, / PA4, / PA5, / PA6) is output to the latency decoder 120.

The latency decoder 120 includes AND gates 121 ˜ 126. The latency decoder 120 combines the address information signals PA2, PA4, PA5, PA6, / PA2, / PA4, / PA5, / PA6 transmitted from the mode register 100 according to the specification shown in FIG. Generate CAS latency (CL5 ~ CL-10). 2 and 3, for example, CL5 is an output value of the AND gate 121 that receives / PA2, PA4, / PA5 and / PA6 signals.

The mode register 130 receives address information and command signals / CS, / RAS, / CAS and / WE to generate a mode register signal MR0.

4 illustrates a specification of a synchronous memory device for additive latency generation. FIG. 5 is an embodiment of implementing a passive latency generation circuit of a synchronous memory device according to the specification of FIG. 4.

Referring to FIG. 5, the additive latency generation circuit includes an address latch 210, a latency decoder 220, and a mode register 130.

The address latch 210 includes latches 211 and 212. The latches 211 and 212 receive and latch the addresses A3 and A4, and generate the address degree signals TA3, TA4, / TA3, and TA4 in synchronization with the mode register signal MR1 to generate a latency decoder. Pass in 220.

Latency decoder 220 includes end gates 221, 222, and 223. The latency decoder 220 logically combines the address information signals TA3, TA4, / TA3, and TA4 transmitted from the mode register 210 to add the additive latency AL0 and the cascade latency CL-1, CL. -2) 4 and 5, AL0 is an output value of the AND gate 211 receiving the / TA3 and / TA4 signals, and CL-1 is an output value of the AND gate 222 receiving the TA3 and / TA4 signals. , CL-2 is the output value of the AND gate 223 which received the / TA3 and / TA4 signals.

The mode register 130 receives address information and command signals / CS, / RAS, / CAS and / WE to generate a mode register signal MR1.

FIG. 6 is an embodiment in which a circuit for decoding the additive latencies AL3 to AL9 from the CAS latencies CL-1, CL-2, CL5 to CL-10 generated from FIGS. 3 and 5 is implemented. The additive latency generation circuit 300 includes end gates 311 to 322. Referring to FIG. 6, AL3 is an output value of the AND gate 311 receiving CL-2 and CL5 signals, and AL4 is an output value of the AND gate 312 receiving CL-1 and CL5 signals, or CL-2 and CL6. One of the output values of the AND gate 313 that receives the signal. AL5 is one of an output value of the AND gate 314 that receives the CL-1 and CL6 signals or an output value of the AND gate 315 that receives the CL-2 and CL7 signals. AL6 is one of the output values of the AND gate 316 receiving the CL-1 and CL7 signals or the output values of the AND gate 317 receiving the CL-2 and CL8 signals. AL7 is one of the output values of the AND gate 318 which received the CL-1 and CL8 signals or the output value of the AND gate 319 which received the CL-2 and CL9 signals. AL8 is one of the output values of the AND gate 320 receiving the CL-1 and CL9 signals or the output value of the AND gate 321 receiving the CL-2 and CL-10 signals. AL9 is an output value of the AND gate 322 which has received the CL-1 and CL8 signals.

The synchronous memory device according to the present invention solves the initial value problem generated during the power-up process by minimizing the use of flip-flops while switching to the end gate while generating the additive latency AL. .

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the synchronous semiconductor memory device according to the present invention includes a random latency generating circuit that logically combines to generate the negative latency AL through the cascade latency CL, thereby minimizing the use of flip-flops, and the latch used. Reducing the number of times solves the initial value problem caused by the power-up process.

Claims (3)

A cascade latency generation circuit, wherein a plurality of addresses are latched in synchronization with a mode register signal, and decode the latched plurality of addresses to generate a plurality of cas latencys; A mode register configured to receive the plurality of addresses and internal commands and generate the mode register signal; And And a additive latency generation circuit configured to decode the plurality of cas latencys to generate a plurality of additive latency. The method of claim 1, And at least one additive latency among the plurality of additive latency is generated directly by the cas latency generating circuit. The method of claim 1, The synchronous memory device is a synchronous memory device, characterized in that the DDR3 synchronous memory device.

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