KR20070079232A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) device is provided to enhance image quality by increasing the number of pixels in a liquid crystal panel by double. First data lines(DD1~DDm) are formed to cross with first gate lines(GD1~GDn). Second gate lines(GA1~GAn) are alternately disposed with the first gate lines. Second data lines(DA1~DAm) are formed to cross with the second gate lines and alternately disposed with the first gate lines. First and second pixels(DP,AP) are disposed on regions which are defined by the first gate and first data lines, and the second gate and second data lines. A timing controller(110) generates a pixel data signal, first and second vertical synchronous signals, first and second gate clock signals, and a control signal. A gate driver(120) drives the first and second gate lines in response to the first and second vertical synchronous signals, and the first and second gate clock signals. A data driver drives the data lines in response to the control signal.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a view showing a configuration of a liquid crystal display according to a preferred embodiment of the present invention;

FIG. 2 is a diagram showing a specific configuration of an embodiment of the present invention of the source driver shown in FIG. 1; FIG.

3 is a timing diagram of signals used in a liquid crystal display according to an exemplary embodiment of the present invention;

4A to 4C illustrate an image displayed on the liquid crystal panel during the first to third frames shown in FIG. 3;

5 is a view illustrating a change in luminance of a CRT display device;

6 is a view illustrating a change in brightness of a general liquid crystal display; And

7 illustrates a change in luminance of the liquid crystal display according to the exemplary embodiment of the present invention.

* Description of the main parts of the drawing

100: liquid crystal display 110: timing controller

120: gate driver 130: source driver

140: liquid crystal panel 150: gray voltage generator

210: shift register 220: data register

230, 260: latch 240, 270: digital-to-analog converter

250: data output buffer 280: auxiliary data output buffer

The present invention relates to a liquid crystal display device.

Recently, the field of application of liquid crystal display devices has been diversified. In particular, a liquid crystal display implemented as a television, which is a representative video display device, requires fast response speed for smooth frame switching. In order to meet this demand, an impulsive driving liquid crystal display device having an operating frequency of 120 Hz has also been proposed.

However, as the operating frequency is raised from 60 Hz to 120 Hz, there is a problem that technologies suitable for the operating frequency 60 Hz cannot be applied at the operating frequency 120 Hz.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of impulsive driving at an operating frequency of 60 Hz.

According to a feature of the present invention for achieving the above object, the liquid crystal display device includes a first and second pixels, a timing controller, a gate driver and a data driver. The first pixels are respectively disposed in regions defined by the plurality of first gate lines and the plurality of first data lines. The second pixels are respectively disposed in regions defined by the plurality of second gate lines and the plurality of second data lines. The timing controller includes a pixel data signal, a first vertical synchronization start signal and a first gate clock signal for driving the plurality of first gate lines, a second vertical synchronization start signal for driving the plurality of second gate lines, and Generate a second gate clock signal and control signals. The gate driver sequentially drives the plurality of first gate lines and the plurality of second gate lines in response to the first and second vertical synchronization start signals and the first and second gate clock signals. . A data driver drives the data lines in response to the control signals.

The second vertical synchronization start signal is activated before the second vertical synchronization start signal. In particular, the second pixels display black.

The source driver may include a first circuit driving the plurality of first data lines in response to the pixel data signal and the control signals, and the plurality of second data in response to the pixel data signal and the control signals. And a second circuit for driving the lines with a signal corresponding to the first color.

The second circuit includes a latch for latching the pixel data signal, and a digital-to-analog converter for converting the digital pixel data signal output from the latch into an analog pixel data signal corresponding to black color.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display device 100 includes a timing controller 110, a gate driver 120, a source driver 130, a liquid crystal panel 140, and a gray voltage generator 150.

The liquid crystal panel 140 includes a plurality of first gate lines GD1 to GDn, a plurality of second gate lines GA1 to GAn, and a plurality of first data lines DD1 to cross the first gate lines. DDm), on the first pixels DP and the second gate line and the second data line, respectively, arranged in the region defined by the second data lines DA1 to DAm, the first gate line, and the first data line. Second pixels AP are arranged in the area defined by each. The plurality of first and second gate lines are alternately arranged one by one. The plurality of first and second data lines are alternately arranged one by one. One first pixel DP and one second pixel AP are used to display one dot information.

Each first pixel DP includes a thin film transistor (not shown) having a gate electrode and a source electrode connected to a gate line and a data line, and a liquid crystal capacitor (not shown) and a storage capacitor connected to a drain electrode of the thin film transistor. (Not shown). Each second pixel AP includes a thin film transistor (not shown) having a gate electrode and a source electrode connected to a second gate line and a second data line, respectively, and a liquid crystal capacitor (not shown) connected to a drain electrode of the thin film transistor. ) And a storage capacitor (not shown).

In this pixel structure, when the first and second gate lines are sequentially selected by the gate driver 120, and a gate-on voltage is applied to the selected gate line in a pulse form, the thin film transistor of the pixel connected to the gate line is turned on. Subsequently, a voltage including pixel information is applied to each data line by the source driver 130. This voltage is applied to the liquid crystal capacitor and the storage capacitor through the thin film transistor of the pixel, and the predetermined display operation is performed by driving the liquid crystal and the storage capacitor. The first pixels DP display a color corresponding to the pixel data signal, and the second pixels AP display a specific color. The driving of the first and second pixels DP and AP will be described later in detail.

The timing controller 110 receives a current pixel data signal RGB, a horizontal sync signal H_SYNC, a vertical sync signal V_SYNC, a clock signal MCLK, and a data enable signal DE input from an external device. The timing controller 110 outputs the pixel data signal RGB ′ and the control signals obtained by converting the data format to match the interface specification with the source driver 130 to the source driver 140. The control signals provided from the timing controller 110 to the source driver 130 include a latch signal TP, a horizontal synchronization start signal STH, a start horizontal signal, an inversion signal POL, and a clock signal HCLK.

In addition, the timing controller 110 outputs control signals such as vertical synchronization start signals STVA, STVD, and start vertical, and gate clock signals CPVA and CPVD to the gate driver 120. The vertical synchronization start signal STVD and the gate clock signal CPVD are signals for driving the first gate lines GD1-GDn, and the vertical synchronization start signal STVA and the gate clock signal CPVA are the second gate. These signals are for driving the lines GA1 -GAn.

The gate driver 120 sequentially scans the second gate lines GA1 -GAn of the liquid crystal panel 140 in response to the control signals STVA and CPVA provided from the timing controller 110. The first gate lines GD1-GDn of the liquid crystal panel 140 are sequentially scanned in response to the control signals STVD and CPVD provided from 110. In this case, scanning refers to sequentially applying gate-on voltages to the gate lines to make pixels of the gate line to which the gate-on voltages are applied to enable data writing.

The gray voltage generator 150 provides the gray voltages V1 -V18 corresponding to the pixel data signal to the source driver 130.

The source driver 130 corresponds to the pixel data signal RGB ′ among the gray voltages from the gray voltage generator 150 in response to the control signals TP, STH, POL, and HCLK provided from the timing controller 110. The data lines DD1 -DDm and DA1 -DAm of the liquid crystal panel 140 are driven with the gray voltages. In general, the source driver 130 is composed of a plurality of integrated circuits.

2 is a diagram illustrating a detailed configuration of the source driver 130 shown in FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 2, the source driver 130 may include a shift register 210, a data register 220, latches 230, digital-to-analog converters 240 and 270, a data output buffer 250 and an auxiliary circuit. A data output buffer 280.

The shift register 210 sequentially shifts the horizontal synchronization start signal STH from the timing controller 110 according to the clock signal HCLK and outputs the sampling signal.

The data register 220 sequentially samples and stores the pixel data signal RGB ′ from the timing controller 110 in predetermined units in response to the sampling signal from the shift register 210. At this time, the size of the data register 220 is (the number of horizontal pixels * the number of bits of each pixel data).

Each of the latches 230 and 260 outputs a pixel data signal from the data register 220 in response to the latch signal TP from the timing controller 110.

The digital-to-analog converter 240 converts the pixel data signal from the latch 230 into an analog pixel signal using the gray scale voltages V1 -V18, and outputs the analog pixel signal in response to the inversion signal POL. . The gray voltages VO-V18 are generated by the gray voltage generator 150.

The data output buffer 250 stores the analog pixel signal output from the digital-to-analog converter 240 and supplies the same to the data lines DD1-DDm of the liquid crystal panel in synchronization with the latch signal TP. For example, the latch 230 outputs the pixel data signal from the data register 220 to the digital-analog converter 240 at the rising edge of the latch signal TP, and the first output buffer 250. Transmits the output of the digital-analog converter 240 to the first data lines DD1 -DDm at the falling edge of the latch signal TP.

The digital-analog converter 270 converts the pixel data signal from the latch 260 into an analog pixel signal corresponding to any one of the gray voltages V1 and V10 in response to the inversion signal POL. The gray voltages V1 and V10 correspond to black color. That is, since the digital-to-analog converter 270 converts the analog pixel signal corresponding to any one of the gray voltages V1 and V10 according to the inversion signal POL, the digital-analog converter 270 is connected to the second data lines DA1 -DAm. The second pixels AP display black. In the present specification, the digital-to-analog converter 270 outputs an analog pixel signal corresponding to black, but the second pixel AP is input to the digital-to-analog converter 270 so that the second pixels AP are displayed in different colors as well as black. The gray voltages to be changed may be changed.

The data output buffer 250 stores the analog pixel signal output from the digital-analog converter 340 and supplies the same to the second data lines DA1-DAm of the liquid crystal panel in synchronization with the latch signal TP. For example, the latch 260 outputs the pixel data signal from the data register 220 to the digital-to-analog converter 270 at the rising edge of the latch signal TP, and the second output buffer 280 The output of the digital-analog converter 270 is transferred to the second data lines DA1-DAm at the falling edge of the latch signal TP.

3 is a timing diagram of signals used in the liquid crystal display device 100 according to an exemplary embodiment of the present invention, and FIGS. 4A to 4C illustrate first to third frames Fa, Fb, and Fc illustrated in FIG. 3. ) Shows an image displayed on the liquid crystal panel 140. In the example shown in FIGS. 4A to 4C, the number of gate lines of the liquid crystal panel 140 is 1080 * 2.

The vertical synchronization start signal STVA is activated 1/2 frame before the vertical synchronization start signal STVD. The gate driver 120 sequentially scans the second gate lines GD1-GDn in response to the vertical synchronization start signal STVA and the gate clock signal CPVA.

As shown in FIG. 4A, the second pixels AP connected to the second gate lines GA1 to GA540 in the liquid crystal panel 140 are sequentially driven to black during the first frame Fa and the remaining pixels. Are not driven.

As shown in FIG. 4B, the second pixels AP connected to the second gate lines GA541 to GA1080 in the liquid crystal panel 140 are sequentially driven to black during the second frame Fb. The first pixels DP connected to the gate lines GD1 to GD540 are sequentially driven by the pixel data signal. That is, the first gate line GD1 is simultaneously driven when the second gate line GA541 is driven, and the first gate line GD2 is simultaneously driven when the second gate line GA542 is driven. In this manner, the second gate lines GA541 to GA1080 and the first gate lines GD1 to GD540 are simultaneously driven during the second frame Fb.

As illustrated in FIG. 4C, the second pixels AP connected to the second gate lines GA1 to GA540 in the liquid crystal panel 140 are sequentially driven to black during the third frame Fc. The first pixels DP connected to the gate lines GD541-GD1080 are sequentially driven by pixel data signals. That is, the first gate line GD541 is simultaneously driven when the second gate line GA1 is driven, and the first gate line GD542 is simultaneously driven when the second gate line GA2 is driven. In this manner, the second gate lines GA1 -GA540 and the first gate lines GD541-GD1080 are simultaneously driven during the third frame Fc.

FIG. 5 illustrates a change in luminance of a cathode ray tube (CRT) display, FIG. 6 illustrates a change in luminance of a general liquid crystal display, and FIG. 7 illustrates a change in luminance of a liquid crystal display according to an exemplary embodiment of the present invention. Giving.

As shown in FIG. 5, the CRT display device is suitable for displaying a moving image because the change in light intensity is fast. On the contrary, as shown in FIG. 6, the general liquid crystal display displays the same image for one frame, so that there is almost no change in luminance for one frame.

The liquid crystal display 100 according to the exemplary embodiment of the present invention uses the first pixel DP and the second pixel DA to display a 1-dot image. The first pixel DP displays a color corresponding to the pixel data signal, the second pixel AP displays black, and the first and second pixels DP and AP alternately at 1/2 frame intervals. Since it is driven, as shown in Fig. 7, impulsive driving is achieved. In other words, while the operating frequency of the liquid crystal display device 100 is maintained at 60 Hz, impulsive driving is implemented by doubling the number of pixels of the liquid crystal panel 140.

In the above, the configuration and operation of the circuit according to the present invention is shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications may be made without departing from the spirit of the present invention. to be.

According to the present invention, the operating frequency of the liquid crystal display is maintained at 60 Hz, but impulsive driving is realized by doubling the number of pixels of the liquid crystal panel. Therefore, the video quality of the liquid crystal display device is improved.

Claims (7)

A plurality of first gate lines; A plurality of first data lines disposed to intersect the first gate lines; A plurality of first pixels respectively disposed in regions defined by the first gate lines and the first data lines; A plurality of second gate lines alternated with the plurality of first gate lines; A plurality of second data lines intersecting the second gate lines and alternately arranged with the plurality of first data lines; A plurality of second pixels respectively disposed in regions defined by the second gate lines and the second data lines; A pixel data signal, a first vertical synchronization start signal and a first gate clock signal for driving the plurality of first gate lines, a second vertical synchronization start signal and a second gate clock for driving the plurality of second gate lines A timing controller for generating signals and control signals; A gate driver sequentially driving the plurality of first gate lines and the plurality of second gate lines in response to the first and second vertical synchronization start signals and the first and second gate clock signals; And And a data driver driving the data lines in response to the control signals. The method of claim 1, And the second vertical synchronization start signal is activated before the second vertical synchronization start signal. The method of claim 2, And the second vertical synchronizing start signal is activated 1/2 frame before the second vertical synchronizing start signal. The method of claim 1, And the first pixels are driven to display a color corresponding to the pixel data signal, and the second pixels are driven to display black. The method of claim 1, The source driver, A first circuit driving the plurality of first data lines in response to the pixel data signal and the control signals; And And a second circuit for driving the plurality of second data lines with a signal corresponding to a first color in response to the pixel data signal and the control signals. The method of claim 5, And the second circuit drives the plurality of second data lines to a signal corresponding to black in response to the pixel data signal and the control signals. The method of claim 5, The second circuit, A latch for latching the pixel data signal; And And a digital-to-analog converter for converting the digital pixel data signal output from the latch into an analog pixel data signal corresponding to black color.

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