KR20070078566A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
KR20070078566A
KR20070078566A KR1020060008953A KR20060008953A KR20070078566A KR 20070078566 A KR20070078566 A KR 20070078566A KR 1020060008953 A KR1020060008953 A KR 1020060008953A KR 20060008953 A KR20060008953 A KR 20060008953A KR 20070078566 A KR20070078566 A KR 20070078566A
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South Korea
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gate
dummy pattern
semiconductor device
edge portion
active region
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KR1020060008953A
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Korean (ko)
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윤훈상
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주식회사 하이닉스반도체
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Priority to KR1020060008953A priority Critical patent/KR20070078566A/en
Publication of KR20070078566A publication Critical patent/KR20070078566A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to prevent an edge of a gate pattern from being damaged by further forming a dummy pattern for chemical mechanical polishing and a falling prevention tap. A semiconductor device includes a gate(120) formed on an edge of a wafer, in which the gate has a line width of 295nm or less and a length of 1000nm or more. Dummy patterns(140) are arranged in a direction parallel with a longitudinal direction of the gate at a periphery of an active region(110). The dummy patterns are formed on both sides of the active region so that the dummy patterns are ended at the same line as an end of the gate.

Description

반도체 소자의 형성 방법{METHOD FOR FORMING SEMICONDUCTOR DEVICE}Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

도 1은 동일 크기의 게이트를 형성하는데 있어서 게이트 선폭의 차이가 발생하는 것을 나타내는 비교 사진들.1 is a comparison picture showing that a difference in gate line width occurs in forming gates of the same size.

도 2는 웨이퍼의 에지부에 형성되는 게이트의 레이아웃을 도시한 개략도.2 is a schematic diagram showing a layout of a gate formed in an edge portion of the wafer.

도 3은 웨이퍼의 에지부에 형성된 실제 게이트 패턴을 나타낸 평면 사진.3 is a planar photograph showing the actual gate pattern formed on the edge of the wafer.

도 4는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 평면도.4 is a plan view showing a method of forming a semiconductor device according to the present invention.

도 5는 본 발명에 따른 CMP 더미 패턴을 도시한 평면도.5 is a plan view showing a CMP dummy pattern according to the present invention.

도 6 및 도 7은 더미 패턴의 쓰러짐 방지용 탭을 도시한 평면도들.6 and 7 are plan views showing the collapse preventing tab of the dummy pattern.

본 발명은 반도체 소자의 형성 방법에 관한 것으로서, 웨이퍼의 에지부에 형성되는 게이트의 에지부가 손상되는 문제를 해결하기 위하여, 웨이퍼의 에지부에 형성되는 게이트 양측에 소정의 더미 패턴들을 형성하되 그 위치 및 길이 관계를 특정하고 CMP용 더미 패턴 및 쓰러짐 방지용 탭을 더 형성함으로써, 게이트 패턴의 에지부가 손상되는 것을 방지하고, 반도체 기판의 토폴로지(Topology) 차이를 최소화 할 수 있는 발명에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In order to solve a problem in which an edge portion of a gate formed at an edge portion of a wafer is damaged, predetermined dummy patterns are formed on both sides of a gate formed at an edge portion of a wafer, and And specifying a length relationship and further forming a dummy pattern for CMP and a tab for preventing collapse, thereby preventing the edge portion of the gate pattern from being damaged and minimizing the topology difference of the semiconductor substrate.

도 1은 동일 크기의 게이트를 형성하는데 있어서 게이트 선폭의 차이가 발생하는 것을 나타내는 비교 사진들이다.FIG. 1 is a comparison photograph illustrating that a difference in gate line width occurs in forming gates of the same size.

도 1을 참조하면, 동일한 크기의 게이트를 형성하는 경우에 있어서 노광 위치 및 웨이퍼 내의 토폴로지 차에 의해 게이트의 선폭이 다르게 형성된다는 것을 알 수 있다. 주변에 형성된 패턴들의 차이에 따라서 게이트 선 폭이 102.2 ~ 133.5nm 까지 차이를 나타낸다.Referring to FIG. 1, it can be seen that when the gates having the same size are formed, the line widths of the gates are formed differently according to the exposure position and the topology difference in the wafer. The gate line width varies from 102.2 to 133.5 nm according to the difference in the patterns formed around the periphery.

도 2는 웨이퍼의 에지부에 형성되는 게이트의 레이아웃을 도시한 개략도이다.2 is a schematic diagram showing a layout of a gate formed in an edge portion of the wafer.

도 2를 참조하면, 반도체 기판(10)의 활성영역(15)을 지나는 게이트(20)가 형성된다. 이때, 웨이퍼의 에지부에 형성되는 게이트(20)는 그 주변에 다른 구조물들이 없기 때문에 토폴로지 차이에 의해서 게이트(20)의 에지부인 "A" 영역이 손상되는 문제가 있다.Referring to FIG. 2, a gate 20 passing through the active region 15 of the semiconductor substrate 10 is formed. At this time, since the gate 20 formed at the edge of the wafer has no other structures in the periphery thereof, there is a problem that the “A” region, which is the edge of the gate 20, is damaged by the topology difference.

도 3은 웨이퍼의 에지부에 형성된 실제 게이트 패턴을 나타낸 평면 사진이다.3 is a planar photograph showing an actual gate pattern formed at an edge portion of a wafer.

도 3을 참조하면 도 2의 "A" 영역과 대응되는 "B" 영역에 게이트가 형성되지 않은 것을 알 수 있다. Referring to FIG. 3, it can be seen that no gate is formed in region “B” corresponding to region “A” of FIG. 2.

상술한 바와 같이, 웨이퍼의 에지부에 형성되는 게이트는 주변의 패턴 상황에 따라서 토폴로지가 변화하고 게이트가 손상되고 반도체 소자의 전기적 특성이 열화되는 문제가 발생할 수 있다. 따라서 반도체 소자의 형성 공정 마진이 감소하고, 수율이 감소하는 문제가 있다.As described above, the gate formed in the edge portion of the wafer may have a problem that the topology changes according to the surrounding pattern situation, the gate is damaged, and the electrical characteristics of the semiconductor device are degraded. Therefore, there is a problem that a process margin of forming a semiconductor device decreases and a yield decreases.

본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 웨이퍼의 에지부에 형성되는 게이트 양측에 소정의 더미 패턴들을 형성하되 그 위치 및 길이 관계를 특정하고 CMP용 더미 패턴 및 쓰러짐 방지용 탭을 더 형성함으로써, 게이트 패턴의 에지부가 손상되는 것을 방지하고, 반도체 기판의 토폴로지 차이를 최소화 할 수 있는 반도체 소자의 형성 방법을 제공하는 것을 그 목적으로 한다.The present invention is to solve the above problems, by forming a predetermined dummy pattern on both sides of the gate formed in the edge portion of the wafer, specifying the position and length relationship, and further forming a dummy pattern for CMP and a fall prevention tab It is an object of the present invention to provide a method for forming a semiconductor device which can prevent the edge portion of the gate pattern from being damaged and minimize the difference in topology of the semiconductor substrate.

본 발명은 상기와 같은 목적을 달성하기 위한 것으로서, 본 발명에 따른 반도체 소자의 형성 방법은,The present invention is to achieve the above object, the method of forming a semiconductor device according to the present invention,

웨이퍼의 에지부에 형성되는 게이트의 선폭이 295nm 이하이며, 게이트의 길이가 1000nm 이상인 반도체 소자에 있어서,In a semiconductor device in which the line width of the gate formed in the edge portion of the wafer is 295 nm or less, and the gate length is 1000 nm or more,

상기 게이트가 형성되는 활성영역의 외측에 상기 게이트의 길이 방향과 평행한 방향으로 배열되는 라인 타입의 더미 패턴을 형성하되,On the outside of the active region where the gate is formed to form a dummy pattern of the line type arranged in a direction parallel to the longitudinal direction of the gate,

상기 더미 패턴은 상기 게이트의 끝부분과 동일한 선상에서 끝나도록 형성하며, 상기 활성영역의 양측에 각각 0 ~ 2개만큼 형성하는 것을 특징으로 한다.The dummy patterns may be formed on the same line as the ends of the gates, and 0 to 2 dummy patterns may be formed on both sides of the active region.

여기서, 상기 더미 패턴의 에지부에 쓰러짐 방지용 탭을 더 형성하고, 상기 더미 패턴의 외측에 CMP용 더미패턴을 더 형성하고, 상기 더미 패턴의 선폭은 150 ~ 250nm이며, 상기 활성영역의 경계로부터 0.08 ~ 0.20nm의 거리만큼 이격시켜 형성하고, 상기 더미 패턴 간의 간격은 200 ~ 300nm이 되도록 형성하는 것을 특징으로 한다.Here, a fall prevention tab is further formed at an edge portion of the dummy pattern, and a dummy pattern for CMP is further formed outside the dummy pattern, and the line width of the dummy pattern is 150 to 250 nm, and 0.08 from the boundary of the active region. It is formed to be spaced apart by a distance of ~ 0.20nm, characterized in that the gap between the dummy pattern is formed to be 200 ~ 300nm.

도 4는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 평면도이다.4 is a plan view illustrating a method of forming a semiconductor device according to the present invention.

도 4를 참조하면, 웨이퍼의 에지부에 형성되는 게이트(120)의 활성영역(110)의 외측에 게이트(120)의 길이 방향과 평행한 방향으로 배열되는 라인 타입의 더미 패턴(140)이 형성된다. 이때, 더미 패턴(140)은 게이트(120)의 끝부분과 동일한 선상에서 끝나도록 형성하며, 활성영역(110)의 양측에 각각 0 ~ 2개만큼 형성하는 것이 바람직하다.Referring to FIG. 4, a dummy pattern 140 of a line type is formed outside the active region 110 of the gate 120 formed at the edge of the wafer in a direction parallel to the longitudinal direction of the gate 120. do. In this case, the dummy patterns 140 may be formed to end on the same line as the end of the gate 120, and 0 to 2 dummy patterns 140 may be formed on both sides of the active region 110, respectively.

여기서, 더미 패턴(140)의 선폭은 150 ~ 250nm이며, 활성영역(110)의 경계로부터 0.08 ~ 0.20nm의 거리만큼 이격시켜 형성하고, 더미 패턴(120)들 간의 간격은 200 ~ 300nm이 되도록 형성 한다. 이와 같이, 각 더미 패턴(140)들은 게이트(120)의 에지부를 보호할 수 있는 길이만큼 형성되므로 CMP 공정이나 에치백 공정에서 게이트(120)의 에지부가 식각되어 게이트(120)의 길이가 짧아지는 것을 방지한다.In this case, the line width of the dummy pattern 140 is 150 to 250 nm, and is formed to be separated from the boundary of the active region 110 by a distance of 0.08 to 0.20 nm, and the gap between the dummy patterns 120 is formed to be 200 to 300 nm. do. As such, each dummy pattern 140 is formed to have a length to protect the edge portion of the gate 120, so that the edge portion of the gate 120 is etched in the CMP process or the etch back process to shorten the length of the gate 120. To prevent them.

도 5는 본 발명에 따른 CMP 더미 패턴을 도시한 평면도이다.5 is a plan view illustrating a CMP dummy pattern according to the present invention.

도 5를 참조하면, 더미 패턴(140)의 선폭이 게이트(120)의 선폭보다 작게 형성되기 때문에 CMP 공정에 의해서 쓰러지는 문제가 발생할 수 있으므로, 이를 방지하기 위하여 CMP용 더미 패턴(150)을 더 형성한다. 이때, 더미 패턴(140)과 CMP용 더미 패턴(150)의 간격은 0.11 ~ 0.88㎛인 것이 바람직하다. Referring to FIG. 5, since the line width of the dummy pattern 140 is smaller than the line width of the gate 120, a problem of falling by the CMP process may occur, so that the dummy pattern 150 for the CMP is further formed to prevent this. do. At this time, the gap between the dummy pattern 140 and the dummy pattern 150 for CMP is preferably 0.11 ~ 0.88㎛.

도 6 및 도 7은 더미 패턴의 쓰러짐 방지용 탭을 도시한 평면도들이다.6 and 7 are plan views illustrating the collapse preventing tabs of the dummy pattern.

더미 패턴(140)의 에지부가 손상되는 것을 방지하고, 쓰러짐 현상을 방지하기 위하여, 더미 패턴(140)의 에지부에 쓰러짐 방지용 탭(160, 170)을 더 형성한다. 이때, 쓰러짐 방지용 탭(160, 170)은 도 6에서와 같은 스페이스 패턴(160)이나 도 7에서와 같은 노치(Notch) 패턴(170)으로 형성하는 것이 바람직하다.In order to prevent the edge portion of the dummy pattern 140 from being damaged and to prevent a fall phenomenon, the fall prevention tabs 160 and 170 are further formed on the edge portion of the dummy pattern 140. At this time, the fall prevention tabs 160 and 170 may be formed of the space pattern 160 as shown in FIG. 6 or the notch pattern 170 as shown in FIG. 7.

상술한 바와 같이, 반도체 소자의 형성 공정에서 웨이퍼의 에지부분에 형성되는 게이트의 길이가 짧아지는 문제를 해결하기 위하여 소정의 더미 패턴들을 형성하되 그 위치 및 길이 관계를 특정하고 CMP용 더미 패턴 및 쓰러짐 방지용 탭을 더 형성함으로써 반도체 소자의 형성 공정 마진을 향상시킬 수 있다.As described above, in order to solve the problem of shortening the length of the gate formed on the edge of the wafer in the process of forming a semiconductor device, predetermined dummy patterns are formed, and the position and length relationship are specified, and the dummy pattern and collapse for CMP are formed. By further forming a tab for prevention, the margin of the formation process of the semiconductor element can be improved.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 형성 방법은 웨이퍼의 에지부에 형성되는 게이트 양측에 소정의 더미 패턴들을 형성하되 그 위치 및 길이 관계를 특정하고 CMP용 더미 패턴 및 쓰러짐 방지용 탭을 더 형성함으로써, 게이트 패턴의 에지부가 손상되는 것을 방지하고, 반도체 기판의 토폴로지(Topology) 차이를 최소화 하여 반도체 소자의 특성을 향상시키고, 반도체 소자의 형성 공정 마진을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming a semiconductor device according to the present invention, predetermined dummy patterns are formed on both sides of a gate formed at an edge of a wafer, and the position and length relationship thereof are specified, and a dummy pattern for CMP and a tap for preventing collapse are formed. By further forming, the edge portion of the gate pattern can be prevented from being damaged, the difference in topology of the semiconductor substrate can be minimized, thereby improving the characteristics of the semiconductor device and improving the process margin of the semiconductor device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (5)

웨이퍼의 에지부에 형성되는 게이트의 선폭이 295nm 이하이며, 게이트의 길이가 1000nm 이상인 반도체 소자에 있어서,In a semiconductor device in which the line width of the gate formed in the edge portion of the wafer is 295 nm or less, and the gate length is 1000 nm or more, 상기 게이트가 형성되는 활성영역의 외측에 상기 게이트의 길이 방향과 평행한 방향으로 배열되는 라인 타입의 더미 패턴을 형성하되,On the outside of the active region where the gate is formed to form a dummy pattern of the line type arranged in a direction parallel to the longitudinal direction of the gate, 상기 더미 패턴은 상기 게이트의 끝부분과 동일한 선상에서 끝나도록 형성하며, 상기 활성영역의 양측에 각각 0 ~ 2개만큼 형성하는 것을 특징으로 하는 반도체 소자의 더미 패턴 형성 방법.The dummy pattern is formed so as to end on the same line as the end of the gate, the dummy pattern forming method for the semiconductor device, characterized in that formed on the both sides of the active region of 0 to 2 each. 제 1 항에 있어서,The method of claim 1, 상기 더미 패턴의 에지부에 쓰러짐 방지용 탭을 더 형성하는 것을 특징으로 하는 반도체 소자의 더미 패턴 형성 방법.A dummy pattern forming method of a semiconductor device, characterized in that the tab for preventing the fall further formed on the edge portion of the dummy pattern. 제 1 항에 있어서,The method of claim 1, 상기 더미 패턴의 외측에 CMP용 더미패턴을 더 형성하는 것을 특징으로 하는 반도체 소자의 더미 패턴 형성 방법.The dummy pattern forming method of a semiconductor device, characterized in that further forming a dummy pattern for CMP on the outside of the dummy pattern. 제 1 항에 있어서,The method of claim 1, 상기 더미 패턴의 선폭은 150 ~ 250nm이며, 상기 활성영역의 경계로부터 0.08 ~ 0.20nm의 거리만큼 이격시켜 형성하는 것을 특징으로 하는 반도체 소자의 더미 패턴 형성 방법.The line width of the dummy pattern is 150 to 250nm, and the dummy pattern forming method of the semiconductor device, characterized in that formed from a distance of 0.08 ~ 0.20nm from the boundary of the active region. 제 1 항에 있어서,The method of claim 1, 상기 더미 패턴 간의 간격은 200 ~ 300nm이 되도록 형성하는 것을 특징으로 하는 반도체 소자의 더미 패턴 형성 방법.The dummy pattern forming method of the semiconductor device, characterized in that the gap between the dummy pattern is formed to be 200 ~ 300nm.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100919805B1 (en) * 2007-10-26 2009-10-01 주식회사 하이닉스반도체 Semiconductor memory device and layout method therefor
KR100935198B1 (en) * 2008-03-27 2010-01-06 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8952423B2 (en) 2012-06-04 2015-02-10 Samsung Electronics Co., Ltd. Semiconductor device having decoupling capacitors and dummy transistors
US9129352B2 (en) 2012-08-30 2015-09-08 Samsung Electronics Co., Ltd. Optical proximity correction modeling method and system
US9557637B2 (en) 2013-11-19 2017-01-31 Samsung Electronics Co., Ltd. Method of designing patterns of semiconductor devices in consideration of pattern density

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100919805B1 (en) * 2007-10-26 2009-10-01 주식회사 하이닉스반도체 Semiconductor memory device and layout method therefor
KR100935198B1 (en) * 2008-03-27 2010-01-06 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8952423B2 (en) 2012-06-04 2015-02-10 Samsung Electronics Co., Ltd. Semiconductor device having decoupling capacitors and dummy transistors
US9129352B2 (en) 2012-08-30 2015-09-08 Samsung Electronics Co., Ltd. Optical proximity correction modeling method and system
US9557637B2 (en) 2013-11-19 2017-01-31 Samsung Electronics Co., Ltd. Method of designing patterns of semiconductor devices in consideration of pattern density

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