KR20070077520A - Column address decoder - Google Patents

Abstract

A column address decoder is provided to prevent current loss due to an unnecessary column address decoding operation by removing unnecessary operation of a circuit in a column address path according to a data output mode. An I/O(Input/Output) selector(130) generates an I/O selection signal for selecting one of a plurality of I/O tools by receiving a data mode signal and an I/O selection data signal. A column address enable controller(140) generates a decoder selection signal by receiving/logically operating the I/O selection signal and a column address enable signal received from the outside. A column address decoding part(160) includes a plurality of decoders, and decodes a column address by receiving a decoder selection signal and the column address from the outside, and operating the decoder corresponding to the decoder selection signal. The column address enable controller performs an AND operation between the I/O selection signal and the column address enable signal.

Description

Column Address Decoder

1 is a diagram illustrating an input / output configuration of a general semiconductor memory device;

2 is a diagram illustrating a conventional column address block diagram;

3 is a timing diagram illustrating an X4 mode operation in the column address block diagram of FIG. 2;

4 is a diagram illustrating a column address block diagram according to an embodiment of the present invention;

5 is a diagram illustrating a column address enable control unit of FIG. 4;

6 is a diagram illustrating the column address decoder of FIG. 4;

7 is a timing diagram illustrating an X4 mode operation in the column address block diagram of FIG. 4.

The present invention relates to a column address decoder, and more particularly, to a column address decoder for connecting a bit line and a data line during a read or write operation in a semiconductor memory.

1 is a diagram illustrating an input / output configuration of a general semiconductor memory device. Referring to FIG. 1, a general semiconductor memory device includes a memory cell array and a means for selecting a memory cell CELL belonging to the cell array to read / write necessary information.

In order to input and output data to and from the memory cell CELL, the word line is enabled by a word line (WL) decoded word line (WL) selection signal, and the data stored in the cell CELL is stored in the bit line ( It is amplified by BLSA (Bit Line Sense Amp.) On a BL (Bit Line).

The data signal is transferred to the memory cell CELL selected by the bit line selection signal Yi, which decodes the column address, to the main amplifier / write driver and the data input / output buffer. Input / Output through Out Buffer).

One input / output pad should be connected to input and output of one or more main amplifiers / light drivers. A multiplexer allows a main amplifier / light driver to be commonly used for multiple input / output pads.

The main amplifier / light driver may be selected by an input / output selection controller (not shown). The input / output selection control unit receives a data mode, a test mode, an input / output selection signal, and a read / write selection signal to select a main amplifier / light driver.

2 is a diagram illustrating a conventional column address block diagram. Referring to FIG. 2, a conventional column address block receives CA <11> and CA <13> as input / output selection signals and receives X16, X8, and X4 as data modes.

Table 1 below shows a case where a conventional input / output selection controller selects a main amplifier and a decoder by receiving data modes X16, X8, and X4 and input / output selection signals CA <11> and CA <13>.

Data mode I / O selector output signal Selected main amplifier Decoder output signal X4 X8 X16 CA <11>: LOW CA <13>: LOW CA <13>: LOW CA <11>, CA <13> DON'T CARE AYIOS <0> MA1,2,3,4 Yi_L <0: 255> CA <11>: HIGH CA <13>: LOW CA <13>: HIGH CA <11>, CA <13> DON'T CARE AYIOS <1> MA8,9,10,11 CA <11>: LOW CA <13>: HIGH CA <13>: LOW CA <11>, CA <13> DON'T CARE AYIOS <2> MA5,6,7,8 Yi_R <0: 255> CA <11>: HIGH CA <13>: HIGH CA <13>: HIGH CA <11>, CA <13> DON'T CARE AYIOS <3> MA12,13,14,15

Referring to Table 1, the conventional column address block uses an input / output selection signal to operate the main amplifier / light driver used for input / output when the data mode is X4 or X8. Prevent operation.

However, since the decoder of the conventional column address block is not selected by a separate control circuit unlike the main amplifier / write driver, the decoders on the left and right sides always operate simultaneously. In particular, if the output signal of the input / output selector is AYISO <0> in the X4 data mode, the main amplifier operates only the selected main amplifiers MA1, 2, 3, and 4, but the decoder operates not only the left decoder but also the right decoder.

Figure 3 shows the operation of this conventional column address block in a timing diagram. Referring to FIG. 3, when AYISO <0> of the output signals of the input / output selector is enabled, not only the output signal LAY_L <i> of the predecoder and the output signal Yi_L <i> of the left decoder, but also the output signal LAY_R of the predecoder. It can be seen that the <i> and the output signal Yi_R <i> of the right decoder are enabled and the right decoder in which the main amplifier does not operate is unnecessary.

That is, the conventional column address block has an unnecessary current consumption because it performs an unnecessary operation such as decoding to select a bit line to which data is not inputted or outputted in the X4 mode operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object thereof is to eliminate unnecessary operation of a circuit existing in a column address path according to a data output mode.

In order to achieve the above object, the present invention includes a column address enable control unit and a plurality of decoders to generate and output a decoder selection signal by performing a logical operation on the input / output selection signal and the column address enable signal, wherein the decoder selection signal and the external And a column address decoder to receive the column address from the decoder and to decode the column address by operating a decoder corresponding to the decoder selection signal.

Herein, the column address enable control unit ANDs the input / output selection signal and the column address enable signal.

The present invention may further include an input / output selection unit configured to receive a data mode signal and an input / output selection data signal from an external source and generate an input / output selection signal for selecting one input / output unit among the plurality of input / output means.

The data mode signal may be a signal indicating an X4 mode through which data is input and output in units of 4 bits.

In addition, it is preferable that the input / output means is any one of a main amplifier and a write driver.

The input / output selection data signal may indicate n states, and the input / output means may be grouped into 2 ⁿ groups.

The column address decoder may include a predecoder that decodes the decoder selection signal and a column address to generate a predecoded signal, and a decoder that receives the decoded signal and decodes the bit decoded signal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a column address block diagram according to an embodiment of the present invention. As shown in FIG. 4, a column address block according to an embodiment of the present invention includes a cell array unit 110, a main amplifier / write driver unit 120, an input / output selection unit 130, and a column address enable control unit ( 140, a predecoder unit 150, and a decoder unit 160.

The cell array unit 110 includes a word line (WL), a bit line (BL), and a memory cell. The memory cells belonging to the cell array unit 110 include the word line selection signal and the bit line selection signals Yi_0 <0: 127>, Yi_1 <0: 127>, Yi_2 <0: 127>, which are output signals of the decoder 160. Yi_3 <0: 127>). In the present embodiment, the cell array unit 110 exemplifies a cell array unit corresponding to one quarter of one bank.

The main amplifier / write driver unit 120 includes a plurality of main amplifiers and a plurality of write drivers, and functions to input and output data to memory cells selected by a word line selection signal and a bit line selection signal.

The main amplifier / light driver unit 120 preferably includes a multiplexer (not shown). The multiplexer receives the input / output selection signals AYIOS <0: 3> from the input / output selection unit 130 and operates the main amplifier / light driver corresponding to the input / output selection signals AYIOS <0: 3> to operate the main amplifier or the amplifier. Select the light driver.

In one embodiment of the present invention, the plurality of main amplifiers MA1, 2, 3 and 4; MA8, 9, 10 and 11 corresponding to the left cell array unit and the main amplifier MA5 corresponding to the right cell array unit. For example, four groups of 6, 7, 8, and MA12, 13, 14, and 15 are illustrated. A plurality of light drivers (not shown) may also be arranged together with the main amplifier.

The input / output selection unit 130 receives a data mode signal, an input / output selection data signal, a read / write selection signal, and the like to generate an input / output selection signal AYIOS <0: 3>, and thus, the main amplifier / light driver unit 120. Select the main amplifier or the light driver to operate from the included main amplifier or the light driver.

In this case, the data mode signal refers to a width of data carried on an I / O bus. The data mode may be X16, X8, or X4 mode. In X 16 mode, 16 I / O pins are used to input and output 16 bit data. In X8 mode, 8 I / O pins are used to input and output 8 bit data. In X4 mode, 4 I / O pins are used to input and output 4 bit data. do.

In addition, the input / output selection data signal selects the main amplifier or the light driver included in the main amplifier / light driver unit 120. In the present embodiment, the input / output selection data signal is described by exemplifying the case of the column addresses CA <11> and CA <13>.

In addition, the read / write selection signal is displayed as a read when outputting data from the memory cell, and a write when a data is inputted to the memory cell. If the read / write selection signal is a lead, the input / output selection unit 130 selects the main amplifier from the main amplifier / light driver unit 120, and if the read / write selection signal is write, the input / output selection unit 130 is the main amplifier / Preferably, the write driver 120 is configured to select a write driver.

The column address enable control unit 140 receives an input / output selection signal AYOIOS <0: 3> and a column address enable signal YAE of the input / output selection unit 130 and a decoder selection signal YAED <0: 3>. ) Is output to the predecoder unit 150.

The predecoder 150 receives the decoder selection signals YAED <0: 3> and the column addresses CA <2: 9> of the column address enable control 140 and predecodes the signals LAY_0 <0: 3>, LAY_1 <0: 3>, LAY_2 <0: 3>, and LAY_3 <0: 3>) are generated and output to the decoder unit 160.

The decoder 160 receives the output signal of the predecoder 150 and receives the bit line selection signals Yi_0 <0: 127>, Yi_1 <0: 127>, Yi_2 <0: 127>, and Yi_3 <0: 127. >) Is generated and output to the cell array unit 110. The decoder unit 160 supplies first and second decoders and right cell arrays to supply bit line selection signals Yi_0 <0: 127> and Yi_1 <0: 127> to the left cell array of the cell array unit 110. And third and fourth decoders for supplying bit line selection signals Yi_2 <0: 127> and Yi_3 <0: 127> to the unit.

FIG. 5 is a diagram illustrating the column address enable control unit of FIG. 4. FIG. As shown in FIG. 5, the column address enable controller 140 receives and inputs each of the input / output selection signals AYIOS <0: 3> and the column address enable signal YAE of the input / output selector 130. And a plurality of AND gates AND1, AND2, AND3, and AND4.

The AND gate AND1, AND2, AND3, and4 generates an decoder selection signal YAED <0: 3> by performing an AND operation on the input / output selection signal AYIOS <0: 3> and the column address enable signal YAE. Output to the predecoder unit 150.

FIG. 6 is a diagram illustrating the column address decoder of FIG. 4. As shown in FIG. 6, the column address decoder includes a predecoder unit 150 and a decoder unit 160.

The predecoder 150 receives the decoder selection signals YAED <0: 3> and the column addresses CA <2: 3> of the column address enable control 140 and predecodes the signals LAY_0 <0: 3. >, LAY_1 <0: 3>, LAY_2 <0: 3>, LAY_3 <0: 3>, and the first, second, third and fourth predecoder and column addresses (CA <4: 9>) And a fifth predecoder configured to receive and predecode the signal.

The decoder unit 160 may respectively pre-decode signals LAY_0 <0: 3>, LAY_1 <0: 3>, LAY_2 <0: 3>, and LAY_3 <0: 3> of the predecoder unit 150 and the fifth pre-decode. It includes a first, second, third and fourth decoder to receive and decode the pre-decoded signal of the decoder. The first, second, third, and fourth decoders decode the decoded bit line selection signals Yi_0 <0: 127>, Yi_1 <0: 127>, Yi_2 <0: 127>, Yi_3 <0: 127>. Output to the array unit 110.

Since the column address decoder of the present embodiment includes four decoders capable of selecting 128 bit lines per quarter bank cell array unlike the conventional method, the column address decoder selects one of four decoders using the I / O selection signal of the I / O selection unit during X4 mode operation. It has a structure that can only operate decode.

Hereinafter, an operation of the column address decoder according to an embodiment of the present invention will be described.

Table 2 shows a case in which the column address decoder according to an embodiment of the present invention selects the operation decoder according to the data mode. Here, CA <11> and CA <13> are input / output selection data signals input to an input / output selection unit.

Data mode I / O selection signal Selected main amplifier Bit line select signal X4 X8 X16 CA <11>: LOW CA <13>: LOW CA <13>: LOW CA <11>, CA <13> DON'T CARE AYIOS <0> MA1,2,3,4 Yi_0 <0: 127> CA <11>: HIGH CA <13>: LOW CA <13>: HIGH CA <11>, CA <13> DON'T CARE AYIOS <1> MA8,9,10,11 Yi_1 <0: 127> CA <11>: LOW CA <13>: HIGH CA <13>: LOW CA <11>, CA <13> DON'T CARE AYIOS <2> MA5,6,7,8 Yi_2 <0: 127> CA <11>: HIGH CA <13>: HIGH CA <13>: HIGH CA <11>, CA <13> DON'T CARE AYIOS <3> MA12,13,14,15 Yi_3 <0: 127> Z

Referring to Table 2, when the data mode is X4, the column address decoder selects the operation decoder according to the state of the input / output selection signals CA <11> and CA <13> of the input / output selection unit. do.

When the input / output selection signals CA <11> and CA <13> are 'LOW' and 'LOW', the input / output selection unit 130 enables the AYIOS <0> input / output selection signal. The column address enable control unit 140 performs an AND operation on the input AYIOS <0> input / output selection signal and the column address enable signal to enable the YAED <0> decoder selection signal.

The predecoder 1500 outputs the input YAED <0> decoder selection signal and the LAY_0 <0> pre decoding signal obtained by pre-decoding the CA <2: 3> column address to the decoder 160. The decoder 160 The decoder generates a Yi_0 <0: 127> bit line selection signal by operating a decoder (first decoder) corresponding to the received LAY_0 <0> pre-decoded signal and outputs the bit line selection signal to the cell array unit 110.

That is, since the column decoder according to an embodiment of the present invention can operate only the decode selected from the four decoders by using the input / output selection signal of the input / output selection unit during the X4 mode operation, data is not inputted or outputted during the X4 mode operation. The problem of performing an unnecessary operation such as decoding to select a bit line is solved.

7 is a timing diagram illustrating an X4 mode operation in the column address block diagram of FIG. 4. As shown in FIG. 7, when the AYIOS <0> input / output selection signal of the output signals of the input / output selection unit is enabled, the YAED <0> decoder selection signal is enabled, and the LAY_0 <i corresponding to the YAED <0> decoder selection signal. The pre-decoded signal and the Yi_0 <i> decoded signal are enabled to operate the first decoder. At this time, other LAY_1 <i>, LAY_2 <i>, LAY_3 <i> pre-decoded signals, and Yi_1 <i>, Yi_2 <i>, Yi_3 <i> decoded signals are disabled.

Therefore, since the column address decoder according to an embodiment of the present invention can operate only one 128 decoder selected by using the input / output selection signal in the X4 mode operation, the decoder that does not input or output data in the X4 mode operation as in the prior art operates. The problem is solved.

In the X4 mode operation, AYIOS <1>, AYIOS <2>, and AYIOS <3> are enabled, respectively, so that the second, third, and fourth decoders are selected and operated. Since the first decoder is selected and operated in the same manner, detailed description thereof will be omitted.

As described above, the column address decoder of the present invention can eliminate unnecessary operation of the circuit existing in the column address path according to the data output mode, thereby preventing the loss of current due to unnecessary column address decoding operation. There is.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (17)

A column address enable controller configured to perform a logical operation on the input / output selection signal and the column address enable signal to generate and output a decoder selection signal; And A column address decoder including a plurality of decoders, the column address decoder unit receiving the decoder selection signal and a column address from the outside to decode the column address by operating a decoder corresponding to the decoder selection signal; Column address decoder comprising a. The method of claim 1, wherein the column address enable control unit ANDing the input / output selection signal and the column address enable signal Column address decoder. The method of claim 1, And an input / output selection unit configured to receive an input of a data mode signal and an input / output selection data signal from an external source and generate an input / output selection signal for selecting one of the plurality of input / output means. Column address decoder. The data mode signal of claim 3, wherein the data mode signal is a signal indicating an X4 mode in which data is input and output in units of 4 bits. Column address decoder. 4. The input / output means according to claim 3, wherein the input / output means is one of a main amplifier and a write driver. Column address decoder. The method of claim 3, wherein the input / output selection data signal indicates n states, and the input / output means are grouped into 2 ⁿ groups. Column address decoder. The method of claim 1, wherein the column address decoder unit A predecoder unit for decoding the decoder selection signal and the column address to generate a predecoded signal; A decoder configured to receive the pre-decoded signal, decode the signal, and output the decoded signal as a bit line selection signal; Column address decoder. The method of claim 7, wherein the pre decoder unit And a plurality of predecoder, wherein a predecoder selected by the decoder selection signal is operated to predecode the column address. Column address decoder. The method of claim 8, wherein the decoder unit And a plurality of decoders respectively receiving output signals of the plurality of pre decoders, wherein a decoder receiving the output signals of the pre decoders operates to decode the output signals of the pre decoder unit. Column address decoder. A column address decoder of a semiconductor memory device comprising a memory cell array and a plurality of input / output means for performing data input / output with respect to a memory cell selected by a word line and a bit line of the memory cell array; An input / output selection unit configured to receive a data mode signal and an input / output selection data signal and generate an input / output selection signal for selecting one of the plurality of input / output means; A column address enable control unit configured to receive the input / output selection signal and a column address enable signal from an external source and perform a logical operation to generate a decoder selection signal; A column address decoder comprising a plurality of decoders, the column address decoder unit receiving the decoder selection signal and a column address from the outside and operating the decoder selected by the decoder selection signal to decode the column address; Column address decoder comprising a. The method of claim 10, wherein the column address enable control unit ANDing the input / output selection signal and the column address enable signal Column address decoder. The data mode signal of claim 10, wherein the data mode signal is a signal indicating an X4 mode in which data is input and output in units of 4 bits. Column address decoder. 11. The apparatus of claim 10, wherein the input / output means is any one of a main amplifier and a write driver. Column address decoder. 11. The apparatus of claim 10, wherein the input / output selection data signal indicates n states, and the input / output means are grouped into 2 ⁿ groups. Column address decoder. The method of claim 10, wherein the column address decoder unit A predecoder unit for decoding the decoder selection signal and the column address to generate a predecoded signal; A decoder configured to receive the pre-decoded signal, decode the signal, and output the decoded signal as a bit line selection signal; Column address decoder. The method of claim 15, wherein the pre decoder unit And a plurality of predecoder, wherein a predecoder selected by the decoder selection signal is operated to predecode the column address. Column address decoder. The method of claim 16, wherein the decoder unit And a plurality of decoders respectively receiving output signals of the plurality of pre decoders, wherein a decoder receiving the output signals of the pre decoders operates to decode the output signals of the pre decoder unit. Column address decoder.

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