KR20070075083A - Semiconductor memory device and method of setting test mode using address pins - Google Patents

Abstract

A semiconductor memory test apparatus of setting a test mode using an address pin is provided to change a test pattern condition by changing a value of the address pin without entering an MRS(Mode Resistor Set) mode. A mode setting register sets the state of a code and a parallel bit test signal according to a mode setting register code applied from the outside in response to a mode setting command. At least one address pin is used for changing a test mode. A mode combination part combines a test mode address value determined by the value of the address pin and the mode setting register value. A test pattern circuit determines a test mode according to the combination result of the mode combination part.

Description

Semiconductor memory device and method of setting test mode using address pins}

1 is a diagram of a semiconductor memory test apparatus to which the present invention is applied;

2 illustrates a parallel bit test mode signal generation logic circuit using an address pin to implement the present invention;

3 is a table illustrating a result of a mode address signal according to a combination of an MMRS signal and an address pin illustrated in FIG. 2;

4A is a diagram of a first test signal combining a first mode address signal and a signal in a mode register setting unit according to a first embodiment of the present invention;

4B is a diagram of a second test signal in which a signal of a second mode address signal and a mode register setting unit are combined according to the first embodiment of the present invention;

5A is a diagram of a first test signal in which a signal of a first mode address signal and a mode register setting unit are combined according to a second embodiment of the present invention;

FIG. 5B is a diagram of a second test signal in which the second mode address signal and the signal in the mode register setting section are combined according to the second embodiment of the present invention. FIG.

* Brief description of symbols for the main parts of the drawings *

10, 20: first comparator 30: signal switching unit

40: second comparator I1, I2, I3, I4: inverter

TG1, TG2, TG3, TG4: Transmission Gate

The present invention relates to a semiconductor memory test, and more particularly, to a semiconductor memory test apparatus and a method for setting a test mode using an address pin.

Conventional semiconductor memory devices must set and input different mode register sets (hereinafter, referred to as 'MRS') codes for each test pattern in order to write the test pattern during the parallel bit test. .

If the conventional semiconductor memory device generates 4 bits of test pattern data internally in response to an MRS code applied from an external tester during parallel bit testing, a total of 16 4 bits of test pattern data are internally generated. If possible, external testers should have 16 different MRS codes to generate 16 test pattern data during parallel bit testing.

Due to this phenomenon, the number of MRS codes used for parallel bit testing of semiconductor memory devices is so large that there is a problem that the number of MRS codes to be used for other purposes is insufficient, and semiconductor memory devices such as DRAM in chip test or post-package test stages. There is a problem that must be tested in various test modes. Among the test modes, the passive mode is a test mode for testing a bit line bridge of a semiconductor memory device such as a DRAM. When a write operation is performed on a DRAM or the like, a data pattern is written into a cell and then read and read. This is tested by merging the data in the. In other words, testing a single cell or bit line unit requires a considerable time and cost to determine whether data on the bit line is normal. Thus, a cell or bit line test of a semiconductor memory device such as a DRAM is performed on all cells. Instead of testing, a data combination is performed by compressing the data by performing a logical combination of the data on the data line using a comparator composed of a logic circuit or the like.

In performing a write operation of a parallel bit test mode test on a semiconductor memory device, in order to detect various types of bit line bridges, various data patterns must be written in a memory cell such as a DRAM. That is, in cells where a word line and a column addressing signal line intersect among memory cell arrays of a general semiconductor memory device such as a DRAM, four data may be accessed by four bit line pairs. Therefore, a peripheral circuit having a data input of n should be implemented so that various data patterns can be freely written to at least four bit line pairs. In general, since a semiconductor memory device having a DQ configuration of X4, X8, and X16 has four or more DQ input / output node pins, data patterns vary over four or more bit line pairs when performing write operation in the passive mode. Can be lighted.

According to the Joint Electronic Device Engineering Council (JEDEC) standard, MRS has data to control various modes of memory, and depending on the value of MRS, CAS latency, burst length, burst sequence, test mode, DLL reset, vendor specific options The mode of operation is determined. However, to make the test screen more accurate, you should always write in various patterns and change the MRS to use different comparison logic. However, in order to change the MRS, it is possible under the condition that the DRAM remains in the precharge state.When precharging, the total test time is too long because the MRS must be newly set and the DRAM is tested with the newly set value. have.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and a first object of the present invention is to provide a semiconductor memory test apparatus for varying test pattern conditions using an address pin.

It is a second object of the present invention to provide a semiconductor memory test method for varying test pattern conditions using an address pin.

A semiconductor memory test apparatus for setting a test mode by using an address pin according to the present invention for achieving the above object, the state of the parallel bit test signal and the code according to the mode setting register code applied from the outside in response to the mode setting command A mode setting register for setting a; At least one address pin for changing a test mode; And a test pattern circuit including a mode combination unit that combines the mode setting register value and the test mode address value determined by the value of the address pin, wherein the test mode is determined according to the combination result of the mode combination unit.

The address pin is a pin that is not used as an address pin during a test.

The mode combination unit inputs a signal of the parallel bit test mode register set logic unit and a mode address signal, and outputs a test mode signal according to the value of the mode address signal without connecting the set logic unit when a test value is read. .

Alternatively, the mode combination unit inputs a signal of a parallel bit test mode register set logic unit and a mode address signal, and outputs a 'high' signal when both values of the signal are 'high' and either value is 'low'. If 'low' signal is output.

The mode address signal is configured to output 'high' when both the values of the parallel bit test mode register set logic and the address pin are 'high', and output 'low' when either of the values is 'low'. do.

In addition, the semiconductor memory test method for setting the test mode by using the address pin according to the present invention for achieving the above object comprises the steps of: generating a parallel bit test signal according to the mode setting register code in response to the mode register setting command; Setting a state of a code of a predetermined bit according to the mode setting register code in response to the mode setting command; Setting a test mode by combining a value of an address pin and a mode setting register code value; And testing the data with the corresponding test pattern when the test code is set.

In setting the test mode, the value of the address pin may be arbitrarily set by the tester.

The method further includes the step of entering the next test mode by the tester by adjusting the address pin value when any test mode is completed.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a diagram of a semiconductor memory test apparatus to which the present invention is applied. Referring to FIG. 1, a semiconductor memory test apparatus to which the present invention is applied writes test data to four memory cells of a semiconductor memory device and reads the written data from the four memory cells. The four read data FDO0 to FDO4 are input to the comparators 10 and 20 in pairs, respectively. That is, FDO0 and FDO1 are input to the comparator 10 and FDO2 and FDO3 are input to the comparator 20. In the present invention, the comparators 10 and 20 are implemented using an exclusive OR that outputs a high signal when two values are different from each other.

When both the PBT_MODE1 signal and the PBT_MODE2 signal are 'low' according to the mode register set (MRS) signal, the transmission gates TG1 and TG4 are inactivated and the transmission gates TG2 and TG3 are enabled. Output signals of the first first comparators 10 and 20 are transmitted to the second comparator 40 as an input signal of the first test mode.

In addition, the second comparator 40 performs an OR operation on the input signals of the first test mode transmitted by the transmission gates TG2 and TG3 and provides them as an output signal of the first test mode.

When the PBT_MODE1 signal is 'low' and the PBT_MODE2 signal is 'high' according to the mode register set (MRS) signal, the transmission gates TG1 and TG3 are inactivated and the transmission gates TG2 and TG4 are in the active state. The output signals of the two comparators 10 and 20 are transmitted to the second comparator 40 as an input signal of the second test mode.

In addition, the second comparator 40 performs an OR operation on the input signals of the second test mode transmitted by the transmission gates TG2 and TG4 and provides them as an output signal of the second test mode.

When the PBT_MODE1 signal is 'high' and the PBT_MODE2 signal is 'low' according to the mode register set (MRS) signal, the transmission gates TG2 and TG4 are inactive and the transmission gates TG1 and TG3 are in the active state. The output signals of the two comparators 10 and 20 are transmitted to the second comparator 40 as an input signal of the third test mode.

The second comparator 40 performs an OR operation on the input signals of the third test mode transmitted by the transmission gates TG1 and TG3 and provides them as an output signal of the third test mode.

When both the PBT_MODE1 and PBT_MODE2 signals are 'high' according to the mode register set (MRS) signal, the transmission gates TG2 and TG3 are inactivated, and the transmission gates TG1 and TG4 are activated. Output signals of the first first comparators 10 and 20 are transmitted to the second comparator 40 as an input signal of a fourth test mode.

In addition, the second comparator 40 performs an OR operation on the input signals of the fourth test mode transmitted by the transmission gates TG2 and TG3 and provides them as an output signal of the fourth test mode.

In the circuit, the transmission gates TG1 and TG4 are provided with inverters I1 and I4 at the front end to operate to invert the result of each comparator 10 and 20 to apply the inverted signal to the next second comparator 40. This is to test for various patterns.

In the present invention, the conventional use of the MRS signal to change the test mode can be easily modified by changing the value of the address pin. A description with reference to the drawings is as follows.

2 is a diagram of a parallel bit test mode signal generation logic circuit using an address pin to implement the present invention. As shown in Figure 2, A0 and A1 use pins that are not used internally during the test. And the basic configuration to change the test mode by combining the existing master MRS signal.

In the logic circuit shown in FIG. 2, a logic value is output as shown in the table shown in FIG.

3 is a table illustrating a result of a mode address signal according to a combination of an MMRS signal and an address pin illustrated in FIG. 2. Referring to FIG. 3, when MMRS is 0 according to the conditions of the values of MMRS, A0, and A1, PBT_MODE1_ADDR and PBT_MODE2_ADDR always have a value of '0' regardless of the values of A0 and A1. Therefore, in order to read the data of the cell in various patterns, the values of A0 and A1 become meaningful with the MMRS set to '1'. That is, four cases are generated according to the values of A0 and A1 as shown in FIG.

The signals of the PBT_MODE1_ADDR and PBT_MODE2_ADDR are combined with the values of the existing PBT_MODE1 MRS setting unit to output the final PBT_MODE1 signal and the PBT_MODE2 signal.

Hereinafter, a structure in which the PBT_MODE1 signal and the PBT_MODE2 signal are combined with the signals of the mode register setting unit will be described for each embodiment.

4A is a diagram illustrating a first test signal in which a first mode address signal and a signal in a mode register setting unit are combined according to a first embodiment of the present invention. 4A illustrates a first embodiment for outputting a PBT_MODE 1 signal. The PBT_MODE1 MRS setting unit and the PBT_MODE1_ADDR signal are inverted and ORed through a NOR gate, and then inverted again through an inverter to obtain a PBT_MODE1 signal.

In this case, when the signal of the PBT_MODE1 MRS setting unit is 'high', various patterns cannot be tested because the PBT_MODE1 signal always shows a 'high' value. Therefore, in order to test various patterns, it may be configured to always apply a 'low' value without connecting the existing PBT_MODE1 MRS setting unit. In this case, the PBT_MODE1 signal outputs a 'low' value when the PBT_MODE1_ADDR signal is 'low' and outputs a 'high' value when the PBT_MODE1_ADDR signal is 'high'.

4B is a diagram illustrating a second test signal in which a second mode address signal and a signal in a mode register setting unit are combined according to the first embodiment of the present invention. FIG. 4B illustrates a first embodiment for outputting a PBT_MODE 2 signal. The PBT_MODE2 MRS setting unit signal and the PBT_MODE2_ADDR signal are inverted and ORed through a NOR gate, and then inverted again through an inverter to obtain a PBT_MODE2 signal.

Here, when the signal of the PBT_MODE2 MRS setting unit is 'high', the PBT_MODE2 signal always shows a 'high' value and thus various patterns cannot be tested. Therefore, in order to test various patterns, it may be configured to always apply a 'low' value without connecting the existing PBT_MODE2 MRS setting unit. In this case, the PBT_MODE2 signal outputs a 'low' value when the PBT_MODE2_ADDR signal is 'low' and outputs a 'high' value when the PBT_MODE2_ADDR signal is 'high'.

5A is a diagram illustrating a first test signal in which a first mode address signal and a signal in a mode register setting unit are combined according to a second embodiment of the present invention. FIG. 5A illustrates a second embodiment for outputting a PBT_MODE 1 signal, in which the PBT_MODE1 MRS setting unit signal and the PBT_MODE1_ADDR signal are inversely ANDed through a NAND gate, and then inverted again through an inverter to obtain a PBT_MODE1 signal.

Here, when the signal of the PBT_MODE1 MRS setting unit is 'low', since the PBT_MODE1 signal always shows a 'low' value, various patterns cannot be tested. Therefore, in order to test various patterns, the existing PBT_MODE1 MRS setting unit may be configured to always apply a 'high' value. In this case, the PBT_MODE1 signal outputs a 'low' value when the PBT_MODE1_ADDR signal is 'low' and outputs a 'high' value when the PBT_MODE1_ADDR signal is 'high'.

5B is a diagram illustrating a second test signal in which a second mode address signal and a signal in a mode register setting unit are combined according to a second embodiment of the present invention. FIG. 5B illustrates a second embodiment for outputting a PBT_MODE 2 signal. The PBT_MODE2 MRS setting unit signal and the PBT_MODE2_ADDR signal are inversely ANDed through a NAND gate, and then inverted again through an inverter to obtain a PBT_MODE2 signal.

Here, when the signal of the PBT_MODE2 MRS setting unit is 'low', the PBT_MODE2 signal always shows a 'low' value and thus various patterns cannot be tested. Therefore, in order to test various patterns, the existing PBT_MODE2 MRS setting unit may be configured to always apply a 'high' value. In this case, the PBT_MODE2 signal outputs a 'low' value when the PBT_MODE2_ADDR signal is 'low' and outputs a 'high' value when the PBT_MODE2_ADDR signal is 'high'.

Although the present invention has been described above with reference to its preferred embodiments, those skilled in the art will variously modify the present invention without departing from the spirit and scope of the invention as set forth in the claims below. And can be practiced with modification. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

As described above, according to the present invention, it is possible to simply change the test mode by changing the value of the address pin in the conventional problem of having to enter a separate MRS setting mode to change the test mode.

Therefore, the time required to perform the test mode change operation is reduced, thereby reducing the overall test time.

Claims (8)

A mode setting register for setting a state of the parallel bit test signal and the code according to a mode setting register code applied from the outside in response to the mode setting command; At least one address pin for changing a test mode; And An address pin including a mode combination unit for combining the mode setting register value and a test mode address value determined by the value of the address pin, and including a test pattern circuit in which a test mode is determined according to a combination result of the mode combination unit. A semiconductor memory test apparatus for setting a test mode by using. The method of claim 1, wherein the address pin A semiconductor memory test apparatus for setting a test mode by using an address pin, wherein the pin is not used as an address pin during a test. The method of claim 1, wherein the mode combination unit A parallel bit test mode register set logic signal and a mode address signal are input, and a test mode signal is output in accordance with the value of the mode address signal without a set logic unit connected when a test value is read. A semiconductor memory test device that sets a test mode using an address pin. The method of claim 1, wherein the mode combination unit Parallel bit test mode register set The logic part signal and the mode address signal are input, and when the value of both signals is 'high', it outputs 'high' signal and when either value is 'low' 'low' signal And setting a test mode by using an address pin. The method of claim 3 or 4, wherein the mode address signal is The parallel bit test mode register set is configured to output a 'high' when both the logic part and the address pin are 'high', and output a 'low' when either of the values is 'low'. A semiconductor memory test device that sets a test mode using pins. Generating a parallel bit test signal according to the mode setting register code in response to the mode register setting command; Setting a state of a code of a predetermined bit according to the mode setting register code in response to the mode setting command; Setting a test mode by combining a value of an address pin and a mode setting register code value; And If the test code is set, the semiconductor memory test method for setting the test mode using the address pin comprising the step of testing data with the test pattern. The method of claim 6, wherein in setting the test mode: The value of the address pin is a semiconductor memory test method for setting the test mode using the address pin, characterized in that the tester can set a value arbitrarily. 7. The semiconductor memory test of claim 6, further comprising: when the test mode is completed, the tester adjusts the address pin value to enter the next test mode. Way.

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