KR20070073493A - Plasma display device - Google Patents

Abstract

A plasma display device is provided to enhance endurance of a driving circuit by decreasing a temporal current amount flowing through a data IC according to a data pulse supplied from an address driver. A plasma display device includes an address electrode and an address driver. The address electrode is arranged to face a scan electrode or a sustain electrode. The address driver applies a data pulse to the address electrode and generates address discharges. The data pulse supplied to the address electrode is increased or decreased in a step-wise manner by two or more steps. The address driver includes a data IC, a voltage source(Va), a first capacitor(40), and a switch terminal(60). The data IC is connected to the address electrode. The first capacitor is charged and discharged by the voltage from the voltage source. The switch terminal is connected to the voltage source and the first capacitor.

Description

Plasma Display device

1 is a perspective view showing the structure of a plasma display panel according to the prior art;

2 is a diagram illustrating a driving waveform of a plasma display panel according to the prior art;

3 is a circuit diagram showing a circuit configuration of an address driver of a plasma display panel according to the prior art;

4 is a circuit diagram showing a circuit configuration of an address driver of a plasma display device according to the present invention;

5 is an exemplary view showing a driving waveform of the plasma display device according to the present invention.

<Explanation of symbols on main parts of the drawings>

30: data IC 40: first capacitor

50: current blocking element 60: switch stage

Cp: Panel Capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus capable of increasing energy efficiency by supplying data pulses by providing a circuit of an address driver to supply data pulses that rise or fall in at least two stages. It is about.

A plasma display device is a display device in which vacuum ultraviolet rays (VUV) collide with phosphors inside a panel to generate light by a discharge gas inside the panel. As shown in FIG. 1, the plasma display panel is configured by combining the front substrate 10 and the rear substrate 20.

The front substrate 10 includes a scan electrode Y and a sustain electrode Z including a metal bus electrode 11 receiving a driving signal from a scan driver or a sustain driver and a transparent electrode 12 connected to the metal bus electrode. Is formed. In addition, the scan electrode (Y) and the sustain electrode (Z) is formed of a dielectric layer 13 stacked in detail and a protective layer 14 formed on the dielectric.

When a driving signal for driving the panel is supplied to the scan electrode Y and the sustain electrode Z, wall charges are accumulated in the dielectric layer 13, and the passivation layer 14 of the dielectric layer 13 is formed by sputtering. It prevents damage and increases the emission efficiency of secondary electrons.

An address electrode X is formed on the rear substrate 20, and a dielectric layer 23 on which wall charges are accumulated is formed on the address electrode. On the dielectric layer 23, a partition 22 partitioning a discharge space, a phosphor 24 is coated on the side surface of the partition and the dielectric layer 23.

In this way, the plasma display apparatus configured as described above is time-divisionally driven by dividing one frame into several subfields having different numbers of emission times. As shown in FIG. 2, each of the subfields includes a reset period R, an address period A, and a sustain period S. As shown in FIG.

During the reset period (R), a signal of a ramp waveform is supplied to generate a reset discharge to initialize the discharge cell.In the address period (A), a data pulse is applied to the address electrode, and the scan electrode is synchronized with and opposite to this. An address discharge is generated by applying a scan pulse having a polarity.

During the sustain period S, sustain pulses are alternately supplied to the scan electrode Y and the sustain electrode Z, and sustain discharge is generated between the scan electrode and the sustain electrode to display an image. In this case, the difference between the high potential voltage and the low potential voltage of the sustain pulse is referred to as the sustain voltage Vs.

The sustain voltage is a high voltage of 100 V or more, and the sustain pulse is formed by repeatedly switching high potentials, so that the power consumption of the panel increases as the number of sustain pulses increases during one frame.

In the conventional plasma display apparatus driven as described above, since the data size of the panel is less than 40 inches or the data pulses are supplied by the dual scan method from the address driver connected to the upper and lower ends of the panel, the address is spaced. The period is secured enough.

However, in recent years, the panel size has been enlarged to 50 inches or more, and in order to reduce manufacturing costs, data pulses are supplied by a single scan method by one address driver, so that the number of data pulses dp supplied by the address driver is reduced. There is a problem that heat generation is increased in the switch element and the data IC and the like provided in the address driver.

Referring to this conventional problem in detail with reference to FIG. 3, the conventional address driver includes a power supply unit 3 including a switch Q1 which is turned on to rise to a positive voltage level Va under the control of a timing controller, and a push-pull. It comprises a data IC (4) consisting of bidirectional switches (Q2, Q3) connected in a form.

Since a panel is connected between the bidirectional switches Q2 and Q3 of the data IC 4, a data pulse rising to a positive voltage level is supplied as the switch Q1 and the upper bidirectional switch Q2 are conducted. As the switch Q1 and the upper bidirectional switch Q2 are shut off and the lower bidirectional switch Q3 is turned on, a data pulse dp that descends to the ground level is supplied.

Therefore, the conventional address driver temporarily supplies current from the voltage source Va to the panel as the switch Q1 is turned on, and temporarily cuts off the supply of the current as the lower bidirectional switch Q3 is turned on. Since the data pulse is supplied through hard switching, there is a problem in that the heat generation of the data IC 4 is increased by the hard switching, thereby degrading circuit durability.

The present invention has been made to solve the above-described problems of the prior art, the object of which is to configure the circuit of the address driver so that the data pulse rising or falling in at least two or more stages, the switch element due to the conventional hard switching and The present invention provides a plasma display device capable of reducing heat generation in a data IC including the same and improving circuit durability.

According to an aspect of the present invention, there is provided a plasma display apparatus including an address electrode facing a scan electrode or a sustain electrode, and an address driver for generating an address discharge by applying a data pulse to the address electrode. The data pulse supplied to the address electrode by the address driver is stepped up or down in at least two stages.

The address driver includes a data IC connected to the address electrode, a voltage source, a first capacitor and a switch stage (first switch and second switch) connected to the voltage source, respectively.

 The address driver may further include a current blocking device connected between the voltage source and the first capacitor to block current flow to the voltage source.

In the data pulse supplied by the address driver of the present invention, when the first switch is turned off and the second switch is turned on, the data pulse rises by the voltage charged in the first capacitor, and the first switch is turned on. On, the data pulse is increased by the voltage applied from the voltage source and the voltage charged in the first capacitor when the second switch is off.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. 4 is a circuit diagram showing a circuit configuration of an address driver of the plasma display device according to the present invention, and FIG. 5 is an exemplary diagram showing a drive waveform of the plasma display device according to the present invention.

First, the panel Cp is formed by combining a front substrate and a rear substrate, and a capacitance is formed between electrodes formed on each substrate, which is called a panel capacitor.

The scan electrode Y formed on the front substrate is connected to a scan driver to supply a driving signal, and the sustain electrode Z formed on the front substrate is connected to a sustain driver to supply a driving signal. In addition, the address electrode X formed on the rear substrate is connected to an address driver to supply a driving signal. The present invention relates to a circuit configuration of the address driver and a waveform of a data pulse supplied from the address driver. .

Referring to FIG. 4, the address driver charges / discharges the data IC 30 connected to the address electrode, a voltage source Va for applying a voltage, and a voltage applied from the voltage source Va. And a switch stage 60 connected to each of the first capacitor 40 and the voltage source Va and the first capacitor 40.

In addition, the address driver is connected between the voltage source (Va) and the first capacitor 40, the current to block the flow of current toward the voltage source (Va) in accordance with the voltage charged in the first capacitor (40) It further comprises a blocking element (50).

The data IC 30 includes bidirectional switches SW1 and SW2 connected in a push-pull form, and each bidirectional switch SW1 and SW2 are complementarily turned on and off, and a panel capacitor Cp therebetween. ) Is connected.

The switch stage 60 includes a first switch SW3 connected in parallel with the first capacitor 40 and a second switch SW4 connected in series with the first switch SW3. The first switch SW3 and the second switch SW4 alternately switch to control the flow of the charge / discharge voltage flowing through the first capacitor 40.

Here, the operation of the first switch SW3 and the second switch SW4 will be described. When the voltage Va is applied, the first switch SW3 is turned off and the second switch SW4 is turned on. The voltage Va applied to the one capacitor 40 is charged, and the voltage Va is applied to the panel capacitor Cp through the data IC 70.

In addition, when the first switch SW3 is turned on and the second switch SW4 is turned off, the voltage Va charged in the first capacitor 40 is discharged. In this case, the voltage applied from the voltage source Va is discharged. And a voltage 2Va is applied to the panel capacitor Cp through the data IC 70 according to the voltage discharged to the first capacitor 40.

For example, when the voltage Va applied from the voltage source is 30V, when the first switch SW3 is turned off and the second switch SW4 is turned on, 30V is applied to the panel capacitor Cp and at the same time, the first switch SW3 is turned on. A 30V voltage is charged to the capacitor 40, and at this time, the first switch SW3 is turned on and the second switch SW4 is turned off to charge the 30V voltage charged in the first capacitor 40 and the voltage source Va. A 60V voltage is applied to the panel capacitor according to the 30V voltage applied.

Therefore, the first switch SW3 and the second switch SW4 are alternately operated to control the flow of the charge / discharge voltage flowing through the first capacitor 40, thereby being applied to the panel capacitor Cp. The voltage can be adjusted to improve energy efficiency

The data pulse dp supplied to the panel from the address driver with the circuit structure configured as described above is a waveform that rises and falls in at least two stages as shown in FIG.

In more detail, referring to FIGS. 4 and 5, when the data pulse is supplied, the first capacitor 40 is charged when the first switch SW3 is turned off and the second switch SW4 is turned on. The data pulse is increased by the first voltage Va, and when the first switch SW3 is turned on and the second switch SW4 is turned off, the data pulse is raised to the second voltage 2Va.

At this time, when the second voltage 2Va is maintained for a predetermined time and the second switch SW4 is turned on, the data pulse drops to the first voltage Va, and the ground level is maintained as the first switch SW3 is turned on. The data pulses fall until.

Accordingly, by controlling the flow of the charge / discharge voltage flowing through the first capacitor 40 by alternately operating the first switch SW3 and the second switch SW4, the data pulse supplied to the address electrode rises. And a falling waveform is formed.

 As such, when the data pulses dp rising and falling in at least two stages are supplied, the amount of current flowing temporarily to the data IC 30 provided in the address driver is reduced to half, so that the heat generation is distributed and circuit durability. This is improved.

As described above, the plasma display device according to the present invention has been described with reference to the illustrated drawings. However, the present invention is not limited by the embodiments and the drawings disclosed herein, and by those skilled in the art within the scope of the technical idea of the present invention. Application is possible.

The plasma display apparatus according to the present invention configured as described above includes a voltage source and a switch stage connected to a capacitor for charging / discharging a voltage applied from the voltage source, so that the plasma display device includes a data pulse supplied from the address driver. Accordingly, the amount of current and heat generated temporarily in the data IC can be reduced, thereby improving circuit durability.

Claims (4)

An address electrode facing the scan electrode or the sustain electrode, An address driver for generating an address discharge by applying a data pulse to the address electrode, And the data pulse supplied to the address electrode by the address driver is stepped up or stepped down in at least two stages. The method according to claim 1, The address driver includes a data IC connected to the address electrode, a voltage source applying a predetermined voltage Va, a first capacitor charging / discharging a voltage Va applied from the voltage source, the voltage source and the first And a switch stage connected to each of the capacitors. The method according to claim 2, And the address driver further includes a current blocking device connected between the voltage source and the first capacitor to block current flow to the voltage source. The method according to claim 2, The switch stage includes a first switch connected in parallel with the first capacitor and a second switch connected in series with the first switch, The data pulse rises by a voltage charged in the first capacitor when the first switch is off and the second switch is on; And the data pulse rises by a voltage applied from the voltage source when the first switch is on and the second switch is off.

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