KR20070073279A - Tft substrate and making method of the same - Google Patents

Abstract

A thin film transistor substrate and a manufacturing method of the same are provided to improve a lifting effect of a thin film from a plastic insulating substrate in a cleaning process of the plastic insulating substrate and a thin film patterning process. A first inorganic layer(20a) is formed on one surface of a plastic insulating substrate(10). A second inorganic layer(20b) is formed on the other surface of the plastic insulating substrate. The thickness of the first inorganic layer is larger than the thickness of the second inorganic layer. The first and second inorganic layers include at least one of silicon oxide and silicon nitride. A gate insulating layer, a resistant contact layer, and a semiconductor layer are formed on the second inorganic layer. The first inorganic layer has a thickness causing stress, of 70 to 80 percent, when forming the third layer.

Description

Thin Film Transistor Substrate and its Manufacturing Method {TFT SUBSTRATE AND MAKING METHOD OF THE SAME}

1A is a plan view of a thin film transistor substrate according to a first embodiment of the present invention,

FIG. 1B is a cross-sectional view of the thin film transistor substrate according to Ib-Ib of FIG.

2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

3 is a cross-sectional view of a plastic insulating substrate according to a second embodiment of the present invention.

Explanation of Signs of Major Parts of Drawings

5: plastic mother board 10: plastic insulation board

11: plastic material 13: undercoating layer

15: barrier coating layer 17a, 17b: hard coating layer

20a: first inorganic layer 20b: second inorganic layer

30: display element

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate and a method of manufacturing the same, wherein the lifting of the thin film formed on the plastic insulating substrate is reduced.

Recently, flat panel displays such as liquid crystal displays and organic light emitting diodes (OLEDs) have been used in place of existing CRTs.

The liquid crystal display device includes a first substrate on which a thin film transistor is formed, a second substrate disposed opposite to the first substrate, and a liquid crystal display panel on which a liquid crystal layer is positioned. Since the liquid crystal display panel is a non-light emitting device, a backlight unit for irradiating light may be disposed on the rear surface of the thin film transistor substrate, and the light emitted from the backlight unit is controlled according to the arrangement state of the liquid crystal layer to form a screen. .

The liquid crystal display device further includes a driving circuit for applying a driving signal to a gate line and a data line formed on the thin film transistor substrate in order to form a screen in the display area. The driving circuit includes a gate driving chip and a data driving chip, and a printed board on which a timing controller and a driving voltage generator are formed.

The organic light emitting device includes an organic light emitting layer formed on a thin film transistor substrate, which receives holes and electrons from a pixel electrode and a common electrode and emits light through a combination of holes and electrons. The organic light emitting display device has an advantage of not requiring a separate backlight unit when the viewing angle is excellent.

Recently, in order to reduce the weight and thickness of flat panel display devices, applications of plastic insulating substrates instead of glass insulating substrates have been actively applied.

Various display devices including a thin film transistor may be formed in a thin film form on the plastic insulating substrate. However, the inorganic thin film constituting the display device does not have good adhesion with the organic plastic insulating substrate, and the thermal expansion degree between the thin film and the plastic insulating substrate is different, which causes a problem in that the thin film is lifted. In addition, there is a problem that a defect may occur in the plastic insulating substrate by the chemical used in the process of cleaning the plastic insulating substrate or patterning the thin films.

It is therefore an object of the present invention to provide a thin film transistor substrate having a reduced problem of lifting a thin film from a plastic insulating substrate.

Another object of the present invention is to provide a method for manufacturing a thin film transistor substrate, which reduces the problem of lifting a thin film from a plastic insulating substrate.

The above object is, according to the present invention, a plastic insulating substrate; A first inorganic layer formed on one surface of the plastic insulating substrate; And a second inorganic layer formed on the other surface of the plastic insulating substrate, wherein the thickness of the first inorganic layer is thicker than the thickness of the second inorganic layer.

The first and second inorganic layers may include at least one of silicon oxide and silicon nitride.

The gate insulating film, the ohmic contact layer, and the three-layer film of the semiconductor layer are successively formed on the second inorganic layer, and the first inorganic layer has a stress of 70% to 80% of the stress generated when the three-layer film is formed. It may have a thickness generated.

In addition, the first inorganic layer may have a thickness in which a stress of 2.0 × 10 ⁹ dyne / cm ² to 2.5 × 10 ⁹ dyne / cm ² is generated.

The thickness of the first inorganic layer may be 1.2 to 1.5 times the thickness of the second inorganic layer.

Here, the third inorganic layer may be further formed between the plastic insulating substrate and the first inorganic layer.

Another object of the invention, according to the invention, the step of bonding the plastic mother substrate to the glass substrate; Forming a first inorganic layer on the plastic mother substrate; Separating the plastic mother substrate from the glass substrate, and then bonding the plastic mother substrate to the additional glass substrate such that the side on which the first inorganic layer is formed faces the additional glass substrate; Forming a second inorganic layer having a thickness thinner than the first inorganic layer on the plastic mother substrate; It is achieved by a method for manufacturing a thin film transistor substrate comprising the step of forming a thin film transistor on the second inorganic layer.

Here, the plastic mother substrate is divided into a plastic insulating substrate region provided with a thin film transistor and a dummy plastic substrate region where an image is not formed, and may further include separating the plastic mother substrate into a plurality of plastic insulating substrates.

At least one of the steps of forming the first and second inorganic layers may further include arranging a mask having an opening formed on one surface of the plastic mother substrate to correspond to the plastic insulating substrate. At least one of the layers may be formed by plasma enhanced chemical vapor deposition (PECVD).

The method may further include forming a third inorganic layer between the plastic mother substrate and the first inorganic layer.

Here, the adhesive member used in bonding the plastic mother substrate to the glass substrate may have a weaker adhesive force than the adhesive member used in bonding the plastic mother substrate to the additional glass substrate.

The forming of the thin film transistor may include forming a three-layered film including a gate insulating film, an ohmic contact layer, and a semiconductor layer in succession, wherein one inorganic layer is 70% to 80% of the stress generated when the three-layer film is formed. The stress may be formed to have a thickness that is generated.

In addition, the first inorganic material layer may be formed to have a thickness in which stress of 2.0 × 10 ⁹ dyne / cm ² to 2.5 × 10 ⁹ dyne / cm ² is generated.

The thickness of the first inorganic layer may be 1.2 to 1.5 times the thickness of the second inorganic layer.

In addition, the thickness of the first inorganic layer may be 1.2 to 1.5 times the thickness of the second inorganic layer.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention. In the following, a film is formed (located) on another layer, not only when two films are in contact with each other but also when another film is between two layers. It also includes the case where it exists.

1A is a plan view of a plastic insulation substrate according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view of the plastic insulation substrate according to Ib-Ib of FIG. 1A.

In general, the thin film transistor substrate to which the plastic insulating substrate 10 is applied is manufactured from one large plastic mother substrate 5. As shown in Fig. 1A, the plastic mother substrate 5 is divided into a plastic insulating substrate region a to be used as the plastic insulating substrate 10 and a dummy plastic substrate region b other than that. The thin film transistor substrate attaches the plastic mother substrate 5 to the glass substrate, and then forms the display element 30 including the plurality of thin films on the plastic mother substrate 5. Next, the plastic mother substrate 5 is separated into a plurality of thin film transistor substrates, and a flat panel display device is manufactured using the separated thin film transistor substrates.

As illustrated in FIG. 1B, the thin film transistor substrate according to the present invention may include a plastic insulating substrate 10, inorganic layers 20a and 20b formed on at least one surface of the plastic insulating substrate 10, and the plastic. The display device 30 is formed on one surface of the insulating substrate 10. The display device 30 includes a thin film transistor in which a plurality of thin films are sequentially deposited, and electrodes formed on the thin film transistor.

The plastic insulating substrate 10 includes a plastic material 11, an undercoat layer 13, a barrier coating layer 15, and hard coating layers 17a and 17b formed on any one surface of the plastic material 11. In the plastic insulating substrate 10 according to the exemplary embodiment of the present invention, an undercoat 13 and a barrier coating layer 15 are sequentially formed on a rear surface of the plastic material 11, and an upper surface and a barrier of the plastic material 11 are formed. Hard coating layers 17a and 17b are formed on the back surface of the coating layer 15, respectively. However, the structure is not limited thereto, and the undercoat 13, the barrier coating layer 15, and the hard coat layers 17a and 17b may be sequentially formed on both surfaces of the plastic material 11, respectively. Of course, other structures are possible.

The plastic material 11 may be made of polycarbon, polyimide, polyether sulfone (PES), polyarylate (PAR), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like. The thickness may be less than 0.2mm and 0.05mm to 0.2mm.

The undercoat 13 serves to improve adhesion between the plastic material 11 and the barrier coating layer 15 and is made of thermosetting acrylic or ultraviolet curing acrylic. When the adhesion between the plastic material 11 and the barrier coating layer 15 is good, for example, when the barrier coating layer 15 is made of an organic material, the undercoat layer 13 may be omitted.

The barrier coating layer 15 prevents oxygen or moisture from penetrating into the plastic material 11. The barrier coating layer 15 may form an inorganic nitride film such as AlOxNy, Al, AlOx, SiOx, SiNx, Al2O3-SiO2, an inorganic oxide film, an organic film such as parylene, or the like. The barrier coating layer 15 may also have a two-layer structure of an inorganic film and an acrylic film. When the barrier coating layer 15 includes an inorganic layer such as a silicon nitride layer, the inorganic layer is densely manufactured to prevent the penetration of oxygen or moisture.

The hard coating layers 17a and 17b prevent scratches and chemical damage of the plastic material 11 and are made of thermosetting acrylic or ultraviolet curing acrylic. The hard coating layers 17a and 17b also serve to facilitate separation between the plastic insulating substrate 10 and the glass substrate after formation of the display element.

The plastic insulating substrate 10 is thinner than the glass insulating substrate and has a characteristic of being well bent, and thus has a disadvantage of being very vulnerable to stress during deposition of a metal layer or another thin film. In particular, the display device 30 is formed on the plastic insulating substrate 10, and the display device 30 includes a gate insulating film forming a thin film transistor, a three-layer film of an ohmic contact layer, and a semiconductor layer. The thin films including the three-layer film are formed by plasma enhanced chemical vapor deposition (PECVD), and when the three-layer film is deposited, a large compressive stress is applied to the plastic insulating substrate 10 to the plastic insulating substrate 10. There is a problem that cracks are generated. In addition, the thin film of the inorganic material constituting the display device does not have good adhesion with the organic plastic insulating substrate 10, and the thermal expansion degree between the thin film and the plastic insulating substrate 10 is different, and thus the lifting of the thin film is caused. There is a problem that occurs. In addition, a chemical is used in the process of cleaning the plastic insulating substrate 10 or patterning the thin films, there is a problem that such a chemical may attack the plastic insulating substrate 10 may cause a defect.

Thus, in the present invention, the first and second inorganic layers 20a and 20b are formed on both surfaces of the hard coating layers 17a and 17b to minimize the above problems. In an embodiment of the present invention, the first inorganic layer 20a is formed using a mask provided with an opening corresponding to the plastic insulating substrate region a. Therefore, the first inorganic material layer 20a is provided corresponding to the plastic insulating substrate region a. When the second inorganic layer 20b is formed, the second inorganic layer 20b is formed on the entire surface of the plastic mother substrate 5 without using the mask. This structure is only one embodiment, and the second inorganic layer 20b may also be formed using a mask.

The first and second inorganic layers 20a and 20b may include at least one of silicon oxide and silicon nitride, and the thickness d1 of the first inorganic layer 20a is the thickness d2 of the second inorganic layer 20b. It is thicker than). Here, the first inorganic layer 20a may be formed to have a thickness d1 of 70% to 80% of the stress generated when the three-layer film is formed. In addition, the first inorganic layer 20a may be formed to have a thickness at which a stress of 2.0 × 10 ⁹ dyne / cm ² to 2.5 × 10 ⁹ dyne / cm ² is generated. In addition, the thickness d1 of the first inorganic layer 20a may be 1.2 to 1.5 times the thickness d2 of the second inorganic layer 20b. As such, the reason why the thicknesses d1 and d2 of the first inorganic layer 20a and the second inorganic layer 20b are different from each other is to balance the stress applied to the plastic insulating substrate 10 to solve the above-described problems. It is to minimize. That is, in consideration of the deposition of a plurality of thin films on the second inorganic layer 20b, forming the thickness d1 of the first inorganic layer 20a to be thicker than the thickness d2 of the second inorganic layer 20b. desirable.

In general, when the stress applied to the plastic insulating substrate 10 is greater than about 3 × 10 ⁹ dyne / cm ² when the three-layer film is formed by the plasma enhanced chemical vapor deposition method, cracks or lifting occur in the plastic insulating substrate 10. Therefore, in order to buffer the stress generated during the three-layer film deposition, the thickness d1 of the first inorganic layer 20a is 2.0 × 10 ⁹ dyne / cm ² to 2.5 ×, which is 70% to 80% of the stress during the three-layer film deposition. It is preferable to form at a thickness of about 10 ⁹ dyne / cm ² . In order to balance the stress on both surfaces of the plastic insulating substrate 10, the thickness d2 of the second inorganic layer 20b is equal to the thickness d1 of the first inorganic layer 20a of the second inorganic layer 20b. It is preferable to form about 1.2 to 1.5 times the thickness (d2) of.

The thin film transistor substrate may be bonded to another substrate with a liquid crystal interposed therebetween and used as a liquid crystal display, or may be used as an OLED by forming an organic light emitting layer and a common electrode on a pixel electrode.

Hereinafter, a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention will be described with reference to FIGS. 2A to 2E.

2A to 2E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

First, the plastic mother substrate 5 is attached to the glass substrate 41 using an adhesive member (not shown) as shown in FIG. 2A. Since the plastic mother substrate 5 is not only thin but also deformed by heat, the plastic mother substrate 5 is processed while being supported by the glass substrate 41. Here, the plastic mother substrate 5 includes a plurality of plastic insulating substrate regions (a, FIG. 1a) in which display elements 30 such as thin film transistors are to be provided in a later process, and a dummy plastic substrate region b in which an image is not formed. , See FIG. 1A). In addition, since the adhesive member (not shown) used in the bonding process is detached from the organic substrate 41 immediately after the first inorganic layer 20a is formed, the adhesive force is preferably weak. The adhesive member (not shown) may be an adhesive in a gel or sol state, or may be an adhesive tape. In addition, the adhesive member (not shown) may be a low temperature detachable type that loses the adhesive force at a predetermined temperature or less, and the adhesion of the plastic mother substrate 5 and the glass substrate 41 may be achieved by applying an adhesive to one surface of the plastic mother substrate 5. After the coating may be performed by attaching to the glass substrate 41. Of course, the opposite is also possible.

Subsequently, as shown in FIG. 2B, the mask 50 is aligned and disposed on the plastic mother substrate 5, and the first inorganic layer 20a is formed by a plasma enhanced chemical vapor deposition (PECVD) method. Here, the mask 50 is provided with an opening corresponding to the plastic insulating substrate region a. The reason for using the mask is to improve the accuracy of the process and to form a plurality of thin film transistor substrates on one large plastic mother substrate 5. This is called a multifaceted method, and the mask 50 may not be used. Since the desired thin film or the like can be formed only in the required area by the multi-sided etching method, the accuracy of the process is improved, and a plurality of thin film transistor substrates can be manufactured from one process, thereby improving the yield. Here, the first inorganic layer 20a may be formed by a sputtering method.

Herein, when the stress applied to the plastic insulating substrate 10 is greater than about 3 × 10 ⁹ dyne / cm ² when the three-layer film (gate insulating film, ohmic contact layer, semiconductor layer) is formed by the plasma enhanced chemical vapor deposition method, the plastic insulation is performed. In consideration of the occurrence of cracks or lifting in the substrate 10, the thickness d1 of the first inorganic layer 20a is from 2.0 × 10 ⁹ dyne / cm ² to 70% to 80% of the stress upon deposition of the three-layer film. It is preferable to form in thickness which becomes about 2.5 * 10 <^9> dyne / cm <^2> . This is to buffer the stress generated during the deposition of the three-layer film.

Thereafter, as shown in FIG. 2C, after the plastic mother substrate 5 is separated from the glass substrate 41 (see FIG. 2B), the surface on which the first inorganic layer 20a is formed is additional glass substrate 45. The plastic mother substrate 5 is bonded to the additional glass substrate 45 so as to face each other. The adhesive member (not shown) used here is preferably stronger than the bonding member (not shown) used in the above-described bonding process (bonding process in Fig. 2A). Since the adhesive member (not shown) used in the bonding process of FIG. 2 is detached from the organic substrate 41 (see FIG. 2A) immediately after the formation of the first inorganic layer 20a, it is preferable that the adhesive force is relatively weak. In the case of the bonding process, since the subsequent display device forming process is performed, it is preferable that the adhesive strength is relatively good.

Next, as shown in FIG. 2D, the second inorganic layer 20b is formed on the surface opposite to the surface on which the first inorganic layer 20a is formed. The second inorganic layer 20b may also be formed by a plasma enhanced chemical vapor deposition method or a sputtering method, and the thickness d2 of the second inorganic layer 20b is equal to the thickness d1 of the first inorganic layer 20a. The thickness of the second inorganic layer 20b is preferably about 1.2 to about 1.5 times the thickness d2. Thus, forming the thickness d2 of the second inorganic layer 20b to be thinner than the thickness d1 of the first inorganic layer 20a may include a display device including a plurality of thin films in the second inorganic layer 20b ( 30, see FIG. 1B) to balance the stress on both sides of the plastic insulating substrate (10). Although the second inorganic layer 20b is manufactured without using a mask, the second inorganic layer 20b may be formed only in a desired region by using a mask like the first inorganic layer 20a.

Next, as shown in FIG. 2E, the display device 30 is formed on the second inorganic layer 20b by a known method. Here, the display element 30 may be formed by a multi-sided method of forming only a desired place using a mask. The display device 30 includes a thin film transistor, and a thin film transistor is formed by sequentially depositing a gate insulating film, an ohmic contact layer, and a three-layer film of a semiconductor layer. The three-layer film is removed through a plasma-enhanced chemical vapor deposition method, and stress is buffered by the first and second inorganic layers 20a and 20b even when stress is generated when the three-layer film is formed, thereby cracking the plastic mother substrate 5. cracks and thin film lifting are reduced. In addition, since the plastic mother substrate 5 is protected by the first and second inorganic layers 20a and 20b, the plastic mother substrate 5 may be generated by a chemical used in the process of cleaning the plastic mother substrate 5 or patterning the thin films. The defect of the mother substrate 5 can be minimized. On the other hand, when the plastic mother substrate 5 is used, the above-described process temperature for forming the first and second inorganic layers 20a and 20b or the thin film is maintained within 150 to 200 ° C., which is a thermally acceptable range of the plastic mother substrate 5. Should be.

Next, although not shown, a thin film transistor substrate is manufactured by separating the plastic mother substrate 5 into a plurality of plastic insulating substrates. The thin film transistor substrate may be bonded to another substrate with a liquid crystal interposed therebetween and used as a liquid crystal display, or may be used as an OLED by forming an organic light emitting layer and a common electrode on a pixel electrode.

3, a thin film transistor substrate according to a second embodiment of the present invention will be described. In the second embodiment of the present invention, only the characteristic parts that are distinguished from the first embodiment will be described and described, and the description thereof will be omitted according to the known technology or the first embodiment. In addition, for the convenience of description, the same reference numerals will be given to the same elements will be described.

In the thin film transistor substrate according to the second embodiment, a third inorganic layer 20c is further formed between the plastic mother substrate 5 (see FIG. 2A) or the plastic insulating substrate 10 and the first inorganic layer 20a. As described above, the first inorganic layer 20a is formed only in a required region by using a mask, whereas the third inorganic layer 20c is formed on the entire surface of the plastic insulating substrate 10. In the first embodiment, as the first inorganic layer 20 is manufactured by a multi-faceted method, a defect may be caused by a chemical into an interspace in which the first inorganic layer 20a is formed. However, by forming the third inorganic layer 20c, it is possible to effectively protect the plastic insulating substrate from chemicals used during cleaning or patterning of the thin film. In addition, the first to third inorganic layers 20a, 20b, and 20c may be provided as a single layer or a plurality of layers.

As described above, according to the present invention, a thin film transistor substrate is provided in which the problem of lifting a thin film from a plastic insulating substrate is reduced.

According to the present invention, there is provided a method of manufacturing a thin film transistor substrate, which reduces the problem of lifting a thin film from a plastic insulating substrate.

Claims (15)

Plastic insulating substrates; A first inorganic material layer formed on one surface of the plastic insulating substrate; A second inorganic layer formed on the other surface of the plastic insulating substrate, The thickness of the first inorganic layer is a thin film transistor substrate, characterized in that thicker than the thickness of the second inorganic layer. The method of claim 1, The thin film transistor substrate of claim 1, wherein the first and second inorganic layers include at least one of silicon oxide and silicon nitride. The method of claim 2, On the second inorganic layer, a gate insulating film, an ohmic contact layer, and a three-layer film of a semiconductor layer are formed in succession, The first inorganic layer is a thin film transistor substrate, characterized in that having a thickness of 70% to 80% of the stress generated when forming the three-layer film. The method of claim 2, The first inorganic layer is a thin film transistor substrate, characterized in that the thickness of the stress is generated 2.0 × 10 ⁹ dyne / cm ² to 2.5 × 10 ⁹ dyne / cm ² . The method according to any one of claims 2 to 4, The thickness of the first inorganic layer is a thin film transistor substrate, characterized in that 1.2 to 1.5 times the thickness of the second inorganic layer. The method of claim 5, A thin film transistor substrate, characterized in that a third inorganic layer is further formed between the plastic insulating substrate and the first inorganic layer. Bonding the plastic mother substrate to the glass substrate; Forming a first inorganic layer on the plastic mother substrate; Separating the plastic mother substrate from the glass substrate, and then bonding the plastic mother substrate to the additional glass substrate so that the side on which the first inorganic layer is formed faces the additional glass substrate; Forming a second inorganic layer having a thickness thinner than the first inorganic layer on the plastic mother substrate; And forming a thin film transistor on the second inorganic layer. The method of claim 7, wherein The plastic mother substrate is divided into a plastic insulating substrate region in which the thin film transistor is provided, and a dummy plastic substrate region in which an image is not formed. And separating the plastic mother substrate into a plurality of plastic insulating substrates. The method of claim 8, At least one of the forming of the first and second inorganic layers may further include arranging a mask having an opening formed on one surface of the plastic mother substrate to correspond to the plastic insulating substrate. At least one of the first and second inorganic layers is formed by plasma enhanced chemical vapor deposition (PECVD). The method according to claim 7 or 9, And forming a third inorganic layer between the plastic mother substrate and the first inorganic layer. The method according to claim 7 or 9, The adhesive member used to attach the plastic mother substrate to the glass substrate has a weaker adhesive force than the adhesive member used to attach the plastic mother substrate to the additional glass substrate. Way. The method according to claim 7 or 9, Forming the thin film transistor includes a step of successively forming a three-layer film of the gate insulating film, the ohmic contact layer, and the semiconductor layer, The first inorganic layer is a thin film transistor substrate manufacturing method characterized in that formed to have a thickness of 70% to 80% of the stress generated during the formation of the three-layer film. The method according to claim 7 or 9, The first inorganic layer is a method of manufacturing a thin film transistor substrate, characterized in that formed to have a thickness that generates a stress of 2.0 × 10 ⁹ dyne / cm ² to 2.5 × 10 ⁹ dyne / cm ² . The method of claim 12, The thickness of the first inorganic layer is a method of manufacturing a thin film transistor substrate, characterized in that 1.2 to 1.5 times the thickness of the second inorganic layer. The method of claim 13, The thickness of the first inorganic layer is a method of manufacturing a thin film transistor substrate, characterized in that 1.2 to 1.5 times the thickness of the second inorganic layer.

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