KR20070072763A - Liquid crystal display having kickback compensation circuit - Google Patents

Abstract

An LCD device having a kickback compensation circuit is provided to enhance image quality by lowering a kickback voltage based on a voltage variation width, when a driving voltage is changed from a gate-on voltage to a gate-off voltage. An LCD(Liquid Crystal Display) device includes a liquid crystal panel, a timing controller, a voltage generator, and a gate driver. The liquid crystal panel includes gate lines. The timing controller outputs a kickback signal(KB) and control signals. The voltage generator generates a gate-on voltage of a first voltage level and a first source voltage. The gate driver supplies the gate-on voltage to gate lines. The voltage generator includes a discharge circuit(202), a voltage divider, and a kickback compensation circuit. The discharge circuit lowers the gate-on voltage to a second voltage level lower than the first voltage level in response to the kickback voltage. The voltage divider is connected between the first source voltage and a ground voltage. The kickback compensation circuit includes an operational amplifier(260). The operational amplifier has an inverting terminal, a non-inverting terminal connected to the voltage divided by the voltage divider, and an output terminal which is connected to the non-inverting terminal and the discharge circuit and outputs the voltage of the second voltage level.

Description

Liquid crystal display including kickback compensation circuit {LIQUID CRYSTAL DISPLAY HAVING KICKBACK COMPENSATION CIRCUIT}

1 is a view showing a configuration of a liquid crystal display according to a preferred embodiment of the present invention;

2 shows a kickback compensation circuit according to a preferred embodiment of the present invention provided in the voltage generator shown in FIG.

3 is a timing diagram showing that the difference between the gate on voltage and the gate off voltage is reduced by the kickback compensation circuit shown in FIG. 2; And

4 is a diagram illustrating a time required for the gate-on voltage to be lowered from the first voltage level to the second voltage level by the kickback compensation circuit according to the exemplary embodiment of the present invention.

* Description of the main parts of the drawing

100: liquid crystal display 110: timing controller

120: voltage generator 130: gate driver

140: source driver 150: liquid crystal panel

200: kickback compensation circuit

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a kickback compensation circuit.

A representative example of lowering the image quality of the thin film transistor liquid crystal display is a luminance unbalance caused by the kickback voltage. In general, when the potential of the gate voltage of the thin film transistor for driving the liquid crystal is switched from the gate on voltage to the gate off voltage, the gray voltage is reduced by a predetermined potential. Kickback voltage refers to the potential that is reduced at this time.

As a method of arranging the gate driver for sequentially applying pulses to the gate lines, there is a single bank structure in which the gate driver is disposed only on one side of the liquid crystal panel, and a dual bank structure in which the gate driver is disposed on both sides of the liquid crystal panel. In the liquid crystal display of the single arrangement structure, the signal delay in the gate line is larger than that of the liquid crystal display of the dual arrangement structure.

For example, in a liquid crystal display device having a single arrangement structure, if a gate voltage is applied to any gate line when the gate driver is disposed on the left side of the liquid crystal panel, the gate voltage actually measured at the rightmost point of the gate line is the gate line. It has a waveform delayed more than the gate voltage measured at its leftmost point. Due to the delay of the gate voltage, the kickback voltage of each pixel connected to one gate line is changed.

This is because charge is supplied through the thin film transistor of the pixel at the corresponding position for a predetermined time when the delayed waveform of the gate voltage is applied. Therefore, even when the data voltage of the same gray level is applied to a plurality of pixels connected to one line, the charging voltages of the leftmost pixel located near the gate driver and the rightmost pixel far from the gate driver are different. This difference in the charging voltage is tolerable to a certain limit, but when it reaches an extent exceeding one gradation level interval, the left and right luminance difference of the liquid crystal panel for the same gradation may be visually identified.

Accordingly, an object of the present invention is to provide a liquid crystal display device having improved image quality by reducing kickback voltage.

According to a feature of the present invention for achieving the above object, the liquid crystal display device includes a liquid crystal panel, a timing controller, a voltage generator and a gate driver. The liquid crystal panel includes a plurality of gate lines. The timing controller outputs kickback signals and control signals having a predetermined period. A voltage generator for generating a gate-on voltage and a first power supply voltage of a first voltage level, the discharge circuit lowering the gate-on voltage to a voltage of a second voltage level lower than the first voltage level in response to the kickback signal; A voltage divider connected between the first power supply voltage and a ground voltage, and an inverting input terminal, a non-inverting input terminal connected to a voltage divided by the voltage divider, and the inverting input terminal and the discharge circuit, and the second voltage And a kickback compensation circuit comprising an operational amplifier having an output stage for outputting a voltage of level. The gate driver sequentially provides the gate-on voltage to the plurality of gate lines of the liquid crystal panel in response to the control signals.

The discharge circuit may include a transistor having a first resistor having one end connected to the gate-on voltage, a first terminal, a second terminal, and a third terminal connected to the first resistor, the third terminal of the transistor, and the And a second resistor having a capacitor connected between a kickback signal, and a first end connected to the third terminal of the transistor, and a second end connected in common with the second terminal of the transistor and the output terminal of the operational amplifier.

The voltage divider includes at least two resistors connected in series between the first power supply voltage and the ground voltage, and a connection node of the resistors is connected with a non-inverting input terminal of the amplifier.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display 100 includes a timing controller 110, a voltage generator 120, a gate driver 130, a source driver 140, and a liquid crystal panel 150.

The liquid crystal panel 150 is formed in a plurality of gate lines G1 -Gn, a plurality of data lines D1 -Dm intersecting the gate lines, and regions formed by the gate lines and the data lines, respectively. Including pixels, the pixels are arranged in a matrix structure.

Each pixel includes a thin film transistor T1 having a gate electrode and a source electrode connected to a gate line and a data line, and a liquid crystal capacitor Clc and a storage capacitor Cst connected to a drain electrode of the thin film transistor T1. . In this pixel structure, the gate lines are sequentially selected by the gate driver 130, and when the gate-on voltage is applied in the form of a pulse to the selected gate line, the thin film transistor T1 of the pixel connected to the gate line is turned on. Subsequently, a voltage including pixel information is applied to each data line by the source driver 140. This voltage is applied to the liquid crystal capacitor Clc and the storage capacitor Cst through the thin film transistor of the corresponding pixel, and the predetermined display operation is performed by driving the liquid crystal and the storage capacitors Clc and Cst.

The timing controller 110 receives the pixel data RGB, the horizontal synchronizing signal H_SYNC, the vertical synchronizing signal V_SYNC, the clock signal MCLK, and the data enable signal DE input from an external device. The timing controller 110 outputs the driving pixel data RGB ′ and the control signals CTRL1 obtained by converting the data format to match the interface specification with the source driver 140 to the source driver 140. The control signals CTRL1 include a start horizontal start signal, a clock signal, and a line latch signal.

In addition, the timing controller 110 outputs control signals CTRL2 such as a start vertical signal, a gate clock signal, and an output enable signal to the gate driver 130.

The source driver 140 may drive signals for driving the data lines D1 -Dm of the liquid crystal panel 150 in response to the driving pixel data RGB ′ and the control signals CTRL1 provided from the timing controller 110. Occurs. In general, the source driver 140 is composed of a plurality of integrated circuits.

The gate driver 130 sequentially scans the gate lines G1 -Gn of the liquid crystal panel 150 in response to the control signals CTRL2 provided from the timing controller 110. Here, scanning refers to sequentially applying the gate-on voltage VON to the gate lines to make the pixel of the gate line to which the gate-on voltage VON is applied to enable data writing.

The voltage generator 120 converts the power supply voltage VDD provided from the outside into various voltages necessary for the operation of the liquid crystal display 100, that is, the gate on voltage VON, the gate off voltage VOFF, and the analog power voltage AVDD. Etc. The gate on voltage VON and the gate off voltage VOFF are provided to the gate driver 130, and the analog power supply voltage AVDD is provided to the source driver 130 and the gate driver 130.

The voltage generator 120 according to the exemplary embodiment of the present invention generates a gate-on voltage VON that may reduce the kickback voltage Vk in response to the kickback signal KB from the timing controller 110.

Kickback voltage (Vk) is a parasitic capacitance (Cgs) existing between the gate and the source of the thin film transistor (T1) when the potential of the gate voltage is switched from the gate-on voltage (VON) to the gate-off voltage (VOFF) has a sharp amount of charge If necessary, the liquid crystal is charged in the liquid crystal capacitor Clc or the storage capacitor Cst, and a portion of the charge is generated by the parasitic capacitance Cgs. The magnitude thereof may be expressed by Equation 1 below.

That is, the kickback voltage Vk increases in proportion to the difference between the gate on voltage VON and the gate off voltage VOFF. The voltage generator 120 of the present invention reduces the kickback voltage Vk by reducing the difference between the gate-on voltage VON and the gate-off voltage VOFF.

FIG. 2 is a diagram illustrating a kickback compensation circuit 200 according to an exemplary embodiment of the present invention configured in the voltage generator 120 illustrated in FIG. 1. In the present specification, the kickback compensation circuit 200 is configured in the voltage generator 120, but the kickback compensation circuit 200 may be configured as an independent circuit separately from the voltage generator 120.

Referring to FIG. 2, the kickback compensation circuit 200 includes a discharge circuit 202, an operational amplifier 260, resistors 270 and 280, and a zener diode 290. The discharge circuit 202 sets the gate-on voltage VON of the first voltage level VON1 to the second voltage level VON2 in response to the kickback signal KB from the timing controller 110 shown in FIG. 1. Discharge.

The discharge circuit 202 includes resistors 210, 230, 250, transistor 220, and capacitor 240. One end of the resistor 210 is connected to the gate-on voltage VON. The transistor 220 includes a collector terminal, an emitter terminal, and a base terminal connected to the other end of the resistor 210. The resistor 230 has one end connected to the base terminal of the transistor 220 and the other end connected to the emitter terminal and the ground voltage. The capacitor 240 has one end and the other end connected to the base terminal of the transistor 220. The resistor 250 is connected between the other end of the capacitor 240 and the kickback signal KB from the timing controller 110.

Resistors 270 and 280 are sequentially connected in series between analog supply voltage AVDD and ground voltage and operate as voltage dividers. The operational amplifier 260 has a non-inverting input terminal, an inverting input terminal and an output terminal connected with the connection node of the resistors 270 and 280. The operational amplifier 260 is a voltage follow type amplifier in which an inverting input terminal and an output terminal are connected. Therefore, the analog power supply voltage AVDD is divided by the resistors 270 and 280, and the divided voltage is supplied to the emitter terminal of the transistor 220 and the other end of the resistor 230.

Here, the gate-on voltage VON and the analog power supply voltage AVDD are voltages generated by the voltage generator 120 shown in FIG. 1. The gate-on voltage VON is, for example, 25V as the first voltage level VON1, and the analog power supply voltage AVDD is, for example, 12-15V as a power supply voltage for driving the data driver 140 and the like. By adjusting the resistance values of the resistors 270 and 280, the voltage at the output terminal of the operational amplifier 260 is, for example, 10V at the second voltage level VON2 lower than the analog power supply voltage AVDD.

A detailed operation of the kickback compensation circuit 200 shown in FIG. 2 will be described in detail with reference to the timing diagram shown in FIG. 3. FIG. 3 is a timing diagram illustrating that the difference between the gate on voltage VON and the gate off voltage VOFF is reduced by the kickback compensation circuit 200 shown in FIG. 2.

Referring to FIG. 3, while the kickback signal KB is in an inactive level, that is, a low level, the base terminal voltage of the transistor 200 is equal to the emitter terminal voltage, that is, the output terminal voltage of the operational amplifier 260, that is, the second voltage. Transistor 220 is turned off since it has level VON2. Therefore, the gate-on voltage VON maintains the first voltage level VON1.

While the kickback signal KB is at an active level, that is, at a high level, the voltage of the base terminal of the transistor 220 through the capacitor 240 is reduced to the second voltage level VON2 and the kickback signal KB output from the operational amplifier 260. Rises to the sum of the voltage levels. The kickback signal KB has a transistor-transistor logic (TTL) level, for example, the voltage at the active level is 3.3V. Therefore, the voltage at the base terminal of the transistor 220 rises to the third voltage level VON2 + 0.3V while the kickback signal KB is at the active level.

As the base terminal voltage of the transistor 220 rises, the transistor 220 is turned on and the gate-on voltage VON is dissipated to the second voltage level VON2 output from the operational amplifier 260 through the resistor 210. It is charged.

After the kickback signal KB transitions from the low level to the high level, the shorter the time Td it takes for the gate-on voltage VON to decrease from the first voltage level VON1 to the second voltage level VON2, the shorter the time Td is. Effective for reducing kickback voltage. In the exemplary embodiment of the present invention, the gate-on voltage VON is lowered to the second voltage level VON2 by using the voltage divider including the resistors 270 and 280 and the operational amplifier 260, but the gate-on voltage VON is reduced. You can speed up the descent of).

As the gate-on voltage VON is periodically lowered from the first voltage level VON1 to the analog power voltage AVDD, the gate-on voltage VON and the gate-off voltage VOFF provided to the gate lines G1 -Gn are provided. ), The first voltage difference VON1-VOFF is reduced to the second voltage difference VON2-VOFF at the time when the kickback voltage Vk occurs. As the voltage difference between the gate on voltage VON and the gate off voltage VOFF decreases, the kickback voltage Vk decreases.

As a result, the degradation of the screen quality due to the kickback voltage can be reduced. Furthermore, the kickback voltage Vk can be further lowered by rapidly changing the falling slope of the gate-on voltage VON.

FIG. 4 is a diagram illustrating a time Td required for the gate-on voltage VON to be lowered from the first voltage level VON1 to the second voltage level VON2 by the kickback compensation circuit according to an exemplary embodiment of the present invention. . In the example shown in FIG. 4, the time Td is short, about 0.8 ms. In other words, the gate-on voltage VON is lowered from the first voltage level VON1 to the second voltage level VON2 within about 0.8 mA. Since the time for which the gate-on voltage VON is maintained at the first voltage level VON1 becomes longer, the charging time of the liquid crystal capacitor Clc and the storage capacitor Cst on the liquid crystal panel 150 is guaranteed. Therefore, even if the kickback voltage is lowered, it is possible to minimize the decrease in the charge rate.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications may be made without departing from the technical spirit of the present invention. .

According to the present invention as described above, when the driving voltage for activating the gate line is changed from the gate on voltage to the gate off voltage, the voltage change width is reduced to lower the kickback voltage. As a result, the quality of the image displayed on the screen is improved.

Claims (3)

A liquid crystal panel comprising a plurality of gate lines; A timing controller for outputting kickback signals and control signals having a predetermined period; A voltage generator for generating a gate-on voltage and a first power supply voltage of a first voltage level; And A gate driver sequentially providing the gate-on voltage to the plurality of gate lines of the liquid crystal panel in response to the control signals; The voltage generator, A discharge circuit lowering the gate-on voltage to a voltage at a second voltage level lower than the first voltage level in response to the kickback signal; A voltage divider coupled between the first power supply voltage and a ground voltage; And Kickback compensation comprising an inverting input stage, a non-inverting input stage connected to the voltage divided by the voltage divider, and an operational amplifier connected to the inverting input stage and the discharge circuit and outputting a voltage of the second voltage level. A liquid crystal display device comprising a circuit. The method of claim 1, The discharge circuit, A first resistor having one end connected to the gate on voltage; A transistor having a first terminal, a second terminal, and a third terminal connected to the first resistor; A capacitor coupled between the third terminal of the transistor and the kickback signal; And And a second resistor having one end connected to the third terminal of the transistor and the other end connected in common to the second terminal of the transistor and the output terminal of the operational amplifier. The method of claim 1, The voltage divider, At least two resistors connected in series between the first supply voltage and a ground voltage; And the connection node of the resistors is connected to a non-inverting input terminal of the amplifier.

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