KR20070072009A - Liquid crystal display device and method driving for the same - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to prevent degradation of image quality occurring in a conventional liquid crystal display by supplying a start pulse signal in advance during a blank period between frames. A liquid crystal display includes a gate driver for sequentially driving a plurality of gate lines on a liquid crystal panel, and a gate control signal generating unit(115) for supplying a gate start pulse having a portion of a blank period to the date driver. The gate control signal generating unit includes a register(120) for storing a reference value on the start time of a start pulse signal in a blank period of a vertical synchronization signal, a counter(118) for counting a number during the blank period, a comparing unit(122) for comparing the counted value with the reference value, and a mono-stable multi-vibrator(124) for generating a start pulse signal having a constant width in response to the output of the comparing unit.

Description

Liquid crystal display device and method driving for the same

1 is a view showing a conventional liquid crystal display device.

FIG. 2 is a diagram illustrating a driving voltage of the gate driver of FIG. 1. FIG.

3 is a view showing a liquid crystal display device according to the present invention.

4 is a detailed view illustrating a gate control signal generator of FIG. 3.

5 is a diagram illustrating a driving voltage of the gate driver of FIG. 3;

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

106a: first data driver IC 106b: second data driver IC

107a: first data TCP 107b: second data TCP

108: timing controller

110-1 to 110-n: first to nth shift registers

112: data PCB 114: control unit

115: gate control signal generator 116: level shifter

118: counter 120: register

122: comparison unit 124: monostable multivibrator

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving image quality.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), and electro luminescent display (ELD) have been studied, and some of them have already been used as display devices in various devices.

Among them, LCD (hereinafter referred to as 'liquid crystal display device') is most widely used as a substitute for CRTs for mobile image display devices due to its excellent image quality, light weight, thinness, and low power consumption. In addition to mobile applications such as monitors of notebook computers, liquid crystal displays have been developed in various ways such as television monitors.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and the image information can be expressed by changing the polarization state of light in the molecular arrangement direction of the liquid crystal by optical anisotropy.

1 is a view showing a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2 displaying a predetermined image, a data PCB 12 provided on one side of the liquid crystal panel 2, and the data PCB 12. ) And a plurality of data TCPs 7a and 7b connected between the liquid crystal panel 2 and a plurality of data driver ICs 6a and 6b mounted inside the plurality of data TCPs 7a and 7b, and the liquid crystal. Control supplied from the timing controller 8 and the timing controller 8 for generating a gate driver 4 provided on the other side of the panel 2 and a predetermined control signal mounted in the data PCB 12. And a level shifter 16 for generating a predetermined voltage using the signal.

Since the liquid crystal display is a well known technique, a detailed description thereof will be omitted.

As described above, the liquid crystal display device configured as described above has a gate in panel (GIP) structure in which the gate driver 4 is formed on the first substrate of the liquid crystal panel 2. In addition, the liquid crystal panel 2 is formed of a storage on gate method.

FIG. 2 is a diagram illustrating a driving voltage of the gate driver of FIG. 1.

As shown in FIGS. 1 and 2, the gate driver 4 includes first to nth gate high voltages synchronized with the start pulse Vst signal and the start pulse Vst signal from the level shifter 16. (VGH-1 to VGH-n) are supplied to the plurality of gate lines GL1 to GLn.

In particular, the start pulse Vst signal is generated in synchronization with a data enable signal DE, and a high section of the data enable signal DE is transmitted to the plurality of data lines DL1 to DLm. Is supplied and displayed on the liquid crystal panel 2. The data enable DE signal has a high section corresponding to the number of gate lines GL1 to GLn arranged in the liquid crystal panel 2 during one frame.

The start pulse Vst signal is generated in synchronization with a first high section of the data enable signal DE. The start pulse Vst signal has a high section for one horizontal section 1H and is synchronized with a falling time of the start pulse Vst signal to the first gate line GL1 in response to a falling time. The high voltage VGH is supplied.

Since the first gate high voltage VGH is supplied to the first gate line GL1 in synchronization with the start pulse Vst signal, the first gate high voltage VGH-1 is applied to the start pulse Vst signal. Not ahead.

Subsequently, a second gate high voltage VGH-2 is sequentially supplied to the second gate line GL2, and the second gate high voltage VGH-2 is synchronized with the first gate high voltage VGH-1. And the second gate line GL2 is supplied to the second gate line GL2.

The second gate high voltage VGH-2 is supplied during two horizontal sections 2H to secure a charging time of the thin film transistor TFT connected to the second gate line GL2. In order to prevent an image corresponding to an undesired data signal from being displayed on the liquid crystal panel 2 due to insufficient charge time of the thin film transistor TFT connected to the second gate line GL2, the second gate line ( GL2) supplies the second gate high voltage VGH-2 corresponding to the two horizontal sections 2H.

The gate high voltage having a high section during the two horizontal sections 2H is supplied to not only the second gate line GL2 but also the remaining gate lines GL2 to GLn except the first gate line GL1. .

The first gate high voltage VGH-1 is synchronized with a falling time of the start pulse Vst signal and simultaneously with a first high period of the data enable signal DE. Therefore, the first gate line GL1 is supplied to the first gate line GL1 during one horizontal section 1H.

That is, the first gate high voltage VGH-1 is supplied to the first gate line GL1 for one horizontal section 1H, and the remaining gate lines GL2 to GLn except for the first gate line GL1 are provided. The second to nth gate high voltages VGH-2 to VGH-n are supplied to the second horizontal section 2H. As a result, the charging time of the thin film transistor TFT connected to the first gate line GL1 is shorter than the charging time of the thin film transistor TFT connected to the second to nth gate lines GL2 to GLn.

For example, when a black screen is displayed on the liquid crystal panel 2, the portion where the first gate line GL1 is positioned is brighter than the portion where the second to nth gate lines GL2 to GLn are positioned.

In more detail, the data signal charged in the storage capacitor Cst overlapping with the first gate line GL1 is formed in the storage capacitor Cst overlapping with the second to nth gate lines GL2 to GLn. It becomes smaller than the charged data signal. Therefore, the portion where the first gate line GL1 is positioned is brighter than the portion where the second to nth gate lines GL2 to GLn are positioned.

Due to this phenomenon, there is a problem that the image quality is deteriorated due to the band-like brightness of the upper portion of the screen.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display and a driving method thereof which can improve image quality by supplying a start pulse signal to a gate driver in advance during a blank period.

The liquid crystal display according to the present invention for achieving the above object generates a gate control signal for supplying a gate start pulse including a portion of a blank period and a gate driver for sequentially driving a plurality of gate lines on the liquid crystal panel to the gate driver Contains wealth.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the liquid crystal display device including a liquid crystal panel having a plurality of gate lines and data lines arranged thereon, the gate start pulse signal including a part of a blank period. Supplying and sequentially driving a plurality of gate lines in synchronization with the gate start pulse signal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention.

3 is a view showing a liquid crystal display according to the present invention.

As shown in FIG. 3, the liquid crystal display of the present invention includes a liquid crystal panel 102 for displaying a predetermined image, a data PCB 112 provided on one side of the liquid crystal panel 102, and the liquid crystal panel. A plurality of data TCPs 107a and 107b connected between the 102 and the data PCB 112, a plurality of data driver ICs 106a and 106b mounted in the plurality of data TCPs 107a and 107b, respectively; And a gate driver 104 provided on the other side of the liquid crystal panel 102.

As described above, the liquid crystal display configured as described above has a gate in panel (GIP) structure in which the gate driver 104 is formed on the first substrate of the liquid crystal panel 102. In addition, the liquid crystal panel 102 is formed of a storage on gate method.

The liquid crystal panel 102 includes a plurality of gate lines GL0 to GLn, a plurality of data lines DL1 to DLm arranged in a direction perpendicular to the gate lines GL0 to GLn, and the gate lines GL0 to GLn. ) And a thin film transistor TFT connected to the data lines DL1 to DLm, a pixel electrode connected to the thin film transistor TFT, and a storage capacitor Cst formed between the pixel electrode and the front gate line. It is provided.

In addition, the liquid crystal panel 102 includes first and second substrates and liquid crystal injected between the first and second substrates. The gate driver 104 may be embedded on the first substrate to reduce manufacturing cost.

The timing controller 108 generates a predetermined control signal in the data PCB 112, and the gate control signal generates a gate control signal using a blank control signal and a clock signal supplied from the timing controller 108. The controller 114 including the generator 115 and a level shifter 116 for generating a start pulse (SP) signal and predetermined voltages using the predetermined control signal are mounted.

The gate driver 104 is formed on the first substrate, as mentioned above. The gate driver 104 includes n shift registers 110-1 to 110-n corresponding to the gate lines GL1 to GLn.

The n shift registers 110-1 to 110-n correspond to the gate lines GL1 to GLn and are formed of a plurality of thin film transistors TFT.

The timing controller 108 generates a predetermined control signal using a vertical / horizontal synchronization signal (Vsync / Hsync), a data enable (DE) signal, and a predetermined clock signal supplied from a system (not shown). In addition, the vertical / horizontal synchronization signal Vsync / Hsync supplied from the system is supplied to the gate control signal generator 115.

The gate control signal generator 115 generates a gate control signal using the vertical / horizontal synchronization signal (Vsync / Hsync).

As shown in FIG. 4, the gate control signal generator 115 includes a counter 118 that counts the number of horizontal sync signals Hsync during the blank period of the vertical sync signal Vsync supplied from the system. The gate control signal is obtained by comparing a register 120 indicating a time point at which the start pulse Vst signal is output during the blank period, and a value counted from the counter 118 and a time point stored in the register 120. And a monostable multivibrator 124 for outputting to increase the width of the gate control signal generated by the comparator 122.

More specifically described as follows.

A counter 118 for inputting a horizontal synchronizing signal and a vertical synchronizing signal is provided. The counter 118 is reset between the syringes of the vertical synchronizing signal and the number of times of input of the horizontal synchronizing signal Hsync in the blank period (or also referred to as the "erasing period") of the vertical synchronizing signal Vsync. Counts. In other words, it is reset by the high potential pulse of the vertical synchronization signal Vsync (ie, the vertical scanning period), and then while the vertical synchronization signal Vsync maintains the low potential (ie, the blank period). The count value is increased by " 1 " for each rising or falling edge of the horizontal synchronization signal Hsync. The counted value is supplied to the comparator 122.

The comparator 122 compares the count value from the counter 118 with a reference value stored in the register 120. Here, the reference value stored in the register 120 is set to a value smaller by "1" than the number of horizontal synchronization signals Hsync included in the blank period of the vertical synchronization signal Vsync. In this case, the counter 118 increases the count value by "1" at the end of the horizontal sync signal Hsync.

On the contrary, when the counter 118 increments the count value by "1" at the start of the horizontal synchronization signal Hsync, the reference value stored in the register 120 is blank period Blnak of the vertical synchronization signal Vsync. It is set to the same value as the number of horizontal sync signal (Hsync) included in. If the count value from the count 118 is equal to the reference value stored in the register 120, the comparator 122 generates a comparison signal having a pulse of a specific logic (for example, a pulse of high or low logic). The pulse of the comparison signal generated by the comparator 122 has a width corresponding to the period of the horizontal synchronization signal Hsync.

The monostable multivibrator 124 which inputs the comparison signal from the comparator 122 generates a high logic gate start pulse having a width corresponding to the period of two horizontal synchronization signals from the time point of the pulse of the comparison signal. The generated gate start pulse is level shifted by the level shifter 116 of FIG. 3 to have an amplitude of a high potential corresponding to the gate high voltage VGH.

The level shifter 126 supplies the gate driver 104 with a start pulse (Vst) signal that amplifies the gate control signal having the increased width to a desired voltage.

The gate driver 104 is sequentially driven by a plurality of gate lines GL1 to GLn connected to the gate driver 104 by being driven by the start pulse Vst signal in the blank period. Supply a high voltage (VGH).

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a counter 118 for counting a horizontal sync signal Hsync during a blank period, which is a preparation period between frames, a register 120 for storing the reference value, and the counter. A comparator 122 for outputting a gate control signal by comparing the number of horizontal sync signals Hsync counted at 118 with the reference value is separately provided.

Accordingly, the start pulse Vst signal is output to the gate driver 104 during the blank period, and the gate driver 104 is synchronized with a falling time of the start pulse Vst signal. The scan signal is supplied to the plurality of gate lines GL1 to GLn.

As shown in FIG. 5 in synchronization with a falling time of the start pulse Vst signal supplied to the gate driver 104, a first frame starts after the blank period. The gate high voltage VGH-1 is supplied to the first gate line GL1.

In this case, the first gate high voltage VGH-1 is supplied to the first gate line GL1 for two horizontal sections 2H. This is to secure the charging time of the thin film transistor TFT connected to the plurality of gate lines GL1 to GLn as mentioned above.

Accordingly, the gate high voltage VGH is supplied to each of the plurality of gate lines GL1 to GLn arranged on the liquid crystal panel 102 for two horizontal sections 2H so that the same gray level is applied to the liquid crystal panel 102. When it is displayed, the phenomenon in which the upper portion of the liquid crystal panel 102 looks bright as in the prior art does not occur.

A thin film transistor connected to the plurality of gate lines GL1 to GLn by supplying a gate high voltage VGH having the same level to the plurality of gate lines GL1 to GLn at the same time, that is, for two horizontal sections 2H. The charging time of the TFTs becomes equal to each other.

When the thin film transistors TFT connected to the plurality of gate lines GL1 to GLn have the same charging time, the storage capacitor Cst in which data signals supplied to the plurality of data lines DL1 to DLm are formed on each pixel area is formed. ), The charging time becomes the same. As a result, the same gray level may be displayed on the liquid crystal panel 102.

As a result, the liquid crystal display according to the present invention can prevent the deterioration of the image quality caused by the conventional liquid crystal display device and improve the image quality by supplying the start pulse (Vst) signal to the gate driver in advance during the blank period.

As described above, the liquid crystal display according to the present invention supplies a start pulse (Vst) signal to the gate driver in advance during a blank period, which is a frame-to-frame period, to reduce image quality deterioration generated in the conventional liquid crystal display device. Prevent and improve image quality.

Claims (6)

A gate driver for sequentially driving a plurality of gate lines on the liquid crystal panel; And And a gate control signal generator for supplying a gate start pulse including a part of a blank period to the gate driver. The method of claim 1, The gate control signal generator, A register having a reference value stored at a start time of a start pulse signal in a blank period of the vertical synchronization signal; A counter that counts during the blank period of the vertical synchronization signal; A comparison unit comparing the count value and the reference value; And And a monostable multivibrator for generating a start pulse signal having a constant width in response to the output of the comparator. The method of claim 2, And the reference value is set to a value smaller by "1" than the number of horizontal synchronization signals included in the blank period, and the counter counts an increment of "1" at the end of the horizontal synchronization signal. The method of claim 2, Wherein the reference value is equal to the number of horizontal synchronization signals included in the blank period and the counter counts an increment of " 1 " at the start of the horizontal synchronization signal. The method of claim 1, And a level shift for shifting the voltage level from the gate control signal generator high. A liquid crystal display comprising a liquid crystal panel in which a plurality of gate lines and data lines are arranged. Supplying a gate start pulse signal including a portion of the blank period; And And sequentially driving a plurality of gate lines in synchronization with the gate start pulse signal.

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