KR20070071320A - Fabrication method of poly-silicon layer and fabrication method of thin film transistor and organic electroluminescence display device using it - Google Patents

Abstract

A method for fabricating a polysilicon layer is provided to reduce hysteresis of a TFT device by forming a polysilicon layer by a crystallization process after ionized inert element is implanted into an amorphous silicon layer. An amorphous silicon layer(220) is formed on a substrate(200). An ionized inert element is implanted into the amorphous silicon layer. The amorphous silicon layer into which the ionized inert element is implanted is crystallized at a temperature of 600~800 °C. The ionized inert element can be one selected from He, Ar, Kr and Xe, having a dosage of 1x10^13-1x10^15 ions/centimeter^2.

Description

Fabrication method of polysilicon film, manufacturing method of thin film transistor and organic light emitting display device using the same {Fabrication method of poly-silicon layer and fabrication method of Thin Film Transistor and organic electroluminescence display device using it}

Figure 1a and 1b is a process cross-sectional view showing a polysilicon crystallization method according to the conventional SPC crystallization.

Figure 2 is a flow chart showing a polysilicon crystallization method according to the SPC crystallization of the present invention.

Figure 3a to 3c is a cross-sectional view showing a polysilicon crystallization method according to the SPC crystallization of the present invention.

4A to 4G are cross-sectional views illustrating a method of manufacturing a thin film transistor having a PMOS using a polysilicon crystallization method according to SPC crystallization according to the present invention.

5A through 5D are cross-sectional views illustrating a method of manufacturing an organic light emitting display device having a PMOS using the polysilicon thin film transistor manufactured in FIG. 4.

6 is a cross-sectional view of a PMOS polysilicon thin film transistor according to Experimental Example and Comparative Example of the present invention.

7 is a diagram illustrating hysteresis characteristics of a thin film transistor fabricated using a conventional polysilicon crystallization method.

8 is a diagram illustrating hysteresis characteristics of a thin film transistor fabricated using a polysilicon crystallization method according to an experimental example of the present invention.

<Description of Signs of Major Parts of Drawings>

200, 300, 500: substrate 210, 310, 510: buffer layer

220, 320: amorphous silicon film 230, 325: impurities

220 ', 320', 520 ': polysilicon film 320': active layer

330 and 530: gate insulating film 340 and 540: gate electrode

350: interlayer insulating film 355: contact hole

360: source electrode 365: drain electrode

370: protective layer 375: via hole

380: First electrode 385: Bank

390 organic layer 395 second electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polysilicon film and a method for manufacturing a thin film transistor and an organic light emitting display device using the same. In particular, a polysilicon film is formed by injecting an inert element ionized into an amorphous silicon film and crystallizing to form a polysilicon film. The present invention relates to a method of manufacturing a polysilicon film capable of reducing the threshold voltage fluctuation, ie, hysteresis (ΔVth), of a stir element and a method of manufacturing a thin film transistor and an organic light emitting display device using the same.

 Recently, as the information society has evolved rapidly, the need for a flat panel display having excellent characteristics such as thinness, light weight, and low power consumption has emerged. Among them, organic electroluminescence display (OLED) Device) is self-luminous, has a wide viewing angle, fast response speed, thin thickness, low manufacturing cost, and high contrast, and is drawing attention as a next-generation flat panel display device.

In general, an organic light emitting diode includes an organic light emitting layer between an anode electrode and a cathode electrode so that holes supplied from the anode electrode and electrons supplied from the cathode electrode combine in the organic light emitting layer to form an exciton which is a hole-electron pair, and again The excitons emit light by energy generated when the excitons return to the ground state.

In general, organic light emitting diodes are classified into a passive matrix method and an active matrix method according to a method of driving N × M pixels arranged in a matrix form. In the active matrix method, a pixel electrode defining a light emitting area and a unit pixel driving circuit for applying a current or voltage to the pixel electrode are positioned in a unit pixel area, and the unit pixel driving circuit includes at least one thin film transistor (TFT). Thin Film Transistor).

The thin film transistor (TFT) generally includes an active layer, a gate electrode, a source electrode, and a drain electrode, wherein the active layer includes a source region and a drain region and a channel region interposed between the source region and the drain region. It is provided.

The active layer may be formed of amorphous silicon or polysilicon, but the polysilicon film may be applied to a high field effect mobility and a high speed operation circuit, and may have a CMOS circuit configuration. It is widely used as an active layer use for transistors. Thin film transistors using such polysilicon films are mainly used in active devices of active matrix liquid crystal display devices (AMLCDs) and switching devices and driving devices of organic light emitting display devices (OLEDs).

In general, MOS (Metal Oxide Semiconductor) is divided into NMOS or PMOS by the method of implanting impurities into the n-channel (p) and p-channel, the active matrix organic electroluminescent device using a thin film transistor having a PMOS mainly In addition, since the polysilicon TFT can directly drive the drive IC together on the TFT array substrate, the polysilicon TFT has an advantage of excellent directness and price competitiveness.

In order to form the active layer used in the TFT as a thin film of polysilicon, pure amorphous silicon (Intrinsic amorphous silicon) is a predetermined method, that is, plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition on the insulating substrate A method of depositing an amorphous silicon film by low pressure chemical vapor deposition (LPCVD) and then crystallizing it again was used.

The crystallization is an excimer laser annealing method (ELA method) which crystallizes amorphous silicon by applying a heat of an excimer laser which is a high power pulse laser instantaneously, and a furnace heating method in a furnace. Solid phase crystallization (SPC method), crystallization of amorphous silicon using the sequential lateral solidification (SLS) method using energy of the complete melting region, or selective deposition of metal on the amorphous silicon film After the heat treatment may be selected from metal induced crystallization (MIC; Metal Induced Crystallization) to induce crystallization occurs by the metal (seed).

 The SPC method is a solid phase crystal method, which is a method of crystallizing an amorphous silicon film at a high temperature (600 ° C. or more) within 20 minutes to 1 hour, and is widely used as a low cost heat treatment method.

Figure 1a and 1b is a cross-sectional view showing a polysilicon crystallization method according to the conventional SPC crystallization.

In the polysilicon crystallization method, as shown in FIG. 1A, a silicon oxide layer (SiO ₂ ) or a silicon nitride layer (SiNx) is deposited on the entire surface of the glass substrate 100 by PECVD or LPCVD to form a buffer layer 110. The amorphous silicon film 120 is formed by depositing amorphous silicon on the buffer layer 110 using a method such as PECVD, LPCVD, or sputtering.

Referring to FIG. 1B, the amorphous silicon film 120 is crystallized at a high temperature of 600 ° C. or higher (600 ° C. or more) for 20 minutes to 1 hour using heat treatment equipment to be converted into a polysilicon film 120 ′. In this case, a plurality of crystal defects 130 exist in the grains of the polysilicon film 120 ′.

Crystallization using the SPC method utilizes the principle of phase transition from amorphous silicon (a-Si) in the solid phase to polysilion in the solid phase by thermal energy.

In the conventional SPC polycrystallization method, crystals of crystallized grains containing a large amount of seeds are small due to the difference in phase transition mechanism, and crystals are crystallized in grains of the crystallized polysilicon film 120 '. A large number of defects 130 will be included. Due to this defect, the threshold voltage (Vth) when the gate voltage is switched from the on state to the off state (on-> off) and the threshold voltage when the gate voltage is switched from the off state to the off state (off-> on) The hysteresis ΔVth defined by the difference of Vth is large, causing an afterimage on the panel, thereby degrading the quality of the screen.

Therefore, for the active matrix organic light emitting display device, it is required that the hysteresis (ΔVth) of the polysilicon thin film transistor is small.

A method of improving the device characteristics of a polysilicon thin film transistor by performing heat treatment for a long time is generally known, but this has a limitation that cannot be applied to production because it increases the process time.

Disclosure of Invention An object of the present invention is to provide a polysilicon manufacturing method capable of reducing the threshold voltage variation of a thin film transistor, that is, hysteresis (ΔVth), and a method of manufacturing a thin film transistor and an organic light emitting display device using the same.

In order to achieve the above object, the polysilicon film manufacturing method according to the present invention comprises the steps of: forming an amorphous silicon film on a substrate, implanting an ionized inert element on the amorphous silicon film, and crystallizing the amorphous silicon film Characterized in that it comprises a step.

In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes forming an amorphous silicon film on a substrate, implanting an ionized inert element onto the amorphous silicon film, and implanting the ionized inactive element. Crystallizing the amorphous silicon film to form a polysilicon film, patterning the polysilicon film to form an active layer, patterning and forming a gate electrode on the active layer, and forming the gate electrode on the active layer as a mask Implanting impurities to define a source region, a drain region, and a channel region between the source region and the drain region, and forming a source electrode and a drain electrode on the gate electrode.

In addition, the organic light emitting display device according to the present invention in order to achieve the above object, forming a substrate amorphous silicon film, implanting an ionized inert element on the amorphous silicon film, the ionized inert element is implanted Crystallizing the amorphous silicon film to form a polysilicon film, patterning the polysilicon film to form an active layer, patterning and forming a gate electrode on the active layer, and masking the gate electrode on the active layer Implanting an impurity to define a source region, a drain region, and a channel region between the source region and the drain region, forming a source electrode and a drain electrode on the gate electrode, and electrically connecting the drain electrode. Forming a first electrode, at least an organic layer on said first electrode Forming an organic layer consisting of a layer, and is characterized in that it comprises a step of forming a second electrode on the organic layer.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

Figure 2 is a flow chart showing a polysilicon crystallization method according to the SPC crystallization of the present invention, Figure 3a to 3c is a process cross-sectional view showing a polysilicon crystallization method according to the SPC crystallization of the present invention.

2, in the polysilicon crystallization method according to SPC crystallization of the present invention, a buffer layer is formed of a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiNx) on a substrate, and amorphous silicon is formed on the buffer layer. Forming a film (S10), implanting an ionized inert element onto the amorphous silicon film (S20), and crystallizing the amorphous silicon film into which the ionized inert element is implanted at a high temperature to crystallize (S30). Is done.

The polysilicon crystallization method according to the present invention will be described in more detail with reference to FIGS. 3A to 3C.

Referring to FIG. 3A, a silicon oxide layer (SiO ₂ ) or a silicon nitride layer (SiNx) is deposited on a substrate 200 by PECVD or LPCVD to form a buffer layer 210, and amorphous silicon is deposited on the buffer layer 210. The amorphous silicon film 220 is formed by depositing by PECVD or LPCVD.

The buffer layer 210 is formed to protect the thin film transistor formed in a subsequent process from impurities flowing out of the substrate 200.

Referring to FIG. 3B, an ionized inactive element 230 is implanted onto the amorphous silicon film 220. In this case, the implanted inert element is located at the interface between the buffer layer 210 and the amorphous silicon film 220.

Here, the ionized inert element (group 0 element) 230 is formed of one selected from helium (He), neon (Ne), argon (Ar), chromium (Kr), and xenon (Xe). In general, argon (Ar) ions are implanted in consideration of the mass of an atom. At this time, a material having a mass larger than xenon (Xe) among the inactive elements is not well implanted, but the amorphous silicon film 220 is injected even if implanted. Limit it because it can destroy it.

The dose of the ionized inert element 230 is in the range of 1x10 ¹³ to 1x10 ¹⁵ ions / cm 2. If the dose amount is equal to or less than 1x10 ¹³ ions / ㎠ it has no effect by the impurity implantation, when greater than 1x10 ¹⁵ ions / ㎠ may crystallization is not formed correctly.

When the ionized inactive element 230 is injected, the acceleration voltage is in the range of 10 to 100 KeV. In general, the amorphous silicon film 220 is formed to be about 300 to 600 kW, and the acceleration voltage depends on the thickness of the amorphous silicon film 220, so that the penetration range of the ionized inactive element 230 is appropriately adjusted. It is formed on the amorphous silicon film 220.

In the present invention, it will be described by injecting an argon cation (Ar +). Since the argon cation (Ar +) 230 injected into the amorphous silicon film 220 has a large mass, it maintains a contact trapping state at an interface between the buffer layer 210 and the amorphous silicon film 220 and is inactive. Because it is an element, no chemical action occurs in the membrane.

Referring to FIG. 3C, the amorphous silicon film 220 into which the argon cation (Ar +) 230 is injected is heat-treated at 600 ° C. to 800 ° C. or higher to crystallize the polysilicon film 220 ′ in FIG. 2. The crystallization uses an SPC method in which amorphous silicon is crystallized using a furnace heating method in a furnace.

When the polysilicon layer 220 'is formed, the implanted argon cation (Ar +) reduces seeds by ion implantation damage, thereby reducing the number of crystallinities having poor crystallinity. It also serves to reduce the number of low quality crystals by breaking the micro crystals that can occur at low temperatures and grow to poor crystallinity while raising the temperature to high temperatures for crystallization.

Therefore, the crystal defects in the grains of the polysilicon film 220 'according to the present invention have an effect of reducing as compared with the conventional.

Thereby, the polysilicon manufacturing method by the SPC method of this invention is completed.

As described above, a polysilicon film of good quality can be produced by injecting an inert element ionized into a particularly amorphous silicon film according to the present invention and then crystallizing at a high temperature.

Meanwhile, a method of forming a polysilicon film by injecting an inert element ionized into such an amorphous silicon film and crystallizing it may be very useful for manufacturing a polysilicon thin film transistor and an active matrix organic light emitting display device.

In particular, when the polysilicon film of the PMOS thin film transistor is manufactured by the above method, there is an effect of reducing hysteresis (ΔVth).

Accordingly, when the PMOS thin film transistor is used in an organic light emitting display device, hysteresis ΔVth may be reduced to improve afterimages of the panel.

Next, a brief description will be made of a process of manufacturing a thin film transistor and an organic light emitting display device using the polysilicon manufacturing method. As is known, the process of manufacturing a TFT substrate of an active matrix organic light emitting display device includes a process of manufacturing a thin film transistor, and thus, the process of manufacturing a TFT substrate of a liquid crystal display device will be described here. do.

4A to 4G are cross-sectional views illustrating a method of manufacturing a thin film transistor having a PMOS using a polysilicon crystallization method according to SPC crystallization according to the present invention, and FIGS. 5A to 5D are polysilicon manufactured in FIG. 4. The process cross-sectional view for explaining a method for manufacturing an organic light emitting display device having a PMOS using a thin film transistor.

4A to 4C, a buffer layer 310 is formed on a substrate 300, and an amorphous silicon film 320 is formed on the buffer layer 310 (FIG. 4A).

The ionized inactive element 325 is implanted into the amorphous silicon film 320. The ionized inactive element 325 is located at the interface between the buffer layer 310 and the amorphous silicon film 320 (FIG. 4B).

Subsequently, the amorphous silicon film 320 into which the ionized inert element 325 is implanted is heat-treated at a high temperature (600 ° C.) for 20 minutes to 1 hour by SPC method, thereby providing a high quality polysilicon film without crystal defects in the grains. Crystallize to (320 ').

Since the method of manufacturing the polysilicon layer 320 ′ is the same as that described with reference to FIG. 3, the material and method for forming the buffer layer 310, the amorphous silicon layer 320, and the polysilicon 320 ′ are as shown in FIG. 3. Same as mentioned.

Referring to FIG. 4D, the polysilicon layer 320 'is patterned by dry etching or wet etching using a mask formed in a photolithography process to form an active layer 320'. To form.

Referring to FIG. 4E, a gate oxide layer 330 is formed by depositing a silicon oxide layer or silicon nitride layer on the active layer 320 ′ by PECVD or LPCVD, and sputtering a conductive metal on the gate layer 330. After deposition and patterning by sputtering or evaporation, a gate electrode 340 corresponding to the active layer 320 ′ is formed.

Referring to FIG. 4F, impurities are implanted using the gate electrode 340 as a mask to implant impurities into the active layer 320 ′, the drain region 320 ′ c, and the source. A channel region 320'b interposed between the region 320'a and the drain region 320'c and to which no impurities are injected is defined. The impurity may be an N-type or P-type impurity, and the N-type impurity may be selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), and the P-type impurity Silver may be selected from the group consisting of boron (B), aluminum (Al), potassium (Ga) and indium (In). In the present invention, it will be described as P-type impurities.

Referring to FIG. 4G, a silicon oxide film or a silicon nitride film is deposited on the gate electrode 340 by PECVD or LPCVD to form an interlayer insulating film 350, and then a portion of the interlayer insulating film 350 is etched using a mask. As a result, contact holes 355 are formed to expose portions of the surfaces of the source and drain regions 320'a and 320'c. Subsequently, a conductive metal is deposited on the interlayer insulating layer 350 by sputtering or vacuum deposition, and then patterned using a mask to form the source and drain regions 320 ′ a and 320 ′ c through the contact hole 355. The source electrode 360 and the drain electrode 365 are electrically connected.

As a result, the PMOS thin film transistor TFT including the active layer 320 ', the gate electrode 340, the source electrode 360, and the drain electrode 365 is completed.

 The PMOS thin film transistor using the polysilicon manufacturing method according to the present invention has an effect of reducing hysteresis (ΔVth).

In addition, the organic light emitting display device according to the present invention will be briefly described with reference to FIG. 5. First, referring to FIG. 5, a protective layer 370 is formed by depositing a silicon oxide layer or a silicon nitride layer on the thin film transistor manufactured in FIG. 4 by PECVD or LPCVD method, and then a part of the protective layer 370 is formed by using a mask. The via hole 375 is formed to expose a portion of the surface of the drain electrode 365 by etching. Subsequently, a transparent conductive material is deposited on the protective layer 370 by sputtering or vacuum deposition and then patterned to form a first electrode 380 connected to the drain electrode 365 through the via hole 375.

The first electrode 380 is formed of an anode electrode having a high work function (4.5 eV or more) and a conductive material, and is formed of a transparent electrode made of indium tin oxide (ITO) or indium zinc oxide (IZO).

A bank 385 having an opening and defining a pixel area is formed on the first electrode 380. The bank 385 is formed by spin coating acrylic resin or polyimide.

Subsequently, an organic layer 390 including at least an organic emission layer (EML) is formed on the first electrode 380. The organic light emitting layer may be a low molecular material or a high molecular material. The low molecular weight material is formed of one kind selected from the group consisting of aluminy quinolium complex (Alq3), anthracene (Anthracene), BeBq2, Balq, and DPVBi. The polymer material is poly (p-phenylenevinylene) (PPV; poly (p-phenylenevinylene)) and its derivatives, polythiophene (PT) and its derivatives and polyphenylene (PPP; polyphenylene) and its derivatives It is formed of one selected from the group consisting of.

The organic layer 390 has a hole injection layer (HIL), a hole transport layer (HTL), and electrons to improve device characteristics by smoothly injecting holes and electrons in addition to the organic light emitting layer (EML). The electronic device may further include one or more layers of an ETL (Electron Transport Layer) and an EIL (Electron Injection Layer).

The organic layer 390 is formed by lamination and patterning by a method such as vacuum deposition, spin coating or ink-jet printing, and vacuum deposition using a laser induced thermal imaging (LITI) or shadow mask. To achieve the desired patterning.

On the organic layer 390, a conductive metal having a low work function (below 4.2 eV or less) is deposited by sputtering or vacuum deposition to form a second electrode 395 as a cathode electrode. The second electrode 395 is a material selected from the group consisting of Mg, Ca, Al, Ag, and alloys thereof, and is formed of a reflective electrode having a thick thickness.

The first electrode 380, the organic layer 390, and the second electrode 395 are formed of an organic light emitting diode, and thus an organic light emitting diode employing a PMOS thin film transistor using a polysilicon manufacturing method according to the present invention. Complete the display.

The organic light emitting display device employing the PMOS thin film transistor can reduce the hysteresis (ΔVth) to improve the afterimage of the panel, thereby improving the quality and reliability of the panel.

Hereinafter, one experimental example of the present invention is presented. However, the following experimental examples are provided only for better understanding of the present invention, and the present invention is not limited to the following experimental examples.

Experimental Example

A PMOS polysilicon thin film transistor was fabricated based on the method for producing a polysilicon film according to the present invention.

6 is a cross-sectional view of a PMOS polysilicon thin film transistor according to an experimental example and a comparative example of the present invention.

As illustrated, a PECVD method is performed on the silicon oxide film (SiO ₂ ) on the glass substrate 500 to form a buffer layer 510 having a thickness of 3000 Å, and the PECVD method is performed on the buffer layer 510 in the same chamber. As a result, an amorphous silicon film (not shown) having a thickness of 450 kHz was formed. Subsequently, argon cation (Ar +) is injected into the amorphous silicon film at a dose of 1x10 ¹⁵ ions / cm2 and an acceleration voltage of 10 KeV through another ion implantation device, followed by AMFC (Alternating Magnetic Field Crystallization) (manufacturer: Viatron A polysilicon film (not shown) was formed by heat treatment at 700 ° C. for 20 minutes using a heat treatment equipment.

Subsequently, the polysilicon layer is patterned using a mask to form an active layer, and boron (B) is implanted into the active layer through ion implantation equipment to inject impurities into the source and drain regions 520'a and 520 '. c) and an active layer 520 'formed of a channel region 520'b into which impurities are not implanted, and a gate insulating film 530 having a thickness of 500 Å is formed on the active layer 520' by PECVD. The gate electrode 540 was formed by sequentially depositing Al / Mo on the gate insulating film 530 in a thickness of 3000 Å / 1000 Å by sputtering.

Subsequently, a silicon nitride film is deposited on the gate electrode 540 by a PECVD method to form an interlayer insulating film 550 having a thickness of 2500 kV, and the contact insulating film 550 is etched to form a contact hole 555. Mo / Al / Mo is deposited on the insulating film 550 in a sputtering method to a thickness of 50 μs / 2000 μs / 500 μs in turn and then patterned to form a source electrode 560 and a drain electrode 565 to form a PMOS polysilicon thin film transistor. It was. In this case, the channel width / channel length of the thin film transistor is 5 μm / 20 μm.

Comparative example

Except for implanting the argon cation (Ar +) before the heat treatment for crystallization after the deposition of the amorphous silicon film was formed in the same manner as in the experimental example.

After applying a drain voltage of 0.1V to the thin film transistor manufactured by the above method, the threshold voltage (Vth) and hysteresis (ΔVth) was measured using HP4155A (manufacturer: HP).

FIG. 7 is a diagram illustrating hysteresis characteristics of a thin film transistor fabricated using a polysilicon crystallization method according to a comparative example, and FIG. 8 is a hysteresis of a thin film transistor fabricated using a polysilicon crystallization method according to an experimental example of the present invention. It is a figure which shows the characteristic. In addition, Table 1 below summarizes the threshold voltage (Vth) and hysteresis (ΔVth) according to the experimental and comparative examples of FIGS. 7 and 8.

Threshold Voltage (Vth) Hysteresis (ΔVth) Experimental Example -2.7072 0.34 Comparative example -4.2256 0.64

Referring to Table 1 and FIGS. 7 and 8, the comparative example shows a threshold voltage (Vth) (a) and an off state when the gate voltage is switched from the on state to the off state (on-> off). It can be seen that the hysteresis ΔVth defined by the difference in the threshold voltage Vth (b) when the signal is switched from the off state to the on state is 0.64.

The above experimental example according to the present invention has a threshold voltage (Vth) (c) when the gate voltage is switched from the on state to the off state (on-> off) and the off state from the off state (off-> on). It can be seen that the hysteresis ΔVth defined by the difference in the threshold voltage Vth (d) when converted to is 0.34.

That is, as shown in the experimental example, hysteresis (ΔVth) was reduced when argon cation (Ar +) was injected into the amorphous silicon film and crystallized to form a thin film transistor.

In addition, the threshold voltage (Vth) is also shifted in the positive (+) direction from -4.2256 to -2.7072, it was confirmed that the threshold voltage (Vth) voltage characteristics are improved.

Accordingly, when manufacturing an organic light emitting display device using a thin film transistor having a reduced hysteresis (ΔVth) formed by the polysilicon manufacturing method according to the present invention, it is possible to improve the quality and reliability of the panel by improving the afterimage problem of the panel. .

While the present invention has been described with reference to the preferred embodiments as described above, those skilled in the art will appreciate that the present invention may be modified in various ways without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated that modifications and variations can be made.

The present invention has the effect of reducing the hysteresis (ΔVth) of the thin film transistor element by injecting an ionized inert element into the amorphous silicon film and crystallization to form a polysilicon film.

The present invention has an effect of improving the image quality of the panel by improving the afterimage problem of the panel by fabricating an organic light emitting display device with reduced hysteresis by employing a thin film transistor using the polysilicon crystallization method.

The present invention has another effect of improving the threshold voltage characteristic of the thin film transistor device by using the polysilicon crystallization method.

Claims (15)

Forming an amorphous silicon film on the substrate; Implanting ionized inert elements onto the amorphous silicon film; And And crystallizing the amorphous silicon film into which the ionized inactive element is implanted. The method of claim 1, The ionized inert element is a polysilicon film production method, characterized in that one selected from helium (He), argon (Ar), chromium (Kr) or xenon (Xe). The method of claim 1, Dose amount of the ionized inert element is a polysilicon film production method, characterized in that in the range of 1x10 ¹³ ~ 1x10 ¹⁵ ions / ㎠. The method of claim 1, Accelerated voltage when the ionized inert element is injected polysilicon film manufacturing method characterized in that the range of 10 ~ 100KV. The method of claim 1, The crystallization is polysilicon film production method characterized in that the heat treatment at 600 ℃ to 800 ℃. Forming an amorphous silicon film on the substrate; Implanting ionized inert elements onto the amorphous silicon film; Crystallizing the amorphous silicon film into which the ionized inactive element is implanted to form a polysilicon film; Patterning the polysilicon film to form an active layer; Patterning and forming a gate electrode on the active layer; Implanting impurities into the active layer using the gate electrode as a mask to define a source region, a drain region, and a channel region between the source region and the drain region; And And forming a source electrode and a drain electrode on the gate electrode. The method of claim 6, The ionized inert element is a method of manufacturing a thin film transistor, characterized in that one selected from helium (He), argon (Ar), chromium (Kr) or xenon (Xe). The method of claim 6, Dose amount of the ionized inert element is a method of manufacturing a thin film transistor, characterized in that in the range of 1x10 ¹³ ~ 1x10 ¹⁵ ions / ㎠. The method of claim 6, The method of manufacturing a thin film transistor, characterized in that the acceleration voltage when the ionized inert element injection ranges from 10 to 100 KeV. The method of claim 6, The crystallization method of manufacturing a thin film transistor, characterized in that the heat treatment at 600 ℃ to 800 ℃. Forming a substrate amorphous silicon film; Implanting ionized inert elements onto the amorphous silicon film; Crystallizing the amorphous silicon film into which the ionized inactive element is implanted to form a polysilicon film; Patterning the polysilicon film to form an active layer; Patterning and forming a gate electrode on the active layer; Implanting impurities into the active layer using the gate electrode as a mask to define a source region, a drain region, and a channel region between the source region and the drain region; Forming a source electrode and a drain electrode on the gate electrode; Forming a first electrode electrically connected with the drain electrode; Forming an organic layer including at least an organic light emitting layer on the first electrode; And And forming a second electrode on the organic layer. The method of claim 11, The ionized inert element is a method of manufacturing an organic light emitting display device, characterized in that one of helium (He), argon (Ar), chromium (Kr) or xenon (Xe). The method of claim 11, The dose of the ionized inert element is a manufacturing method of an organic light emitting display device, characterized in that 1x10 ¹³ ~ 1x10 ¹⁵ ions / ㎠. The method of claim 11, The method of manufacturing an organic light emitting display device, characterized in that the acceleration voltage during implantation of the ionized inert element is in the range of 10 to 100 KeV. The method of claim 11, The crystallization is a method of manufacturing an organic light emitting display device, characterized in that the heat treatment at 600 ℃ to 800 ℃.

Images