KR20070071024A - High volage schottky diode - Google Patents

High volage schottky diode Download PDF

Info

Publication number
KR20070071024A
KR20070071024A KR1020050134140A KR20050134140A KR20070071024A KR 20070071024 A KR20070071024 A KR 20070071024A KR 1020050134140 A KR1020050134140 A KR 1020050134140A KR 20050134140 A KR20050134140 A KR 20050134140A KR 20070071024 A KR20070071024 A KR 20070071024A
Authority
KR
South Korea
Prior art keywords
active region
anode
well
cathode
conductivity type
Prior art date
Application number
KR1020050134140A
Other languages
Korean (ko)
Other versions
KR101212267B1 (en
Inventor
권병기
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020050134140A priority Critical patent/KR101212267B1/en
Publication of KR20070071024A publication Critical patent/KR20070071024A/en
Application granted granted Critical
Publication of KR101212267B1 publication Critical patent/KR101212267B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A high voltage schottky diode is provided to enable a high speed operation while guaranteeing a sufficient reverse bias breakdown voltage by forming a diode by a metal-silicon junction. A well of second conductivity type for a schottky diode is formed in a substrate(21) of first conductivity type. A filed oxide layer defines an active region(20a) for an anode and an active region(20b) for a cathode, locally formed in the substrate having the well of second conductivity type. An anode electrode is formed on the active region for the anode wherein the well of second conductivity type and the anode electrode constitute a schottky diode. A cathode electrode comes in contact with the surface of the active region for the cathode. A well of second conductivity type is formed in the active region for the cathode. A high density impurity layer of second conductivity type for a transistor is formed in the deep position in the well of second conductivity type, and a low density impurity layer of second conductivity type is formed in the shallow position in the well of second conductivity type. The periphery of the active region for the anode is surrounded by a field stop layer(25) of first conductivity type.

Description

고전압 숏키 다이오드{HIGH VOLAGE SCHOTTKY DIODE}High Voltage Schottky Diodes {HIGH VOLAGE SCHOTTKY DIODE}

도 1a는 본 발명의 실시예에 따른 고전압 다이오드의 구조를 도시한 평면도, 1A is a plan view showing the structure of a high voltage diode according to an embodiment of the present invention;

도 1b는 도 1a의 Ⅰ∼Ⅰ선에 따른 수직 단면도,FIG. 1B is a vertical sectional view taken along the line I-I of FIG. 1A;

도 2a 내지 도 2c는 도 1a의 Ⅰ∼Ⅰ선에 따른 공정 단면도,2A to 2C are cross-sectional views of a process taken along lines I to I of FIG. 1A;

도 3a 및 도 3b는 본 발명의 실시예에 따른 숏키다이오드의 바이어스특성을 도시한 도면.3A and 3B illustrate bias characteristics of a Schottky diode according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : p형 반도체기판 22 : 숏키다이오드용 웰21: p-type semiconductor substrate 22: well for Schottky diode

23 : N형 웰 24 : 필드산화막23 N-type well 24: field oxide film

25 : NF 주입층 26 : NM 층25: NF injection layer 26: NM layer

27 : N+ 층 28 : 층간절연막27: N + layer 28: interlayer insulating film

29 : 배리어메탈 30 : 금속막 29: barrier metal 30: metal film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 고전압 다이오드(High volate diode)의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a high volat diode.

고전압소자에서 사용되는 고전압 다이오드는 0.5㎛ 40V 이상의 고전압에서 사용가능한 PN 접합 다이오드(P-N junction diode)이다.The high voltage diode used in the high voltage device is a PN junction diode (P-N junction diode) that can be used at a high voltage of 0.5 µm or more.

그러나, 종래기술의 PN 접합 다이오드는 역방향 바이어스(Reverse bias) 인가시의 항복전압(Breakdown voltage)은 만족할 만한 특성을 가지나, 접합다이오드 특성상 순방향 바이어스(Forward bias) 영역에서의 턴온 전압(0.7V 수준으로 높음) 및 전류 구동 능력에는 한계를 가지고 있으므로 고속 동작에 어려움을 가지고 있다.However, the PN junction diode of the prior art has a satisfactory breakdown voltage when applying reverse bias, but the turn-on voltage in the forward bias region (0.7V level) is high due to the junction diode characteristics. High) and current drive capability, which is difficult to operate at high speed.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 제안된 것으로, 숏키배리어, 즉 메탈-실리콘 접합(Metal-silicon junction)에 의한 다이오드를 형성시켜 충분한 역방향 바이어스 항복전압을 확보함과 동시에 고속 동작이 가능한 고전압 다이오드를 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art, by forming a diode by a Schottky barrier, that is, a metal-silicon junction to ensure a sufficient reverse bias breakdown voltage and at the same time capable of high-speed operation The purpose is to provide a high voltage diode.

상기 목적을 달성하기 위한 본 발명의 고전압 다이오드는 제1도전형 기판, 상기 기판 내에 형성된 숏키다이오드용 제2도전형 웰, 상기 제2도전형 웰이 형성된 기판에 국부적으로 형성되며 애노드용 활성영역과 캐소드용 활성영역을 정의하는 필드산화막, 상기 애노드용 활성영역의 표면 상에 형성되어 상기 제2도전형 웰과 숏키 다이오드를 형성하는 애노드전극, 및 상기 캐소드용 활성영역 상에 콘택된 캐소드전극을 포함하는 것을 특징으로 하고, 상기 캐소드용 활성영역 내에 형성된 제2도전형 웰, 상기 제2도전형 웰 내에 깊게 형성된 트랜지스터용 제2도전형 고농도 불순물층과 얕게 형성된 제2도전형 저농도 불순물층, 및 상기 애노드용 활성영역의 주변을 에워싸는 제1도전형 필드스탑층을 더 포함하는 것을 특징으로 한다.The high voltage diode of the present invention for achieving the above object is formed locally on the first conductive substrate, the second conductive well for the Schottky diode formed in the substrate, the substrate on which the second conductive well is formed and the active region for the anode and A field oxide layer defining a cathode active region, an anode formed on a surface of the anode active region to form a second conductive well and a Schottky diode, and a cathode electrode contacted on the cathode active region A second conductive well formed in the cathode active region, a second conductive high concentration impurity layer for a transistor deeply formed in the second conductive well, and a second conductive low concentration impurity layer shallowly formed; And a first conductive field stop layer surrounding the periphery of the active region for the anode.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 1a는 본 발명의 실시예에 따른 고전압 다이오드의 구조를 도시한 평면도이고, 도 1b는 도 1a의 Ⅰ∼Ⅰ선에 따른 수직 단면도이다.FIG. 1A is a plan view illustrating a structure of a high voltage diode according to an exemplary embodiment of the present invention, and FIG. 1B is a vertical cross-sectional view taken along lines I to I of FIG. 1A.

도 1a 및 도 1b를 참조하면, p형 반도체 기판(21), p형 반도체기판(21) 내에 형성된 숏키다이오드용 웰(SDwell, 22), 숏키다이오드용 웰(SDwell, 22)이 형성된 기판(21)에 국부적으로 형성되며 애노드용 활성영역(20a)과 캐소드용 활성영역(20b)을 정의하는 필드산화막(24), 상기 애노드용 활성영역(20a)의 표면 상에 형성되어 숏키다이오드용 웰(22)과 메탈-실리콘 접합의 숏키 다이오드를 형성하는 Ti/TiN 배리어막(29)과 금속막(30)으로 된 애노드전극, 및 상기 캐소드용 활성영역(20b) 상에 콘택된 Ti/TiN 배리어막(29)과 금속막(30)으로 된 캐소드전극을 포함한다.1A and 1B, a substrate 21 having a p-type semiconductor substrate 21, a Schottky diode well (SDwell, 22) formed in the p-type semiconductor substrate 21, and a Schottky diode well (SDwell, 22) is formed. Formed on the surface of the anode active region 20a and the cathode active region 20b, and formed on the surface of the anode active region 20a, and the Schottky diode well 22 ) And an anode electrode formed of a Ti / TiN barrier layer 29 and a metal layer 30 forming a Schottky diode of a metal-silicon junction, and a Ti / TiN barrier layer contacted on the cathode active region 20b. 29) and a cathode electrode made of a metal film 30.

그리고, 상기 캐소드용 활성영역(20b) 내에는 N형 웰(23)이 형성되고, N형 웰(23) 내에 깊게 형성된 트랜지스터용 고농도 N+ 층(26)과 얕게 형성된 저농도 NM 층(27), 애노드용 활성영역(20a)의 주변을 에워싸는 NF층(25)을 포함한다.An N-type well 23 is formed in the active region 20b for the cathode, and a high concentration N + layer 26 for transistors and a low concentration NM layer 27 and an anode formed deep in the N-type well 23 are formed. And an NF layer 25 surrounding the periphery of the active region 20a.

도 1a에서, 애노드용 활성영역(20a)의 모양은 평면상으로 팔각형이고, 애노드용 활성영역(20a)에 콘택되는 애노드전극은 사각형이다.In FIG. 1A, the shape of the anode active region 20a is octagonal in plan view, and the anode electrode contacting the anode active region 20a is rectangular.

그리고, 애노드용 활성영역(20a)과 캐소드용 활성영역(20b)간 간격 유지를 위해 상기 캐소드용 활성영역(20b) 및 캐소드전극의 모양은 챔퍼드(Chamfered) 모양이다.The cathode active region 20b and the cathode electrode have a chamfered shape in order to maintain a gap between the anode active region 20a and the cathode active region 20b.

도 1a 및 도 1b에 따르면, 숏키다이오드용 웰(22)만을 추가하여 충분한 역방향 바이어스 특성을 가지면서 메탈(Ti/TiN 배리어메탈/금속막)-실리콘(숏키다이오드용 웰이 형성된 실리콘)의 접합에 의한 우수한 순방향 특성을 가지는 숏키배리어다이오드(SD)를 형성할 수 있다.1A and 1B, only a Schottky diode well 22 is added to the junction of metal (Ti / TiN barrier metal / metal film) -silicon (silicon having a Schottky diode well formed) with sufficient reverse bias characteristics. By the Schottky barrier diode (SD) having excellent forward characteristics.

도 2a 내지 도 2c는 도 1a의 Ⅰ∼Ⅰ선에 따른 공정 단면도이다.2A to 2C are sectional views taken along the lines I to I of FIG. 1A.

도 2a에 도시된 바와 같이, p형 반도체기판(21) 내에 숏키다이오드가 형성될 숏키다이오드용 웰(SD-well, 22)을 형성한다. 이때, 숏키다이오드용 웰(SDwell, 22)은 포토레지스트패턴을 이온주입배리어로 사용한 이온주입에 의해 형성된다. 상술한 숏키다이오드용 웰(SDwell, 22)의 농도는 40V 이상의 역방향 항복전압을 가지게 하기 위해 평가를 통해 결정할 수 있으며, 종래 고전압 40V용 웰보다 낮은 농도가 필요하다. 그리고, 드라이브인 조건은 종래 조건을 그대로 유지할 수 있다. 예컨대, 숏키다이오드용 웰(SDwell, 22)을 형성하기 위한 이온주입은 인(Ph)을 125keV의 에너지로 1.0E12 atoms/cm2의 도즈량을 갖도록 실시한다. 이처럼, 숏키다이오드용 웰(SDwell, 22)은 낮은 도즈의 n형 불순물을 이온주입하고, 드라이브인(drive-in)을 길게(long drive-in) 하여 깊은 깊이까지 형성한다. As shown in FIG. 2A, a Schottky diode well (SD-well) 22 in which a Schottky diode is to be formed is formed in the p-type semiconductor substrate 21. At this time, the Schottky diode wells SDwell 22 are formed by ion implantation using a photoresist pattern as an ion implantation barrier. The concentration of the Schottky diode well (SDwell) 22 described above may be determined through evaluation in order to have a reverse breakdown voltage of 40 V or more, and a concentration lower than that of the conventional high voltage 40 V well is required. The drive-in condition can maintain the conventional condition as it is. For example, ion implantation for forming the wells for Schottky diodes SDwell 22 is carried out so that phosphorus Ph has a dose amount of 1.0E12 atoms / cm 2 at an energy of 125 keV. As such, the Schottky diode wells SDwell 22 are ion-implanted with low-dose n-type impurities, and have a long drive-in to form deep depths.

이어서, 숏키다이오드용 웰(22)의 일정 영역에 서로 격리되는 N형 웰(NWELL, 23)을 형성한다. N형 웰(23) 또한 포토레지스트 패턴을 이온 마스크로 사용한 이온 주입에 의해 달성된다. N형 웰(23)의 형성을 위한 이온 주입은 아세닉(As) 특히, 60keV의 에너지로 5.0E15 atoms/cm2의 도즈량을 갖도록 실시한다. 상기 N형 웰(23)은 저전압 PMOS용 웰이다.Subsequently, N-type wells NWELL 23 that are isolated from each other are formed in a predetermined region of the Schottky diode well 22. The N type well 23 is also achieved by ion implantation using a photoresist pattern as an ion mask. Ion implantation for the formation of the N-type well 23 is carried out so as to have a dose amount of 5.0E15 atoms / cm 2 with an energy of acenic (As), in particular, 60 keV. The N-type well 23 is a low voltage PMOS well.

이어서, NNMOS/PMOS 활성 영역을 정의하기 위하여 P형 반도체 기판(21)에 필드산화막(24)을 형성한다. 이때, 필드산화막(24)은 국부산화방법(LOCOS) 방법을 이용하여 형성한다.Subsequently, a field oxide film 24 is formed on the P-type semiconductor substrate 21 to define the NNMOS / PMOS active region. At this time, the field oxide film 24 is formed using a local oxidation method (LOCOS) method.

도 2b에 도시된 바와 같이, NF(NMOSFET Field stop) 이온을 주입하여 숏키 다이오드가 형성되는 영역의 주변 필드산화막(24) 아래에 NF 주입층(25)을 형성한다. 이러한 NF 이온 주입은 필드산화막(24)에 의한 절연 능력의 향상 및 숏키 다이오드의 항복 전압과 누설 전류 특성을 향상시키기 위하여 실시하는 것이다. 예컨대, NF 이온주입은 보론과 같은 P형 불순물을 이온주입한다.As shown in FIG. 2B, NF (NMOSFET field stop) ions are implanted to form an NF implant layer 25 under the peripheral field oxide layer 24 in the region where the Schottky diode is formed. Such NF ion implantation is performed to improve the insulation capability by the field oxide film 24 and to improve the breakdown voltage and leakage current characteristics of the Schottky diode. For example, NF ion implantation implants P-type impurities such as boron.

이어서, NM 및 N+ 공정을 진행하여, N형 웰 내에 저농도의 NM층(26)과 고농도의 N+ 층(27)의 수직 구조를 형성한다. 여기서, NM이라 함은 저농도 N형 불순물을 이온주입하는 공정이며, N+ 공정은 고농도의 N형 불순물을 이온주입하는 공정으 로서, 소스/드레인을 위한 것이다.Subsequently, the NM and N + processes are performed to form a vertical structure of the low concentration NM layer 26 and the high concentration N + layer 27 in the N-type well. Here, NM is a process of ion implantation of low concentration N-type impurities, and the N + process is a process of ion implantation of high concentration of N-type impurities, for source / drain.

도 2c에 도시된 바와 같이, 전면에 층간절연막(ILD, 28)을 형성한 후, 층간절연막을 선택적으로 식각하여 콘택홀을 형성한 다음, 콘택홀을 포함한 전면에 Ti/TiN 배리어메탈(29)과 알루미늄막의 금속막(30)을 형성한다. 이후, 금속배선 식각을 진행한다.As shown in FIG. 2C, after the interlayer dielectric layer (ILD) 28 is formed on the front surface, the interlayer dielectric layer is selectively etched to form contact holes, and then the Ti / TiN barrier metal 29 is formed on the front surface including the contact hole. And a metal film 30 of an aluminum film. After that, the metal wiring etching is performed.

여기서, 숏키다이오드영역에 형성되는 Ti/TiN 배리어메탈(29)과 금속막(30)의 적층(이하, 애노드전극)은 그 아래에 위치하는 쇼키다이오드용 웰(22)과 메탈-실리콘 접합의 숏키 다이오드(SD)가 되고, N+ 층(27)에 연결되는 배리어메탈(29)과 금속막(30)의 적층은 캐소드전극의 역할을 한다. 따라서, Ti/TiN 배리어메탈(29)과 숏키다이오드용 웰(SDwell, 22)간의 메탈, 실리콘 사이의 일함수 차이에 의해 숏키배리어가 형성되는 것이다.Here, the stack of the Ti / TiN barrier metal 29 and the metal film 30 (hereinafter, referred to as an anode electrode) formed in the Schottky diode region (hereinafter referred to as an anode electrode) is referred to as the Schottky well 22 and the Schottky of the metal-silicon junction. The stack of the barrier metal 29 and the metal film 30, which becomes the diode SD and is connected to the N + layer 27, serves as a cathode electrode. Therefore, the Schottky barrier is formed by the work function difference between the metal and silicon between the Ti / TiN barrier metal 29 and the Schottky diode wells SDwell 22.

상술한 실시예에 따르면, 숏키다이오드영역이 되는 활성영역(20a)은 그 형태가 숏키다이오드의 누설특성을 개선하기 위해 모서리가 깍인 챔퍼드(Chamfered) 팔각형 형태를 유지하는 것이 좋으나, 베이스 공정인 0.5㎛ 고전압 40V 공정상 살리사이드 형성이 불가하므로 애노드를 형성시키기 위한 활성영역 모양을 팔각형으로 하고, 숏키배리어를 형성하는 Ti/TiN 배리어메탈과 콘택되는 부분(애노드전극)은 사각형으로 유지한다.According to the above-described embodiment, it is preferable that the active region 20a, which is a Schottky diode region, maintains a chamfered octagonal shape having a cornered shape in order to improve leakage characteristics of the Schottky diode. Since the formation of the salicide is impossible in the high-voltage 40V process, the active region for forming the anode is octagonal, and the portion (anode electrode) in contact with the Ti / TiN barrier metal forming the Schottky barrier is kept in a rectangle.

또한, 누설특성 개선을 목적으로 애노드가 되는 활성영역의 주변을 NF 이온주입을 통해 감싸준다. 즉, P형 불순물의 NF 이온주입을 통해 애노드 주변을 감싸준다.In addition, NF ion implantation surrounds the periphery of the active region to be an anode for the purpose of improving leakage characteristics. That is, it wraps around the anode through NF ion implantation of P-type impurities.

그리고, 도 1a의 평면도에서 캐소드전극은 애노드전극의 주변을 에워싸는 형태인데,전류구동능력에 영향을 줄 수 있는 애노드전극과 캐소드전극간의 간격 유지를 위해 캐소드용 활성영역(20b)과 캐소드전극의 모양을 챔퍼드 모양으로 형성한다.In addition, in the plan view of FIG. 1A, the cathode electrode surrounds the periphery of the anode electrode, and the shape of the cathode active region 20b and the cathode electrode to maintain the gap between the anode electrode and the cathode electrode, which may affect the current driving capability. To form a chamfered shape.

그리고, 숏키다이오드의 전류구동능력 개선을 목적으로 캐소드 영역에 저전압 PMOS 트랜지스터의 웰로 쓰이는 N형 웰(Nwell, 23)을 형성시키므로써 전류경로의 저항을 낮춰 보다 향상된 순방향 전류 특성을 구현한다.In order to improve the current driving capability of the Schottky diode, an N-type well N23, which is used as a well of a low voltage PMOS transistor, is formed in a cathode region, thereby improving the forward current characteristics by lowering the resistance of the current path.

그리고, 숏키다이오드의 사이즈 확장(size extension) : 애노드 폭의 확장시 누설레벨의 증가를 초래하므로, 폭(Width)은 고정된 사이즈를 적용하고 길이(Length)만을 확장하거나, 동일 폭 및 길이를 가지는 다이오드를 다중(Multiple)으로 연결하여 사용한다.In addition, the size extension of the Schottky diode: an extension of the anode width causes an increase in the leakage level, so that the width applies a fixed size and only extends the length, or has the same width and length. Multiple diodes are used for connection.

도 3a 및 도 3b는 본 발명의 실시예에 따른 숏키다이오드의 바이어스특성을 도시한 도면으로서, 순방향 바이어스시 턴온전압을 0.3V로 낮게 확보함과 동시에 역방향 바이어스 항복전압을 -48V로 확보할 수 있음을 알 수 있다.3A and 3B are diagrams illustrating bias characteristics of a Schottky diode according to an embodiment of the present invention, which may ensure a low turn-on voltage of 0.3V and a reverse bias breakdown voltage of -48V during forward bias. It can be seen.

상술한 본 발명은 0.5㎛ 및 0.6㎛ 고전압 공정에 숏키다이오드용 웰 공정 조건 및 드라이브인 시간, 배리어메탈 등을 적절히 선택하여 사용할 수 있다.According to the present invention described above, the well process conditions for the Schottky diode, the drive-in time, the barrier metal, and the like may be appropriately selected and used in the 0.5 µm and 0.6 µm high voltage processes.

이상에서 설명한 바와 같이 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

상술한 본 발명은 0.6㎛ 고전압 40V 공정에 숏키다이오드용 웰 공정만을 추가하여 충분한 역방향 바이어스 특성을 가지면서 메탈-실리콘 접합에 의한 우수한 순방향 특성을 가지는 숏키배리어다이오드를 형성할 수 있는 효과가 있다.The present invention described above has the effect of forming a Schottky barrier diode having excellent forward characteristics by a metal-silicon junction while having a sufficient reverse bias characteristic by adding only a Schottky diode well process to a 0.6 μm high voltage 40V process.

또한, 고속에 의한 신호의 지연시간 감소 효과 등을 요구하는 광범위한 응용 제품에 적용할 수 있는 효과가 있다.In addition, there is an effect that can be applied to a wide range of applications that require the effect of reducing the delay time of the signal due to the high speed.

Claims (6)

제1도전형 기판;A first conductive substrate; 상기 기판 내에 형성된 숏키다이오드용 제2도전형 웰;A second conductive well for a Schottky diode formed in the substrate; 상기 제2도전형 웰이 형성된 기판에 국부적으로 형성되며 애노드용 활성영역과 캐소드용 활성영역을 정의하는 필드산화막;A field oxide layer formed locally on the substrate on which the second conductive well is formed and defining an anode active region and a cathode active region; 상기 애노드용 활성영역의 표면 상에 형성되어 상기 제2도전형 웰과 숏키 다이오드를 형성하는 애노드전극; 및An anode electrode formed on a surface of the anode active region to form the second conductive well and a Schottky diode; And 상기 캐소드용 활성영역 상에 콘택된 캐소드전극A cathode electrode contacted on the cathode active region 을 포함하는 고전압 다이오드.High voltage diode comprising a. 제1항에 있어서,The method of claim 1, 상기 캐소드용 활성영역 내에 형성된 제2도전형 웰;A second conductive well formed in the cathode active region; 상기 제2도전형 웰 내에 깊게 형성된 트랜지스터용 제2도전형 고농도 불순물층과 얕게 형성된 제2도전형 저농도 불순물층; 및A second conductive high concentration impurity layer for a transistor deeply formed in the second conductive well and a second conductive low concentration impurity layer shallowly formed; And 상기 애노드용 활성영역의 주변을 에워싸는 제1도전형 필드스탑층A first conductive field stop layer surrounding the periphery of the active region for the anode 을 더 포함하는 것을 특징으로 하는 고전압 다이오드.High voltage diode further comprising a. 제1항에 있어서,The method of claim 1, 상기 애노드용 활성영역의 모양은 평면상으로 팔각형이고, 상기 애노드전극은 사각형인 것을 특징으로 하는 고전압 다이오드.The anode active region has a planar octagonal shape, and the anode electrode is characterized in that the high voltage diode. 제1항에 있어서,The method of claim 1, 상기 애노드용 활성영역과 캐소드용 활성영역간 간격 유지를 위해 상기 캐소드용 활성영역 및 캐소드전극의 모양은 챔퍼드 모양인 것을 특징으로 하는 고전압 다이오드.In order to maintain the gap between the active region for the anode and the active region for the cathode, the shape of the cathode active region and the cathode electrode is characterized in that the chamfer shape. 제1항에 있어서,The method of claim 1, 상기 애노드전극의 폭은 고정된 사이즈이고, 길이가 확장된 것을 특징으로 하는 고전압 다이오드.The width of the anode electrode is a fixed size, high voltage diode, characterized in that the length is extended. 제1항 내지 제5항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 5, 상기 제1도전형은 P형 불순물이 도핑된 것이고, 상기 제2도전형은 N형 불순물이 도핑된 것을 특징으로 하는 고전압 다이오드.The first conductive type is doped with P-type impurities, and the second conductive type is doped with N-type impurities.
KR1020050134140A 2005-12-29 2005-12-29 High volage schottky diode KR101212267B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050134140A KR101212267B1 (en) 2005-12-29 2005-12-29 High volage schottky diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050134140A KR101212267B1 (en) 2005-12-29 2005-12-29 High volage schottky diode

Publications (2)

Publication Number Publication Date
KR20070071024A true KR20070071024A (en) 2007-07-04
KR101212267B1 KR101212267B1 (en) 2012-12-14

Family

ID=38506227

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050134140A KR101212267B1 (en) 2005-12-29 2005-12-29 High volage schottky diode

Country Status (1)

Country Link
KR (1) KR101212267B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070815B2 (en) 2012-08-23 2015-06-30 Samsung Electronics Co., Ltd. Photonic device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101872069B1 (en) * 2015-05-22 2018-06-28 매그나칩 반도체 유한회사 Shottky Diode having a Floating Structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11163373A (en) * 1997-12-01 1999-06-18 Mitsubishi Electric Corp Semiconductor device having schottky barrier diode and its manufacture
JP3760945B2 (en) 2004-04-01 2006-03-29 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9070815B2 (en) 2012-08-23 2015-06-30 Samsung Electronics Co., Ltd. Photonic device

Also Published As

Publication number Publication date
KR101212267B1 (en) 2012-12-14

Similar Documents

Publication Publication Date Title
US5315144A (en) Reduction of bipolar gain and improvement in snap-back sustaining voltage in SOI field effect transistor
US6979861B2 (en) Power device having reduced reverse bias leakage current
US20090206364A1 (en) Insulated gate bipolar transistor and method of fabricating the same
KR20170059706A (en) Power semiconductor devices
US7521342B2 (en) Semiconductor structure with high-voltage sustaining capability and fabrication method of the same
US10256340B2 (en) High-voltage semiconductor device and method for manufacturing the same
KR0159141B1 (en) Semiconductor device having a plurality of impurity layers and manufacturing method thereof
KR101212267B1 (en) High volage schottky diode
KR20180104236A (en) Method of Manufacturing Power Semiconductor Device
JPH02203566A (en) Mos type semiconductor device
US20090152587A1 (en) Deep guard regions for reducing latch-up in electronics devices
KR19990078010A (en) Insulated gate transistor, a method of manufacturing same, and semiconductor integrated circuit device
KR100366829B1 (en) Semiconductor device
US11049853B2 (en) ESD protection device with breakdown voltage stabilization
US8193602B2 (en) Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the reverse breakdown
US6492710B1 (en) Substrate isolated transistor
KR20010094722A (en) method for manufacturing high voltage device and the same
US6306717B1 (en) Method of manufacturing an avalanche diode with an adjustable threshold
KR101928253B1 (en) Method of Manufacturing Power Semiconductor Device
KR100792377B1 (en) Method for fabricating fin transistor
KR100233623B1 (en) Method for manufacturing semiconductor device having reduced width of channel stopper region
KR100261173B1 (en) Method for fabricating semiconductor device
KR101099564B1 (en) Bipolar junction transistor and method for manufacturing the same
KR100551895B1 (en) Zener diode of semiconductor intergrated circuit
KR100600273B1 (en) Method of manufacturing a transistor in a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20151118

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20161118

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20171117

Year of fee payment: 6

FPAY Annual fee payment

Payment date: 20181120

Year of fee payment: 7

FPAY Annual fee payment

Payment date: 20191119

Year of fee payment: 8