KR20070070701A - The method for fabricating array substrate for in-plane switching mode lcd - Google Patents

Abstract

A method for fabricating an array substrate for an in-plane switching mode LCD is provided to prevent light leakage generated by bad rubbing in a stepped part without widening a black matrix. A plurality of gate lines are formed on a substrate(110) in a first direction. A plurality of common lines are separated from the plurality of gate lines. An outermost common electrode(118) branched from the common line is formed at an outermost part of each pixel area. A gate insulating layer(121) is formed on the plurality of gate lines, the plurality of common lines, and the outermost common electrodes. A plurality of data lines(130) are formed on the gate insulating layer, crossing the gate lines for defining a plurality of pixel areas(P). A thin film transistor is formed at each pixel area, connected with the gate lines and the data lines. A passivation layer(140) made of an inorganic insulating material is formed on the data lines and the thin film transistors, wherein upper parts of the outermost common electrodes and a part where the outermost common electrodes are not formed, are the same in height from a substrate plane. The passivation layer has drain contact holes exposing the thin film transistors. Outermost pixel electrodes are formed on the passivation layer, contacting with the thin film transistors through the drain contact holes and overlapped with a part of the outermost common electrode.

Description

The method for fabricating array substrate for In-Plane switching mode LCD}

1 is a cross-sectional view schematically showing a part of a general transverse electric field type liquid crystal display device.

2A and 2B are cross-sectional views showing operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

3 is a plan view showing a part of a conventional array substrate for a transverse electric field type liquid crystal display device.

4 is a cross-sectional view of a portion cut along the cutting line IV-IV of FIG.

5A through 5G are cross-sectional views illustrating manufacturing steps of one pixel area including a switching element of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

<Brief description of the main parts of the drawing>

110 array substrate 115 gate electrode

118: outermost common electrode 121: gate insulating film

125: semiconductor layer 125a: active layer

125b: ohmic contact layer 126a: pure amorphous silicon pattern

126b: Impurity Amorphous Pattern 130: Data Wiring

140: protective layer 133: source electrode

136: drain electrode 145: drain contact hole

181a: first photoresist pattern

A1: A protective layer portion in which no wiring and electrodes are formed below (first region)

A2: second area

P: pixel area

TrA: switching area

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a transverse electric field type liquid crystal display device capable of reducing wiring resistance of a Vcom wiring.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated as an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes a color filter substrate on which a common electrode is formed, an array substrate on which pixel electrodes are formed, and a liquid crystal interposed between the two substrates. In such a liquid crystal display, the common electrode and the pixel electrode are caused by an electric field applied up and down. It is excellent in the characteristics, such as transmittance | permeability and aperture ratio, by the method of driving a liquid crystal.

However, the liquid crystal drive due to the electric field applied up and down has a disadvantage that the viewing angle characteristics are not excellent.

Accordingly, a transverse field type liquid crystal display device having excellent viewing angle characteristics has been proposed to overcome the above disadvantages.

Hereinafter, a general transverse electric field type liquid crystal display device will be described in detail with reference to FIG. 1.

1 is a cross-sectional view of a general transverse electric field type liquid crystal display device.

As shown, the upper substrate 9, which is a color filter substrate, and the lower substrate 10, which is an array substrate, are spaced apart from each other, and the liquid crystal layer 11 is interposed between the upper and lower substrates 9, 10. It is.

The common electrode 17 and the pixel electrode 30 are formed on the lower substrate 10 on the same plane, and the liquid crystal layer 11 is formed on the common electrode 17 and the pixel electrode 30. It is operated by the horizontal electric field (L).

2A and 2B are cross-sectional views illustrating operations of on and off states of a general transverse electric field type liquid crystal display device, respectively.

First, referring to FIG. 2A, which illustrates an arrangement of liquid crystals in an on state where a voltage is applied, a phase change of a liquid crystal 11a at a position corresponding to the common electrode 17 and the pixel electrode 30 is performed. Although the liquid crystal 11b positioned in the section between the common electrode 17 and the pixel electrode 30 is formed by the horizontal electric field L formed by applying a voltage between the common electrode 17 and the pixel electrode 30, It is arranged in the same direction as the horizontal electric field (L). That is, in the transverse electric field type liquid crystal display device, since the liquid crystal moves by the horizontal electric field, the viewing angle is widened.

Therefore, when the transverse electric field type liquid crystal display device is viewed from the front, it can be seen in the up / down / left / right directions even in the about 80 to 85 ^o direction without inversion phenomenon.

Next, referring to FIG. 2B, since a horizontal electric field is not formed between the common electrode and the pixel electrode because no voltage is applied to the liquid crystal display, the arrangement state of the liquid crystal layer 11 does not change.

FIG. 3 is a plan view schematically illustrating a part of a conventional array substrate for a transverse electric field type liquid crystal display device, and FIG. 4 is a cross-sectional view of a portion cut along the cutting line IV-IV of FIG. 3.

First, as shown in FIG. 3, a conventional general horizontal transverse electric field type liquid crystal display array substrate 40 includes a plurality of gate wires 43 arranged in parallel in a horizontal direction at a predetermined interval, and the gate wires. The pixel region P intersects the common wiring 47 formed in parallel with the gate wiring 43 and intersects with the two wirings 43 and 47, and particularly with the gate wiring 12. The data wiring 60 to be defined is configured.

The thin film transistor Tr including the gate electrode 45, the semiconductor layer 51, and the source drain electrodes 53 and 55 is formed at the intersection point of the gate line 43 and the data line 60. At this time, the source electrode 53 branches off the data line 43, and the gate electrode 45 branches off the gate line 43.

In addition, the pixel region P includes a plurality of pixel electrodes 70a and 70b connected to the drain electrode 55 and are alternately arranged in parallel with the pixel electrodes 70a and 70b. A plurality of common electrodes 49a and 49b branched from 47 are formed.

Next, the cross-sectional structure will be described with reference to FIG.

First, a plurality of common electrodes 49a and 49b are formed on the substrate 40 so as to be spaced apart from each other, and a gate insulating film 50 is formed on the entire surface thereof. At this time, the gate insulating film 50 is formed by depositing an inorganic insulating material, and the surface of the gate insulating film 50 is convex as much as the thickness of the common electrodes 49a and 49b for the portion where the common electrodes 49a and 49b are formed. It is formed with a step.

In addition, although not shown in the drawing, the gate wires extending in one direction along with the common electrodes 49a and 49b are connected to the common electrodes 49a and 49b, and common wirings are further formed. The gate insulating film 50 formed on the upper portion of the gate insulating film 50 is formed with a step in a convex shape.

Next, a data line 60 is formed on the gate insulating layer 50 to define the pixel region P by crossing the gate line (not shown). In this case, the data line 60 is formed to define the pixel area P, and is formed at a boundary between one adjacent pixel area P. In this case, the data line 60 is formed in each pixel area. It can be seen that it is formed between the common electrode 49b formed at the outermost part of (P).

Next, an upper portion of the data line 60 is formed as an inorganic insulating material on the front surface thereof, and a protective layer 65 having a level difference is formed on the surface of the data line 60. The plurality of pixel electrodes 70a and 70b may be alternately disposed on the passivation layer 65 to alternate with the common electrodes 49a and 49b formed under the gate insulating layer 50 in each pixel region P. Referring to FIG. Is being formed.

At this time, among the pixel electrodes 70a and 70b, the pixel electrode 70b positioned at the outermost portion of each pixel region P has a common outermost portion formed at a lower portion thereof to improve the aperture ratio in the pixel region P. The electrode 49b and a portion thereof overlap each other, and the outermost pixel electrode 70b overlapping the outermost common electrode 49b is formed at an upper portion thereof by the thickness of the outermost common electrode 49b. It can be seen that the gate insulating film 50 itself is formed with a step.

The liquid crystal display is formed by forming and bonding a liquid crystal layer between the array substrate 40 having such a configuration and the color filter substrate 80 including the color filter layer 85, the black matrix BM, and the overcoat layer 87. This completes the device.

In this case, in order to move the liquid crystal molecules consistently with respect to a specific voltage by applying a voltage to the liquid crystal layer, it is necessary to have a consistent arrangement of liquid crystal molecules at first. For this purpose, the array substrate 40 and the color filter substrate (not shown) An alignment film (not shown) on each of the two layers, and rubbing the two substrates 40 and 80 on which the alignment films (not shown) are formed so that the liquid crystals are arranged in one direction in the alignment film (not shown). Doing.

However, when rubbing proceeds to the alignment layer, particularly in the case of the array substrate 40 having a step on the surface thereof, rubbing does not proceed well in the stepped portion formed by the electrodes and the wiring, so that the liquid crystal It will behave irregularly. Accordingly, a black matrix BM is formed to prevent light from passing through the color filter substrate 80 in response to the irregularly-formed liquid crystal, particularly the gate and the data line (not shown) 60.

In particular, the data line 60 includes the data line 60 so as to sufficiently cover the outermost common electrode 49b positioned on both sides thereof, more precisely formed at the outermost portion to overlap the common electrode 49b. The black matrix BM is formed to sufficiently cover the stepped part SA of the outermost pixel electrode 70b having the stepped part SA by the surface step of the protective layer 65. In the stepped portion SA of the outermost pixel electrode 70b, an alignment film portion in which rubbing is not properly progressed due to the step is generated. The stepped portion SA is caused by the black matrix BM. ), Even if they cover the problem of light leakage occurs.

Therefore, to solve this problem, when the black matrix BM is formed to completely cover the outermost pixel electrode 70b, the width of the black matrix BM is further increased in the pixel area. This causes a problem that the brightness is lowered.

An object of the present invention is to provide a method of manufacturing a transverse field array substrate which prevents light leakage due to a step, which is a problem of the conventional transverse field type liquid crystal display device, and further prevents light leakage from a step portion without increasing the width of the black matrix. It is done.

A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to an embodiment of the present invention for achieving the above object is a plurality of gate wiring and a plurality of spaced apart from the plurality of gate wiring in a first direction on the substrate Forming a common wiring and an outermost common electrode branched from the common wiring at the outermost portion of each pixel region; Forming a gate insulating layer on the plurality of gate lines, the common lines, and the outermost common electrode; Forming a plurality of data wires over the gate insulating film, the plurality of data wires crossing the gate wires and defining a plurality of pixel areas; Forming a thin film transistor connected to the gate line and the data line in each pixel area; A protective layer having a drain contact hole exposing the uppermost outermost common electrode and the portion where the outermost common electrode is not formed as an inorganic insulating material over the data line and the thin film transistor has the same height from the substrate surface and exposes the thin film transistor. Forming a; Forming an outermost pixel electrode on the protective layer through the drain contact hole and contacting the thin film transistor and overlapping a portion of the outermost common electrode.

In the forming of the protective layer, an inorganic insulating material is deposited on the entire surface of the thin film transistor and the data line to have a first height corresponding to the outermost common electrode, and corresponding to the central portion of the pixel region. Forming an insulating layer having a second height lower than the height; The mask is formed so that the transflective region corresponds to the portion of the insulating layer having the first height above the insulating layer, and the transmissive region corresponds to the portion of the thin film transistor in which the drain contact hole is to be formed, and the blocking region corresponds to the remaining portion. Positioning and exposing; The exposed photoresist layer is developed to expose the insulating layer to correspond to a portion of the thin film transistor, and to correspond to the insulating layer having the first height, to correspond to the first photoresist pattern having a first thickness and other regions. Forming a second photoresist pattern having a second thickness thicker than the first thickness; Etching the insulating layer exposed to the outside of the first and second photoresist patterns to form a drain contact hole exposing a portion of the thin film transistor; Ashing and removing the first photoresist pattern; Etching the insulating layer exposed to the outside of the second photoresist pattern so that the insulating layer exposed to the outside of the second photoresist pattern has a height substantially equal to the second height.

The forming of the outermost common electrode may further include forming a plurality of spaced apart central common electrodes branched from the common wiring between the outermost common electrodes, wherein the outermost pixel electrode is formed. The method may further include forming a plurality of central pixel electrodes alternately alternate with the central common electrode between the outermost pixel electrodes.

The forming of the outermost pixel electrode may further include forming a plurality of central common electrodes and a central pixel electrode which are alternately spaced apart from each other as the same material on the same layer on which the outermost pixel electrode is formed. The forming of the protective layer may further include forming a common wiring contact hole exposing the common wiring to connect the central common electrode and the common wiring.

In addition, the outermost pixel electrode overlapping the outermost common wiring may be formed without a step.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention includes: a gate line and a data line intersecting each other on a substrate and defining pixel regions, respectively, formed on the lower and upper portions of the gate insulating film; A common wiring formed on the same layer in parallel with the gate wiring, and first and second outermost common electrodes branched from the common wiring to an innermost outer side of the pixel region; A thin film transistor connected to the gate line and the data line over the gate insulating layer; A drain contact hole is formed over the thin film transistor and the gate insulating layer to expose one electrode of the thin film transistor as an inorganic insulating material, and has a height from a center portion of the pixel region and the substrate surface on the first and second outermost common electrodes. Is substantially the same protective layer; A central portion formed in contact with one electrode of the thin film transistor through the drain contact hole, the first and second outermost pixel electrodes partially overlapping the first and second outermost common electrodes, and a plurality of spaced apart portions from the protective layer; It includes a pixel electrode.

In this case, the first and second outermost common electrodes may further include a plurality of central common electrodes parallel to and alternate with the plurality of central pixel electrodes with the same material on the same layer.

In addition, the first and second outermost pixel electrodes may further include a plurality of central common electrodes alternately parallel to and intersected with the central pixel electrodes on the same layer by the same material as the plurality of central pixel electrodes.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

5A through 5G are cross-sectional views illustrating manufacturing steps of one pixel area including a switching element of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, a first metal material such as aluminum (Al) or aluminum alloy (AlNd) or chromium (Cr), molybdenum (Mo), molybdenum alloy, A metal material selected from copper (Cu) and a copper alloy is deposited on the entire surface of the substrate 110 to form a first metal layer, and then a photoresist is applied thereon, and exposed using a mask having a transmission region and a blocking region. In addition, a gate process (not shown) extending in one direction and a common wiring spaced apart from the gate wire (not shown) may be performed by developing the exposed photoresist and etching the exposed first metal layer. C).

At the same time, in the switching region TrA in which the thin film transistor, which is a switching element, is formed, a gate electrode 115 branched from the gate wiring (not shown) is formed, and in each pixel region P, the common wiring (not shown). Branching at the to form a plurality of common electrodes 118.

Next, as shown in FIG. 5B, an inorganic insulating material such as silicon oxide (SiO) is formed on the entire surface of the gate wiring (not shown) including the gate electrode 115, the common wiring (not shown), and the common electrode 118. ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating layer 121.

In this case, the gate insulating layer 121 is formed by depositing with an inorganic insulating material, and the surface of the gate insulating layer 121 is not flat and the thickness of the gate wiring (not shown), common wiring (not shown), and common electrode 118 formed at the bottom thereof. Reflected is formed to have a step higher than the other portion in the wiring (not shown) and the electrode 118 portion.

Successively sequentially depositing pure amorphous silicon and impurity amorphous silicon on the gate insulating layer 121 to form a pure amorphous silicon layer and an impurity amorphous silicon layer, and a second metal material, for example, molybdenum, on the impurity amorphous silicon layer By depositing (Mo), a second metal layer is formed.

Next, the data line 130 defining the pixel region P to cross the gate line (not shown) by patterning the second metal layer, an impurity amorphous silicon layer, and a pure amorphous silicon layer under the mask process. At the same time, in the switching region TrA, an active layer 125a made of pure amorphous silicon is formed on the gate insulating layer 121 from below, and an impurity amorphous silicon is formed on the active layer 125a and spaced apart from each other. The ohmic contact layer 125b and the source and drain electrodes 133 and 136 spaced apart from each other are respectively formed on the ohmic contact layer 125b and the ohmic contact layer 125b spaced apart from each other, thereby forming a thin film transistor as a switching element in the switching region TrA. Complete Tr). In this case, the source electrode 133 is formed to be connected to the data line 130.

Meanwhile, the semiconductor layer 125 and the source and drain electrodes 133 and 136 are formed under the data line 130 by one mask process. The active layer 125a and the ohmic contact layer 125b are formed. The semiconductor material 126 of pure amorphous silicon and non-crystalline silicon may be formed using the same material forming the same. However, when the semiconductor layer and the source and drain electrodes are formed by performing different mask processes, the semiconductor pattern may not be formed below the data line.

Next, as illustrated in FIG. 5C, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the data line 130 and the source and drain electrodes 133 and 136 on the front surface. As a result, the protective layer 140 is formed. At this time, the protective layer 140 is also formed of an inorganic insulating material by the deposition, the lower surface of the data line 130, the common wiring (not shown) and the step formed by the common electrode 118, etc. reflects the surface thereof as it is. This is not flat but is formed with a step.

That is, when the height from the surface of the substrate 110 of the portion A1 of the protective layer 140a where the wiring and the electrode are not formed below is referred to as the first height h1, the outermost portion of the pixel region P is formed. Since the outermost common electrode 118 is formed at the bottom thereof, the height of the protective layer 140b formed from the substrate 110 surface of the protective layer 140b is reflected by the thickness of the outermost common electrode 118. It is formed to have a second height h2 higher than (h1). In this case, for convenience of description, the portion where the protective layer 140a of the first height h1 is formed is the first region A1 and the portion where the protective layer of the second height h2 higher than the first height is formed. Is defined as a second area A2.

Thereafter, a photoresist is coated on the entire surface of the protective layer 140 to form a photoresist layer 181. In this case, the photoresist layer 181 will be described as an example of using a positive type photoresist having a characteristic that the lighted portion is removed during development. However, in the case of a negative photoresist having the opposite characteristic, that is, a part where light is left when developing, the same result can be obtained by using a mask in which the transmission region and the blocking region of the mask will be described later. .

Next, the transmissive area TA, the blocking area BA, and the slit-shaped semi-transmissive area for controlling the amount of light passing through the photoresist layer 181 on the substrate 110 formed thereon ( After placing a mask 191 composed of a HTA (slit type) or a semi-transmissive region (HTA) (half tone type) coated with a multilayer organic film absorbing the transmitted light, the photoresist layer 181 The exposure through the mask 191 is performed. The photoresist pattern having a different thickness by applying a diffraction exposure technique or a halftone technique that controls the amount of light irradiated to the photoresist layer 181 by using the mask 191 provided with the semi-transmissive region (HTA). To form.

At this time, during the exposure through the mask 191, the degree of light transmission is 100% light is transmitted in the transmission area (TA), light is not transmitted at all in the blocking area (BA) is blocked, transflective In the area HTA, the amount of light determined as an appropriate percentage is transmitted between 0% and 100% depending on the slit structure (slit width and slit spacing) or the coating strength (coating count or coating thickness) for halftone implementation.

In the case where the mask 191 including the transflective area HTA is positioned on the passivation layer 140 and exposed, the transmissive area TA may be formed with respect to a part of the drain electrode 136 of the switching area TrA. In order to correspond to this, the semi-transmissive region corresponds to a region overlapping with the outermost common electrode 118, including a step portion generated by the outermost common electrode 118 corresponding to an edge portion of the pixel region P. The exposure is performed in a state where the mask 191 is positioned so that the HTA corresponds to and the blocking area BA corresponds to the other area.

 Next, when the photoresist layer 181 exposed through the mask 191 is developed, as illustrated in FIG. 5D, a thick first thickness () may be formed in an area corresponding to the blocking area BA of the mask 191. The first photoresist pattern 181a having t1 remains, and the outermost common electrode 118 of the outermost portion of the pixel region P, that is, the portion corresponding to the transflective region HTA of the mask 191 is left. A second thickness thinner than the first thickness t1 on the protective layer 140b of the second region A2 corresponding to the outermost common wiring 118 including the stepped portion SA generated by The second photoresist pattern 181b having t2 remains, and the upper portion of the passivation layer 140 covering the drain electrode 136 corresponding to the transmission area TA of the mask 191 has the photoresist layer ( All of them are removed during development of 181 of FIG. 5C to expose the protective layer 140.

Thereafter, the protective layer 140 exposed to the outside of the first and second photoresist patterns 181a and 181b is etched and removed to expose the drain contact hole 145 exposing the drain electrode 136 in the switching region TrA. ).

Next, as shown in FIG. 5E, the second and second photoresist patterns (181a and 181b of FIG. 5D) are ashed to the substrate 110 where the drain electrode 136 is exposed. A second region formed by removing the second photoresist pattern (181b of FIG. 5D) having a thickness (t2 of FIG. 5D) and having a second height h2 from the surface of the substrate 110 by the outermost common electrode 118. The protective layer 140b of (A2) is exposed. At this time, the ashing characteristic of the first photoresist pattern 181a of the first thickness (t1 of FIG. 5D) is also reduced over the entire surface of the substrate 110, but the second photoresist pattern (FIG. Only the thickness of 181b of 5d is removed so that the thickness remains on the substrate 110 in a reduced state.

Next, as illustrated in FIG. 5F, the neighboring protective layer 140b of the second region A2 having the second height h2 exposed to the outside of the first photoresist pattern 181a of FIG. 5E is formed. The etching is performed such that the height becomes substantially the same as the first height h1 of the protective layer 140a of the first region A1 so that the step is eliminated.

In this case, during etching of the protective layer 140b of the second region A2 exposed between the first photoresist pattern 181a of FIG. 5E, an etching time and an etching liquid (when wet etching) or a gas in the chamber are performed. (In the case of dry etching) By appropriately adjusting the concentration, it can be etched to be as high as the height of the protective layer 140a of the neighboring first region A1.

Therefore, the step formed in the outermost protective layer 140 in one pixel region P is conventionally formed inside the pixel region P in the outermost common electrode (49b of FIG. 4). Due to the etching of the passivation layer 140b of the second region A2, the stepped portion SA of the passivation layer 140b of the second region A2 overlaps the outermost common electrode 118. It can be seen that it is formed or near the data line 130 to the outermost part of the pixel region (P).

Next, as illustrated in FIG. 5G, the step SA on the passivation layer 140 in the second area A2 is etched and moved on the substrate 110 moved to the outer side of the pixel area P. The remaining first photoresist pattern 181a in FIG. 5F is stripped and removed.

Subsequently, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the protective layer 140, and patterned by performing a mask process to form the drain contact hole ( The pixel electrode 150 is formed to contact the drain electrode 136 and to be spaced apart from each other through 154.

At this time, the outermost pixel electrode 150b formed to overlap the outermost common electrode 118 with a part of the outermost portion of the pixel region P may also have a first region in which wiring and electrodes are not formed thereunder. A stepped portion SA of the protective layer 140 is seen in the same manner as the pixel electrode 150a formed in the flat structure on the protective layer 140a of A1 without a step, that is, formed at the center portion of the pixel region P. Due to the characteristics of the present invention, since the data line 130 is moved to be flat without a step, it does not have a stepped portion in itself, and thus light leakage due to a rubbing defect is not generated.

Accordingly, the two substrates 110 and 170 face each other, having the structure such that the color filter substrate 170 having the completed array substrate 110, the black matrix BM, the color filter layer 175, and the overcoat layer 187 face each other. In order to complete the liquid crystal display by injecting and bonding the liquid crystal between the liquid crystal display device, a gate wiring (not shown), data wiring 130 and thin film transistor (not shown) of the array substrate 110 are formed on the color filter substrate 170. The black matrix BM formed to correspond to the data line 130 among the black matrix BM formed corresponding to Tr includes the data line 130 and the pixel area P around the data line 130. The light leakage can be sufficiently prevented by forming the innermost end of the innermost common wiring 118 to coincide with the inner end of the pixel region P. FIG.

Because of the characteristics of the present invention, the outermost pixel electrode 150b formed to overlap the outermost common electrode 118 is formed to be flat without a step, and thus an alignment layer (not shown) is disposed on the outermost pixel electrode 150b. ) And rubbing, the rubbing defect does not occur on the outermost pixel electrode 150b having the flat surface and formed without a step so that no light leakage defect occurs in the portion.

Accordingly, in the transverse electric field type liquid crystal display device having the array substrate 110 according to the present invention, the step of the outermost pixel electrode 150b can be increased without widening the width of the black matrix BM that covers the data line 130. Since no light leakage occurs due to poor rubbing, the width of the black matrix BM covering the data line 130 is covered to the inner end of the outermost common electrode 118 as in the prior art. It can be seen that the light leakage does not occur even when formed.

According to the exemplary embodiment of the present invention, unlike the outermost common electrode 118, the common electrode in contact with the substrate 110 is not formed in the center portion of the pixel region P. This is because P is formed at the center part of the same material on which the pixel electrode 150 is formed to be spaced apart from the pixel electrode 150 in the same layer (protective layer). In this case, the common electrode 155 formed at the center of the transparent conductive material may have a common wiring (not shown) connected to the outermost common electrode 118 in the protective layer 140 and the gate insulating layer 121 below. The semiconductor device may further include a common wiring contact hole (not shown) for exposing and contacting the common wiring (not shown) through the common wiring contact hole (not shown).

In the modified example, even if the pixel region and the common electrode are alternately formed at the center of the pixel region, even if the same layer is formed of the same material as the outermost common electrode in the center of the pixel region, the outermost pixel is formed. Unlike the electrode, the pixel electrode itself formed at the center of the pixel region does not have a step, and thus does not cause light leakage due to poor rubbing, but in this case, according to the present invention described above, A method of manufacturing an array substrate is used to form a photoresist pattern having a low second height even with respect to the stepped protective layer on the common electrode formed at the center of the pixel region, and to etch the protective layer of the second region. The surface can be flattened to prevent rubbing defects Ice can prevent light leakage in accordance with (rubbing) is bad.

The present invention is characterized in that, in the fabrication of the array substrate for the transverse electric field type liquid crystal display device, the surface of the stepped protective layer is flattened without the addition of a mask process, and the above-described embodiments and modifications without departing from the spirit of the present invention. It is obvious that modification and change can be made without being limited to this.

The array substrate for a transverse electric field type liquid crystal display device according to the present invention is formed by moving a protective layer formed in a stepped form by a lower wiring and an electrode by moving the portion having the surface flat or the stepped part to a part covered by the black matrix. There is an effect of sufficiently preventing light leakage caused by rubbing defects in the stepped portion without widening the width of the matrix.

Further, in order to prevent light leakage caused by poor rubbing of the stepped portions, it is not necessary to increase the width of the black matrix covering these portions, thereby improving aperture ratio and luminance.

Claims (10)

Forming a plurality of common wirings spaced apart from the plurality of gate wirings in the first direction and a plurality of common wirings on the substrate, and an outermost common electrode branched from the common wiring at the outermost portion of each pixel region; Forming a gate insulating layer on the plurality of gate lines, the common lines, and the outermost common electrode; Forming a plurality of data lines over the gate insulating layer, the plurality of data lines defining a plurality of pixel regions intersecting the gate lines; Forming a thin film transistor connected to the gate line and the data line in each pixel area; A protective layer having a drain contact hole exposing the uppermost outermost common electrode and the portion where the outermost common electrode is not formed as an inorganic insulating material over the data line and the thin film transistor has the same height from the substrate surface and exposes the thin film transistor. Forming a; Forming an outermost pixel electrode contacting the thin film transistor through the drain contact hole and overlapping a portion of the outermost common electrode over the passivation layer; Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, Forming the protective layer An insulating layer having a first height corresponding to the outermost common electrode by depositing an inorganic insulating material over the thin film transistor and the data line, and having a second height lower than the first height corresponding to the central portion of the pixel region. Forming a; The mask is formed so that the transflective region corresponds to the portion of the insulating layer having the first height above the insulating layer, and the transmissive region corresponds to the portion of the thin film transistor in which the drain contact hole is to be formed, and the blocking region corresponds to the remaining portion. Positioning and exposing; The exposed photoresist layer is developed to expose the insulating layer to correspond to a portion of the thin film transistor, and to correspond to the insulating layer having the first height, to correspond to the first photoresist pattern having a first thickness and other regions. Forming a second photoresist pattern having a second thickness thicker than the first thickness; Etching the insulating layer exposed to the outside of the first and second photoresist patterns to form a drain contact hole exposing a portion of the thin film transistor; Ashing and removing the first photoresist pattern; Etching the insulating layer exposed to the outside of the second photoresist pattern so that the insulating layer exposed to the outside of the second photoresist pattern has a height substantially equal to the second height. Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, Forming the outermost common electrode And forming a plurality of spaced apart central common electrodes branched from the common wiring between the outermost common electrodes. The method of claim 3, wherein Forming the outermost pixel electrode And forming a plurality of central pixel electrodes alternately alternate with the central common electrode between the outermost pixel electrodes. The method of claim 1, Forming the outermost pixel electrode And forming a plurality of central common electrodes and central pixel electrodes which are spaced apart from each other by the same material and alternately alternately formed on the same layer on which the outermost pixel electrodes are formed. The method of claim 5, Forming the protective layer And forming a common wiring contact hole to expose the common wiring, thereby connecting the central common electrode and the common wiring. The method of claim 1, And the outermost pixel electrode overlapping the outermost common wiring is formed without a step. Gate wirings and data wirings crossing each other on the substrate to define pixel regions, respectively, formed on the lower and upper portions of the gate insulating film; A common wiring formed on the same layer side by side with the gate wiring, and first and second outermost common electrodes branched from the common wiring to the outermost inner side of the pixel region; A thin film transistor connected to the gate line and the data line over the gate insulating layer; A drain contact hole is formed over the thin film transistor and the gate insulating layer to expose one electrode of the thin film transistor as an inorganic insulating material, and has a height from a center portion of the pixel region and the substrate surface on the first and second outermost common electrodes. Is substantially the same protective layer; A central portion formed in contact with one electrode of the thin film transistor through the drain contact hole, the first and second outermost pixel electrodes partially overlapping the first and second outermost common electrodes, and a plurality of spaced apart portions from the protective layer; Pixel electrode Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 8, And a plurality of central common electrodes parallel to and intersecting with the plurality of central pixel electrodes with the same material on the same layer inside the first and second outermost common electrodes. The method of claim 8, An array for a transverse field type liquid crystal display device further comprising a plurality of central common electrodes parallel to and intersected with the central pixel electrodes on the same layer and made of the same material as the plurality of central pixel electrodes inside the first and second outermost pixel electrodes. Board.

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