KR20070069673A - Method for fabricating thin film transistor array substrate - Google Patents

Abstract

A method for manufacturing a TFT(Thin Film Transistor) array substrate is provided to perform a photoresist ashing process by using an active layer as a photoresist ashing stopper, thereby effectively improving the uniformity of pixel electrodes formed in pixel regions. A first metal layer is formed on a transparent insulating substrate(100) and patterned to form a gate line(122), a gate electrode(123) and a gate pad(121). A gate insulating layer(120), an active layer, and a second metal layer are sequentially formed on the transparent insulating layer. A first photoresist pattern(150) is formed on a data pad region, a data line region, a pixel region, and a TFT region of the second metal layer. A data pad and a data line are respectively formed in the data pad region and the data line region, the active layer is exposed, and a TFT is formed in the TFT region by using the first photoresist pattern. The first photoresist pattern is removed. A passivation layer is formed on the overall surface of the transparent insulating substrate, and a second photoresist pattern is formed on a region of the passivation layer other than regions corresponding to the gate pad and the data pad. The second photoresist pattern formed in the pixel region is removed through ashing.

Description

Method for fabricating thin film transistor array substrate

1 through 10 are cross-sectional views of respective manufacturing process steps of a thin film transistor array substrate according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

G-PAD: Gate Pad Area D-PAD: Data Pad Area

D-line: data line area PXL: pixel area

G-line: gate line region TFT: thin film transistor region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT) array substrate for a liquid crystal display (LCD), and more particularly, a photoresist ashing stopper for an active layer in a pixel region. The present invention relates to a method for manufacturing a thin film transistor array substrate for a liquid crystal display device which can effectively improve uniformity of pixel electrodes formed in a pixel region by performing a photoresist ashing process.

In today's information society, the role of electronic displays has become very important, and various electronic displays have been widely used in various industrial fields. In the electronic display device field, electronic display devices having new functions suitable for the demands of the information society, which have been continuously developed and diversified, are continuously being developed. In general, an electronic display device refers to a device that transmits various pieces of information to a human through vision. That is, an electronic display device refers to an electronic device that converts an electronic information signal output from various electronic devices into an optical information signal that can be recognized by a human eye, and is a device that plays a role of a bridge between humans and electronic devices. It can be said.

In such an electronic display device, when an optical information signal is displayed by a light emitting phenomenon, it is referred to as a light emitting display device, and when it is displayed by light modulation due to reflection, scattering, or interference phenomenon, it is called a light receiving display device. Light emitting displays, also called active display devices, include cathode ray tube (CRT), plasma display panel (PDP), organic electroluminescent display (OLD), and light emitting diodes (LED). Light Emitting Diode (LED) etc. can be mentioned. The light receiving display device, which is called a passive display device, may include a liquid crystal display (LCD) and an electrophoretic image display (EPID).

Cathode ray tube display device, which is used for television and computer monitor, and has the longest history, has the highest market share in terms of economy, but has many disadvantages such as heavy weight, large volume and high power consumption. .

Recently, due to the rapid progress of semiconductor technology, there is a demand for a flat panel display device as an electronic display device suitable for a new environment in accordance with the trend of lowering and lowering power of various electronic devices and miniaturization, thinning, and lightening of electronic devices. It is rapidly increasing. Accordingly, flat panel display devices such as a liquid crystal display (LCD), a plasma display device (PDP), an organic EL display device (OELD), and the like have been developed, and among these flat panel display devices, it is easy to miniaturize, light weight, and thinner. In particular, liquid crystal display devices having low power consumption and low driving voltage are drawing attention.

In the liquid crystal display device, a liquid crystal material having anisotropic dielectric constant is injected between a color filter substrate on which a color filter and a black matrix are formed, and a thin film transistor array substrate on which a thin film transistor and a pixel electrode are formed. The display device expresses a desired image by adjusting the intensity of an electric field formed in the liquid crystal material by applying different potentials to the molecules, thereby changing the molecular arrangement of the liquid crystal material, and controlling the amount of light transmitted through the transparent insulating substrate.

Since the manufacturing process of the thin film transistor array substrate requires a plurality of mask processes, the manufacturing process is complicated and becomes a major factor in the increase in manufacturing cost of the liquid crystal display device. In order to solve this problem, the manufacturing process of the thin film transistor array substrate has been developed to reduce the number of photographic processes requiring a mask. This is because one mask process includes many processes such as a deposition process, a cleaning process, a photolithography process, an etching process, a photoresist ashing process, and an inspection process. Accordingly, in recent years, a manufacturing method using three masks has emerged as a manufacturing process of a thin film transistor array substrate.

However, in the conventional method of manufacturing a thin film transistor array substrate using three masks, when the photoresist ashing process is performed, the selectivity of the gas used in the photoresist ashing process is lowered, thus forming a lower portion of the photoresist in addition to the photoresist. Damage occurred in the membrane. In particular, such damage could reduce the uniformity of the pixel electrode formed in the pixel region.

Accordingly, an object of the present invention is to perform a photoresist ashing process using an active layer as a photoresist ashing stopper in a pixel region, thereby providing uniformity of pixel electrodes formed in the pixel region. It is an object of the present invention to provide a method of manufacturing a thin film transistor array substrate for a liquid crystal display device, which can effectively improve the efficiency.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above may be clearly understood by those skilled in the art from the following description. There will be.

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor array substrate includes: forming a gate line, a gate electrode, and a gate pad after depositing a first metal film on a transparent insulating substrate; Sequentially forming a gate insulating film, an active layer, and a second metal film on the entire surface of the transparent insulating substrate, and forming a first photoresist pattern on the data pad area, the data line area, the pixel area, and the thin film transistor area on the second metal film. Forming a data pad in the data pad region, forming a data line in the data line region, exposing an active layer formed in the pixel region, and using the first photoresist pattern in the thin film transistor region. Forming a thin film transistor, and forming the first photoresist pattern. And forming a passivation film on the entire surface of the transparent insulating substrate, forming a second photoresist pattern on the passivation film except for the upper portion of the gate pad and the upper data pad, and forming the second photoresist pattern formed on the pixel region. Ashing and removing.

In the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the present invention, in the step of forming the first photoresist pattern, the thickness of the first photoresist pattern formed in the pixel region is preferably 3000 kPa to 8000 kPa.

In addition, in the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, in the step of ashing and removing the second photoresist pattern, it is preferable to use a gas including SF6 and O2.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to a preferred embodiment of the present invention will be described in detail with reference to FIGS. 1 to 10. 1 through 10 are cross-sectional views of respective manufacturing process steps of a thin film transistor array substrate according to an exemplary embodiment of the present invention.

First, as shown in FIG. 1, a first metal film such as Al, Mo, Cu, MoW, MoTa, MoNb, Cr, W, or a double layer of Al and Mo is deposited on the transparent insulating substrate 100 by a sputtering method. By patterning the first metal film through a mask process, the gate pad 121 is formed in the gate pad region G-PAD, the gate line 122 is formed in the gate line region G-line, and the thin film transistor region TFT. The gate electrode 123 is formed in each.

Next, as shown in FIG. 2, an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the transparent insulating substrate 100 to form the gate insulating layer 120, and sequentially amorphous silicon The active layer 130 is formed by depositing a material, and a second metal layer 140 is formed by sequentially depositing a metal material such as Al, AlNd, Cr, Mo, Cu, or the like.

Next, as shown in FIG. 3, the data pad region D-PAD, the data line region D-line, the pixel region PXL, and the gate line region G-line on the second metal layer 140. And a first photoresist pattern 150 in the thin film transistor region TFT. Here, the first photoresist pattern 150 is formed by a photolithography process using a diffraction mask or a halftone mask and is formed in the pixel region PXL and the gate line region G-line. The first photoresist pattern 150 formed in a region of the pattern 150 and the thin film transistor region TFT that faces the gate electrode 123 is thinner than the first photoresist pattern 150 in another region. On the other hand, the thickness of the first photoresist pattern 150 formed in the pixel region PXL and the gate line region G-line is preferably between 3000 kPa and 8000 kPa. Thus, even if the second metal layer 140 and the active layer 130 are etched in a subsequent process, the active layer formed in the pixel region PXL and the gate line region G-line may remain.

Next, the second metal film 140 and the active layer 130 in the region where the first photoresist pattern 150 is not formed are etched using the first photoresist pattern 150 as a mask, as shown in FIG. 4. As described above, a data pad including the etched second metal layer 141 and the active layer 131 and a data line including the etched second metal layer 142 and the active layer 132 are formed. Subsequently, the gate electrode 123 is formed in the first photoresist pattern 150 and the thin film transistor region TFT formed in the pixel region PXL and the gate line region G-line through a photoresist ashing process. The first photoresist pattern 150 formed in the opposing area is removed. Here, in the photoresist ashing process, the photoresist ashing process may be performed using a gas including SF6 and O2. Thereby, the execution time of the photoresist ashing process can be effectively reduced.

Subsequently, the second metal layer 140 is etched using the remaining first photoresist pattern 150 as a mask, thereby forming the pixel region PXL and the gate line region G-line, as shown in FIG. 4. The active layer 133 is exposed, and the thin film transistor includes a gate electrode 123, a gate insulating layer 120, a semiconductor layer 134, a source electrode 143, and a drain electrode 144 in the thin film transistor region TFT. Is formed.

Next, the remaining first photoresist pattern 150 is removed using a photoresist stripper, and an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the transparent insulating substrate 100. The passivation film 160 is formed. Subsequently, as illustrated in FIG. 5, the second photoresist pattern 170 is formed on the passivation layer 160 except for the upper portion of the gate pad 121 and the upper portion of the data pads 131 and 141. Here, the second photoresist pattern 170 is formed by a photolithography process using a diffraction mask or a halftone mask, and the second photoresist pattern formed in the pixel region PXL and the gate line region G-line. The second photoresist pattern 170 formed between the 170 and the thin film transistor region TFT and the gate line region G-line is thinner than the second photoresist pattern 170 of the other region.

Next, as shown in FIG. 6, the passivation film 160 in the region where the second photoresist pattern 170 is not formed is etched using the second photoresist pattern 170 as a mask. Subsequently, the second photoresist pattern 170, the thin film transistor region TFT and the gate line region G formed in the pixel region PXL and the gate line region G-line through a photoresist ashing process. -line) to remove the second photoresist pattern 170 formed. Here, the active layer 133 formed in the pixel region PXL and the gate line region G-line may be used as a photoresist ashing stopper when the photoresist ashing process is performed, and thus photoresist. Although damage is caused to the passivation film 160 formed in the pixel region PXL and the gate line region G-line by the gas used in the ashing process, the gas used in the photoresist ashing process is the pixel region PXL and It is possible to effectively suppress the occurrence of damage to the gate insulating film 120 formed in the gate line region G-line. Therefore, the uniformity of the pixel electrode (see 183 of FIG. 10) formed in the pixel region PXL may be improved in a subsequent process.

Here, in the photoresist ashing process, the photoresist ashing process may be performed using a gas including SF6 and O2. Thereby, the execution time of the photoresist ashing process can be effectively reduced.

Next, as illustrated in FIG. 7, the gate insulating layer 120 of the gate pad region G-PAD and the data pad region D-PAD are formed using the remaining second photoresist pattern 170 as a mask. 2 the passivation film 160 between the metal film, the pixel region PXL and the gate line region G-line, and the passivation film 160 between the thin film transistor region TFT and the gate line region G-line. Etch it.

Next, as shown in FIG. 8, the active layer 133 of the pixel region PXL and the gate line region G-line is etched using the remaining second photoresist pattern 170 as a mask.

Next, as shown in FIG. 9, a transparent conductive film 180 such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited on the entire surface of the transparent insulating substrate 100. Next, photoresist 190 is applied.

Next, the second photoresist pattern 170 and the applied photoresist 190 are removed, the transparent conductive film 180 is etched, and the gate connection terminal 181 and the data pad connected to the gate pad 121 are removed. Data connection terminals 182 and pixel electrodes 183, 184, and 185 connected to the 131 and 141 are formed.

In the method of manufacturing the thin film transistor array substrate 100 according to the exemplary embodiment of the present invention, the photoresist ashing process is performed by using the active layer 133 as a photoresist ashing stopper in the pixel region PXL. By doing so, the uniformity of the pixel electrode 183 formed in the pixel region PXL can be effectively improved.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

In the method of manufacturing the thin film transistor array substrate according to the exemplary embodiment of the present invention, the photoresist ashing process is performed by using the active layer as a photoresist ashing stopper in the pixel region. The uniformity of the pixel electrode formed in the region can be effectively improved.

Claims (3)

After depositing a first metal film on the transparent insulating substrate, forming a gate line, a gate electrode and a gate pad; Sequentially forming a gate insulating film, an active layer, and a second metal film on the entire surface of the transparent insulating substrate; Forming a first photoresist pattern on a data pad region, a data line region, a pixel region, a gate line region, and a thin film transistor region on the second metal film; By using the first photoresist pattern, a data pad is formed in the data pad area, a data line is formed in the data line area, an active layer formed in the pixel area and the gate line area is exposed, and the thin film is formed. Forming a thin film transistor in the transistor region; Removing the first photoresist pattern and forming a passivation film on the entire surface of the transparent insulating substrate, and then forming a second photoresist pattern on the passivation film except for the upper portion of the gate pad and the upper data pad; And And ashing and removing the second photoresist pattern formed in the pixel region and the gate line region. The method of claim 1, In the step of forming the first photoresist pattern, And a thickness of the first photoresist pattern formed in the pixel region and the gate line region is 3000 kPa to 8000 kPa. The method of claim 1, In the step of ashing and removing the second photoresist pattern, A method of manufacturing a thin film transistor array substrate, wherein a gas containing SF6 and O2 is used.

Images