KR20070064841A - Capillary for coating insulated material and wire bonding method - Google Patents

Capillary for coating insulated material and wire bonding method Download PDF

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Publication number
KR20070064841A
KR20070064841A KR1020050125366A KR20050125366A KR20070064841A KR 20070064841 A KR20070064841 A KR 20070064841A KR 1020050125366 A KR1020050125366 A KR 1020050125366A KR 20050125366 A KR20050125366 A KR 20050125366A KR 20070064841 A KR20070064841 A KR 20070064841A
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capillary
wire
bonding
coating
insulating material
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KR1020050125366A
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Korean (ko)
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강동우
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삼성전자주식회사
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Publication of KR20070064841A publication Critical patent/KR20070064841A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H01L2224/78302—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch

Abstract

A capillary for coating an insulation material and a wire bonding method using the same are provided to stably perform a wire bonding process by coating a surface of a bonding wire with the insulation material of gel state. A capillary body(12) has a through-hole(13), through which a bonding wire is inserted in one end of the through-hole, and is drawn out from the other end. A coating tool(16) is inserted in the outer end of the body of the capillary body to coat a surface of the bonding wire drawn out from the other end with an insulation material(18) of gel state. The coating tool has a tool body(17) disposed in a groove(14) formed on an inner surface of the through-hole.

Description

절연 물질 코팅용 캐필러리 및 그를 이용한 와이어 본딩 방법{Capillary for coating insulated material and wire bonding method}Capillary for insulating material coating and wire bonding method using the same {Capillary for coating insulated material and wire bonding method}

도 1은 본 발명의 실시예에 따른 절연 물질 코팅용 캐필러리를 보여주는 분해사시도이다.1 is an exploded perspective view showing a capillary for insulating material coating according to an embodiment of the present invention.

도 2는 도 1의 횡 단면도이다.2 is a cross-sectional view of FIG. 1.

도 3은 도 1의 종 단면도이다.3 is a longitudinal cross-sectional view of FIG. 1.

도 4는 본 발명의 실시예에 따른 캐필러리를 이용한 와이어 본딩 공정을 보여주는 단면도이다.4 is a cross-sectional view showing a wire bonding process using a capillary according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

10 : 캐필러리 12 : 캐필러리 몸체10: capillary 12: capillary body

13 : 관통 구멍 14 : 설치홈13 through hole 14 mounting groove

16 : 코팅 툴 17 : 툴 몸체16: coating tool 17: tool body

18 : 절연 물질 20, 21 : 본딩 와이어18: insulating material 20, 21: bonding wire

30 : 배선기판 32 : 기판 패드30: wiring board 32: board pad

40 : 하부 칩 42, 52 : 칩 패드40: lower chip 42, 52: chip pad

50 : 상부 칩50: upper chip

본 발명은 반도체 패키지용 와이어 본딩 기술에 관한 것으로, 더욱 상세하게는 와이어 본딩을 진행하면서 본딩 와이어에 겔 상태의 절연 물질을 코팅하는 절연 물질 코팅용 캐필러리 및 그를 이용한 와이어 본딩 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wire bonding technology for semiconductor packages, and more particularly, to a capillary for insulating material coating for coating an insulating material in a gel state on a bonding wire while the wire bonding is performed, and a wire bonding method using the same.

반도체 패키지의 제조 공정에 있어서 와이어 본딩이란 반도체 칩(또는 다이)과 배선기판을 본딩 와이어로 연결하는 것을 의미한다. 이때 사용되는 본딩 와이어로는 금(Au)이나 알루미늄(Al)을 주로 사용하고 구리(Cu)를 사용하는 경우도 있다. 배선기판은 리드 프레임을 비롯하여 인쇄회로기판, 세라믹 기판, 테이프 배선기판 등을 포함한다.In the manufacturing process of a semiconductor package, wire bonding means connecting a semiconductor chip (or die) and a wiring board with a bonding wire. In this case, as the bonding wire used, gold (Au) or aluminum (Al) may be mainly used, and copper (Cu) may be used. The wiring board includes a lead frame, a printed circuit board, a ceramic board, a tape wiring board, and the like.

반도체 칩과 배선기판을 본딩 와이어로 연결해 주는 장비를 와이어 본더(wire bonder)라 하며, 와이어 본더는 실질적인 와이어 본딩 공정을 진행하는 캐필러리(capillary)를 포함한다.The equipment that connects the semiconductor chip and the wiring board with the bonding wire is called a wire bonder, and the wire bonder includes a capillary that performs a substantial wire bonding process.

한편 전자기기들의 경박단소화 추세에 따라 그의 핵심 소자인 반도체 패키지의 고밀도, 고실장화가 중요한 요인으로 대두되고 있으며, 이에 대응하기 위해서 반도체 칩의 크기는 줄어들면서 칩 패드 수는 증가하고 있다. 또한 복수의 반도체 칩을 3차원으로 적층한 적층 칩 기술이 사용되고 있다.On the other hand, with the trend of thin and short electronic devices, high-density and high-mounting of the core package, which is a core element, is becoming an important factor. To cope with this, the number of chip pads is increasing while the size of semiconductor chips is reduced. In addition, a laminated chip technology in which a plurality of semiconductor chips are stacked in three dimensions is used.

이와 같은 반도체 패키지의 경우, 반도체 칩과 배선기판을 연결하는 본딩 와이어의 길이는 길어지고 밀도는 증가하고, 직경은 줄어들고 있다. 이로 인해 상하 본딩 와이어 사이의 전기적 쇼트 문제가 발생되거나, 본딩 와이어가 반도체 칩의 가장자리 부분에 접촉하여 전기적 간섭이 발생될 수 있다.In the case of such a semiconductor package, the length of the bonding wire connecting the semiconductor chip and the wiring board is longer, the density is increased, and the diameter is reduced. As a result, an electric short problem may occur between the upper and lower bonding wires, or electrical interference may occur due to the bonding wires coming into contact with edge portions of the semiconductor chip.

이와 같은 문제점을 해소하기 위한 방안으로서, 절연 물질이 코팅된 본딩 와이어를 이용한 와이어 본딩 방법이 일부 사용되고 있다.In order to solve such a problem, a wire bonding method using a bonding wire coated with an insulating material is partially used.

하지만 절연 물질이 코팅된 본딩 와이어는 와이어 본딩의 작업성이 떨어지는 문제점을 안고 있다. 즉 와이어 본딩 공정 중 볼 본딩을 진행하기 위해서, 본딩 와이어의 끝단에 볼을 형성해야 하는데 절연 물질로 인하여 볼이 잘 형성되지 않는 문제가 발생되고 있다.However, the bonding wire coated with an insulating material has a problem of poor workability of wire bonding. That is, in order to proceed with ball bonding during the wire bonding process, a ball must be formed at the end of the bonding wire, but a problem is that a ball is not formed well due to an insulating material.

따라서, 본 발명의 목적은 와이어 본딩의 작업성과 본딩 와이어의 절연성을 함께 확보할 수 있도록 하는 데 있다.Accordingly, it is an object of the present invention to ensure both workability of wire bonding and insulation of the bonding wire.

상기 목적을 달성하기 위하여, 본 발명은 금 소재의 본딩 와이어를 사용하여 와이어 본딩을 진행하면서 와이어 본딩 공정 중에 본딩 와이어에 겔 상태의 절연 물질을 코팅할 수 있는 캐필러리를 제공한다. 즉 본 발명은 일단으로 본딩 와이어가 삽입되어 타단으로 본딩 와이어가 인출될 수 있는 관통 구멍이 형성된 캐필러리 본체와, 캐필러리 본체의 타단 안쪽에 설치되어 캐필러리 본체의 타단으로 인출되는 본딩 와이어의 표면에 겔(gel) 상태의 절연 물질을 코팅하는 코팅 툴을 포함하는 절연 물질 코팅용 캐필러리를 제공한다.In order to achieve the above object, the present invention provides a capillary capable of coating the insulating material of the gel state on the bonding wire during the wire bonding process while the wire bonding using the bonding wire of gold material. That is, in the present invention, the capillary body having a through hole through which the bonding wire is inserted into one end and the bonding wire is drawn out to the other end, and the bonding that is installed inside the other end of the capillary body and drawn out to the other end of the capillary body Provided is a capillary for insulating material coating comprising a coating tool for coating an insulating material in a gel state on the surface of a wire.

본 발명에 따른 캐필러리에 있어서, 코팅 툴은 툴 몸체와 절연 물질로 구성된다. 툴 몸체는 캐필러리 본체의 관통 구멍 내벽 안쪽으로 형성된 설치홈에 분리 되어 설치되며, 관통 구멍에 대응되는 내주면을 갖는다. 절연 물질은 겔 상태로 툴 몸체의 내주면에 형성되어 있다.In the capillary according to the invention, the coating tool consists of a tool body and an insulating material. The tool body is installed separately from the installation groove formed inside the through hole inner wall of the capillary body, and has an inner circumferential surface corresponding to the through hole. The insulating material is formed on the inner circumferential surface of the tool body in a gel state.

절연 물질로는 티올(thiol)계를 함유한 에폭시 수지가 사용되며, 실리콘을 더 함유할 수 있다.As the insulating material, an epoxy resin containing a thiol system is used, and may further contain silicon.

그리고 본 발명에 따른 캐필러리에 있어서, 설치홈은 와이어 볼을 형성하는 캐필러리 몸체의 타단보다는 안쪽에 형성하는 것이 바람직하다.And in the capillary according to the present invention, the installation groove is preferably formed in the inner side rather than the other end of the capillary body forming a wire ball.

본 발명은 또한 전술된 캐필러리를 이용한 와이어 본딩 방법을 제공한다. 즉 본 발명은 (a) 캐필러리의 일단으로 본딩 와이어가 삽입되어 캐필러리의 타단으로 본딩 와이어가 노출된 캐필러리와, 일면에 적어도 하나 이상의 반도체 칩이 실장된 배선기판을 준비하는 단계와, (b) 캐필러리의 타단에 와이어 볼을 형성하여 반도체 칩에 볼 본딩하는 단계와, (c) 볼 본딩된 지점에서 캐필러리가 배선기판으로 이동하면서 와이어 루프를 형성하는 단계와, (d) 캐필러리가 배선기판에 와이어 루프와 연결된 본딩 와이어를 스티치 본딩하는 단계를 포함한다. 이때 본딩 와이어가 캐필러리에서 인출되면서 코팅 툴에 의해 표면에 겔 상태의 절연 물질이 코팅된다.The present invention also provides a wire bonding method using the capillary described above. That is, (a) preparing a capillary, in which a bonding wire is inserted into one end of the capillary and the bonding wire is exposed to the other end of the capillary, and a wiring board having at least one semiconductor chip mounted on one surface thereof; (b) forming a wire ball at the other end of the capillary and ball bonding the semiconductor chip, (c) forming a wire loop while the capillary moves to the wiring board at the ball bonded point, and (d) The filler includes stitch bonding a bonding wire connected to the wire loop to the wiring board. At this time, as the bonding wire is drawn out of the capillary, the insulating material in a gel state is coated on the surface by the coating tool.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 1은 본 발명의 실시예에 따른 절연 물질 코팅용 캐필러리(10)를 보여주는 분해사시도이다. 도 2는 도 1의 횡 단면도이다. 그리고 도 3은 도 1의 종 단면도이다.1 is an exploded perspective view showing a capillary 10 for insulating material coating according to an embodiment of the present invention. 2 is a cross-sectional view of FIG. 1. 3 is a longitudinal cross-sectional view of FIG. 1.

도 1 내지 도 3을 참조하면, 본 발명의 실시예에 따른 캐필러리(10)는 종 방향으로 관통 구멍(13)이 형성된 캐필러리 본체(12)와, 관통 구멍(13) 내에 설치된 코팅 툴(16; coating tool)을 포함한다.1 to 3, the capillary 10 according to the embodiment of the present invention has a capillary body 12 having a through hole 13 formed in a longitudinal direction, and a coating provided in the through hole 13. A tool 16;

캐필러리 본체(12)는 일단으로 본딩 와이어(20)가 삽입되어 타단으로 본딩 와이어(20)가 인출될 수 있는 관통 구멍(13)이 종 방향으로 형성되어 있다. 캐필러리 본체(12)의 타단에 근접한 관통 구멍(13)의 내벽 안쪽에 코팅 툴(16)이 설치될 수 있는 설치홈(14)이 형성되어 있다.The capillary body 12 has a through hole 13 formed in the longitudinal direction in which the bonding wire 20 is inserted into one end thereof and the bonding wire 20 can be drawn out to the other end thereof. An installation groove 14 in which the coating tool 16 can be installed is formed in the inner wall of the through hole 13 near the other end of the capillary body 12.

코팅 툴(16)은 캐필러리 본체(12)의 설치홈(14)에 탈착할 수 있도록 설치되어 캐필러리 본체(12)의 관통 구멍(13)을 통과하는 본딩 와이어(20)의 표면에 겔(gel) 상태의 절연 물질(18)을 코팅한다. 코팅 툴(16)은 설치홈(14)에 반으로 분리되어 설치되며, 관통 구멍(13)에 대응되는 내주면을 갖는 툴 몸체(17)와, 툴 몸체(17)의 내주면에 형성된 겔 상태의 절연 물질(18)을 포함한다. 톨 몸체(17)와 본딩 와이어(20)의 상호 접촉으로 인한 본딩 와이어(20)의 손상을 최소화할 수 있도록, 툴 몸체(17)의 소재로는 본딩 와이어(20)보다 경도가 낮은 소재를 사용하는 것이 바람직하다. 절연 물질(18)로는 겔 상태로 존재하며 본딩 와이어(20)의 작은 움직임에도 묻어 나올 수 있고, 스냅 큐어(snap cure)가 가능하고, 금과 반응성이 좋은 티올(thiol)계를 함유한 에폭시 수지를 사용하는 것이 바람직하다. 절연성과 열안정성을 향상시키기 위해서, 절연 물질(18)은 실리콘을 더 함유할 수 있다.The coating tool 16 is installed on the surface of the bonding wire 20 to be detachably inserted into the installation groove 14 of the capillary body 12 and passes through the through hole 13 of the capillary body 12. The insulating material 18 in a gel state is coated. The coating tool 16 is half-separated and installed in the installation groove 14, and has a tool body 17 having an inner circumferential surface corresponding to the through hole 13, and gel insulation formed on the inner circumferential surface of the tool body 17. Material 18. In order to minimize damage of the bonding wire 20 due to mutual contact between the toll body 17 and the bonding wire 20, a material having a lower hardness than the bonding wire 20 is used as the material of the tool body 17. It is desirable to. The insulating material 18 exists in a gel state and can be buried even in small movements of the bonding wire 20, and can be snap cure, and an epoxy resin containing a thiol system that is highly reactive with gold. Preference is given to using. In order to improve insulation and thermal stability, insulating material 18 may further contain silicon.

이때 설치홈(14)에 설치된 코팅 툴(16)과 와이어 볼을 형성하는 캐필러 본체(12)의 타단이 서로 간섭하지 않도록, 설치홈(14)은 와이어 볼이 형성되는 부분보 다는 안쪽의 관통 구멍(13) 부분에 형성된다.At this time, the installation groove 14 is penetrated inward from the portion where the wire ball is formed so that the coating tool 16 installed in the installation groove 14 and the other ends of the capillary body 12 forming the wire ball do not interfere with each other. It is formed in the hole 13 part.

따라서 본 실시예에 따른 캐필러리(10)를 사용함으로써, 작업성이 우수한 기존의 본딩 와이어(20)를 그대로 사용하면서 와이어 본딩 공정 중에 본딩 와이어(20)의 표면에 절연 물질(18)을 코팅할 수 있다.Accordingly, by using the capillary 10 according to the present embodiment, the insulating material 18 is coated on the surface of the bonding wire 20 during the wire bonding process while using the existing bonding wire 20 having excellent workability. can do.

이와 같은 본 실시예에 따른 캐필러리(10)를 이용한 와이어 본딩 공정을 도 4를 참조하여 설명하면 다음과 같다.The wire bonding process using the capillary 10 according to the present embodiment will be described with reference to FIG. 4 as follows.

먼저 와이어 본딩 공정은 일단으로 본딩 와이어(20)가 삽입되어 타단으로 본딩 와이어(20)가 노출된 캐필러리(10)와, 상부면에 반도체 칩(40, 50)들이 적층된 배선기판(30)을 준비하는 단계로부터 출발한다. 이때 본딩 와이어(20)로는 작업성이 좋은 금선이 사용될 수 있다. 배선기판(30)에 실장된 하부 칩(40)의 칩 패드(42)와 배선기판(30)의 기판 패드(32)는 본딩 와이어(21)에 의해 연결되어 있다. 본딩 와이어(21)의 표면에는 절연 물질(18)이 코팅되어 있다.First, in the wire bonding process, the capillary 10 having the bonding wire 20 inserted into one end and the bonding wire 20 exposed at the other end thereof, and the wiring board 30 having the semiconductor chips 40 and 50 stacked on the upper surface thereof. Start from the stage of preparation. In this case, a gold wire having good workability may be used as the bonding wire 20. The chip pad 42 of the lower chip 40 mounted on the wiring board 30 and the board pad 32 of the wiring board 30 are connected by a bonding wire 21. An insulating material 18 is coated on the surface of the bonding wire 21.

다음으로 캐필러리(10)의 타단에 와이어 볼을 형성하여 상부 칩(50)의 칩 패드(52)에 볼 본딩하는 단계가 진행된다. 예컨대, EPO(Electric Frame Off) 방전을 통해 캐필러리(10)의 끝단으로 돌출된 본딩 와이어(20) 끝단에 와이어 볼을 형성한 다음 상부 칩(50)의 칩 패드(52)에 소정의 하중과 초음파 에너지를 캐필러리(10)의 하단에 전달하면, 볼이 눌리면서 칩 패드(52)에 접합된다. 도면부호 22는 칩 패드(52)에 볼 본딩된 부분을 나타낸다.Next, a wire ball is formed at the other end of the capillary 10 and the ball bonding is performed on the chip pad 52 of the upper chip 50. For example, a wire ball is formed at the end of the bonding wire 20 protruding to the end of the capillary 10 through the electric frame off (EPO) discharge, and then a predetermined load is applied to the chip pad 52 of the upper chip 50. When the ultrasonic energy is transferred to the lower end of the capillary 10, the ball is pressed and bonded to the chip pad 52. Reference numeral 22 denotes a ball bonded portion to the chip pad 52.

다음으로 볼 본딩된 지점에서 캐필러리(10)가 배선기판(30)으로 이동하면서 와이어 루프를 형성한다.Next, at the ball bonded point, the capillary 10 moves to the wiring board 30 to form a wire loop.

마지막으로 캐필러리(10)가 배선기판(30)의 기판 패드(32)에 와이어 루프와 연결된 본딩 와이어(20)를 스티치 본딩(stitch bonding)으로 마무리함으로써 와이어 본딩 공정이 완료된다.Finally, the wire bonding process is completed by the capillary 10 finishing the bonding wire 20 connected to the wire loop to the substrate pad 32 of the wiring board 30 by stitch bonding.

이때 본딩 와이어(20)는 캐필러리 몸체(12)의 관통 구멍(13)에서 인출되면서 코팅 툴(16)에 의해 표면에 겔 상태의 절연 물질(18)이 코팅되기 때문에, 와이어 본딩 공정과 절연 물질 코팅 공정을 동시에 진행할 수 있다. 본딩 와이어(20)에 겔 상태의 절연 물질(18)이 코팅되기 때문에, 와이어 볼을 용이하게 형성할 수 있다. 그리고 겔 상태의 절연 물질(18)은 경화되어 본딩 와이어(20)의 표면에 절연 물질(18)로 구성된 코팅막을 형성하게 된다.In this case, since the bonding wire 20 is drawn out from the through hole 13 of the capillary body 12 and the insulating material 18 in a gel state is coated on the surface by the coating tool 16, the wire bonding process and the insulation are performed. The material coating process can proceed simultaneously. Since the bonding material 20 is coated with the insulating material 18 in a gel state, the wire ball can be easily formed. The insulating material 18 in a gel state is cured to form a coating film made of the insulating material 18 on the surface of the bonding wire 20.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다. 예컨대 본 실시예에서는 일반적인 볼 본딩을 포함하는 와이어 본딩 공정을 예시하였지만 범프 리버스 본딩 등 다양한 와이어 본딩 공정에 본 실시예에 따른 캐필러리가 사용될 수 있다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. For example, in the present embodiment, a wire bonding process including a general ball bonding is illustrated, but the capillary according to the present embodiment may be used in various wire bonding processes such as bump reverse bonding.

따라서, 본 발명의 구조를 따르면 본딩 와이어가 인출되는 캐필러리 몸체의 관통 구멍에 코팅 툴을 설치함으로써, 작업성이 좋은 금 소재의 본딩 와이어를 사 용하여 와이어 본딩 공정을 진행할 수 있다.Therefore, according to the structure of the present invention by installing a coating tool in the through-hole of the capillary body from which the bonding wire is drawn out, it is possible to proceed with the wire bonding process using a bonding wire of gold material having good workability.

그리고 와이어 본딩 공정 중 캐필러리 몸체의 타단으로 인출되는 본딩 와이어의 표면에 겔 상태의 절연 물질이 코팅되기 때문에, 와이어 볼을 형성하는 공정을 포함하여 와이어 본딩 공정을 안정적으로 진행할 수 있고, 본딩 와이어 사이의 전기적 쇼트 및 본딩 와이어와 반도체 칩 사이의 접촉으로 인한 전기적 간섭 현상을 억제할 수 있다.In addition, since the insulating material in a gel state is coated on the surface of the bonding wire drawn out to the other end of the capillary body during the wire bonding process, the wire bonding process may be stably performed, including a process of forming a wire ball. It is possible to suppress the electrical interference due to the electrical short between and the contact between the bonding wire and the semiconductor chip.

또한 와이어 본딩 공정과 절연 물질 코팅 공정을 동시에 진행하기 때문에, 생산성을 향상시킬 수 있다.In addition, since the wire bonding process and the insulating material coating process are performed at the same time, productivity can be improved.

Claims (6)

일단으로 본딩 와이어가 삽입되어 타단으로 본딩 와이어가 인출될 수 있는 관통 구멍이 형성된 캐필러리 본체와;A capillary body having a through hole through which a bonding wire is inserted into one end and a bonding wire can be drawn out to the other end; 상기 캐필러리 본체의 타단 안쪽에 설치되어 상기 캐필러리 본체의 타단으로 인출되는 상기 본딩 와이어의 표면에 겔(gel) 상태의 절연 물질을 코팅하는 코팅 툴;을 포함하는 것을 특징으로 하는 절연 물질 코팅용 캐필러리.And a coating tool installed inside the other end of the capillary body and coating an insulating material in a gel state on the surface of the bonding wire drawn out to the other end of the capillary body. Capillary for coating. 제 1항에 있어서, 상기 코팅 툴은,The method of claim 1, wherein the coating tool, 상기 캐필러리 본체의 관통 구멍 내벽 안쪽으로 형성된 설치홈에 분리되어 설치되며, 상기 관통 구멍에 대응되는 내주면을 갖는 툴 몸체와;A tool body which is separately installed in an installation groove formed in the inner wall of the through hole of the capillary body and has an inner circumferential surface corresponding to the through hole; 상기 툴 몸체의 내주면에 형성된 겔 상태의 절연 물질;을 포함하는 것을 특징으로 하는 절연 물질 코팅용 캐필러리.Capillary for insulating material coating comprising a; insulating material in a gel state formed on the inner peripheral surface of the tool body. 제 2항에 있어서, 상기 절연 물질은 티올(thiol)계를 함유한 에폭시 수지인 것을 특징으로 하는 절연 물질 코팅용 캐필러리.3. The capillary for insulating material coating according to claim 2, wherein the insulating material is an epoxy resin containing a thiol system. 제 3항에 있어서, 상기 절연 물질은 실리콘을 더 함유하고 있는 것을 특징으로 하는 절연 물질 코팅용 캐필러리.The capillary for insulating material coating according to claim 3, wherein the insulating material further contains silicon. 제 2항 내지 제 4항의 어느 한 항에 있어서, 상기 설치홈은 와이어 볼을 형성하는 상기 캐필러리 몸체의 타단보다는 안쪽에 형성된 것을 특징으로 하는 절연 물질 코팅용 캐필러리.The capillary for coating the insulating material as claimed in any one of claims 2 to 4, wherein the installation groove is formed inside the other end of the capillary body forming the wire ball. 제 5항에 따른 캐필러리를 이용한 와이어 본딩 방법으로,A wire bonding method using a capillary according to claim 5, (a) 상기 캐필러리의 일단으로 본딩 와이어가 삽입되어 상기 캐필러리의 타단으로 상기 본딩 와이어가 노출된 캐필러리와, 일면에 적어도 하나 이상의 반도체 칩이 실장된 배선기판을 준비하는 단계와;(a) preparing a capillary having a bonding wire inserted into one end of the capillary and exposing the bonding wire to the other end of the capillary, and a wiring board having at least one semiconductor chip mounted on one surface thereof; (b) 상기 캐필러리의 타단에 와이어 볼을 형성하여 상기 반도체 칩에 볼 본딩하는 단계와;(b) forming a ball of wire at the other end of the capillary and ball-bonding the semiconductor chip; (c) 상기 볼 본딩된 지점에서 상기 캐필러리가 상기 배선기판으로 이동하면서 와이어 루프를 형성하는 단계와;(c) forming a wire loop while the capillary moves to the wiring board at the ball bonded point; (d) 상기 캐필러리가 상기 배선기판에 상기 와이어 루프와 연결된 상기 본딩 와이어를 스티치 본딩하는 단계;를 포함하며,(d) the capillary stitch bonding the bonding wires connected to the wire loops to the wiring board; 상기 본딩 와이어가 상기 캐필러리에서 인출되면서 상기 코팅 툴에 의해 표면에 겔 상태의 절연 물질이 코팅되는 것을 특징으로 하는 절연 물질 코팅용 캐필러리를 이용한 와이어 본딩 방법.The bonding wire is drawn out of the capillary, the coating tool is a wire bonding method using a capillary for coating the insulating material, characterized in that the coating material is coated on the surface by a gel.
KR1020050125366A 2005-12-19 2005-12-19 Capillary for coating insulated material and wire bonding method KR20070064841A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022215951A1 (en) * 2021-04-07 2022-10-13 백민 Bonding wire for semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022215951A1 (en) * 2021-04-07 2022-10-13 백민 Bonding wire for semiconductor package

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