KR20020050556A - Semiconductor lead frame and semiconductor package applying the same - Google Patents
Semiconductor lead frame and semiconductor package applying the same Download PDFInfo
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- KR20020050556A KR20020050556A KR1020000079731A KR20000079731A KR20020050556A KR 20020050556 A KR20020050556 A KR 20020050556A KR 1020000079731 A KR1020000079731 A KR 1020000079731A KR 20000079731 A KR20000079731 A KR 20000079731A KR 20020050556 A KR20020050556 A KR 20020050556A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체 패키지에 관한 것으로서, 보다 상세하게는 내부리이드가 내부 및 외부단자로 공히 구현가능하도록 구조가 개선된 반도체 리드프레임과 이를 채용한 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor lead frame having an improved structure and a semiconductor package employing the same so that an inner lead can be embodied by both internal and external terminals.
통상적으로, 플립칩(flip) 실장은 베어(bare) 칩을 기판에 직접적으로 부착하는 방식으로, 고속, 고밀도, 다핀화 추세를 지원할 수 있는 새로운 반도체 패키지 방식으로 주목을 받고 있다.In general, flip chip mounting has attracted attention as a new semiconductor package method capable of supporting a high speed, high density, and multipinning trend by directly attaching a bare chip to a substrate.
플립칩 실장은 반도체 칩의 크기가 대략 반도체 패키지의 크기와 상응하여 소형화 및 경량화에 유리하고, 입출력 단자의 거리도 짧아서 전송속도가 라인이 있는 반도체 패키지보다 수십배 빠르다. 일명, 선없는 반도체로도 불리우는 플립칩은 전자부품의 표면실장화 기술이 만들어 낸 최상의 패키지 형태로 차세대 기가급이상 메모리반도체의 주력 반도체 패키지로 채택될 전망이다.Flip chip mounting is advantageous in miniaturization and light weight, in which the size of a semiconductor chip corresponds approximately to that of a semiconductor package, and the distance between input and output terminals is also short, which makes the transfer rate several ten times faster than a semiconductor package having a line. The flip chip, also known as a wireless semiconductor, is expected to be adopted as the flagship semiconductor package of the next generation of giga-class memory semiconductors in the best package form created by the surface mount technology of electronic components.
도 1은 종래의 제1 실시예에 따른 플립칩 방식의 반도체 패키지(10)를 도시한 것이다.1 illustrates a flip chip type semiconductor package 10 according to a first embodiment of the present invention.
도면을 참조하면, 상기 반도체 패키지(10)는 리이드(11)와, 다이패드(12)와, 상기 리이드(11)의 팁부에 접착된 절연테이프(13)와 상기 다이패드(12)의 윗면에 접착된 에폭시재(14)를 매개로 하여 부착되는 반도체 칩(15)과, 상기 리이드(11)와 반도체 칩(15)을 와이어 본딩시키는 와이어(16)와, 상기 리이드(11)와 반도체 칩(15)을 몰딩하는 몰딩재(17)와, 상기 리이드(11)중에서 외부로 노출되는 부분에 부착되는 솔더볼(18)을 포함한다.Referring to the drawings, the semiconductor package 10 may include a lead 11, a die pad 12, an insulating tape 13 adhered to a tip of the lead 11, and an upper surface of the die pad 12. The semiconductor chip 15 attached via the bonded epoxy material 14, the wire 16 for wire bonding the lead 11 and the semiconductor chip 15, the lead 11 and the semiconductor chip ( And a solder ball 18 attached to a portion of the lead 11 that is exposed to the outside.
이러한 구조를 가지는 반도체 패키지(10)는 두꺼운 금속소재로 된 반도체 리드프레임중에서 상기 다이패드(12)가 형성되는 부분과, 솔더볼(18)이 부착되는 부분이외에는 반에칭(half etching)을 수행하게 된다. 이때, 상기 리이드(11)는 그 윗면이 몰딩재(17)로 몰딩되기 이전에는 외부로 전면 노출된 상태에서 반도체 칩(15)과 와이어 본딩되어 내부단자의 역할을 하게 된다. 또한, 상기 리이드(11)는 상기 반도체 칩(15)에 대하여 반대되는 면의 일부, 즉, 상기 솔더볼(18)이 부착되는 부분이 몰딩후 외부로 노출되고, 이 부위에 솔더볼(18)이 부착되어 다른 기판과 접속되는 외부단자로서 역할을 수행하게 된다.The semiconductor package 10 having such a structure performs half etching except for a portion where the die pad 12 is formed and a portion where the solder ball 18 is attached in the semiconductor lead frame made of a thick metal material. . At this time, the lead 11 is wire-bonded with the semiconductor chip 15 in a state where the upper surface is exposed to the outside before being molded into the molding material 17 to serve as an internal terminal. In addition, the lead 11 is exposed to a part of the surface opposite to the semiconductor chip 15, that is, the part to which the solder ball 18 is attached to the outside after molding, and the solder ball 18 is attached to this part. It serves as an external terminal connected to the other substrate.
도 2는 종래의 제2 실시예에 따른 반도체 패키지(20)를 도시한 것이다.2 shows a semiconductor package 20 according to a second conventional embodiment.
도면을 참조하면, 상기 반도체 패키지(20)는 리이드(21)와, 상기 리이드(21)의 팁부에 접착된 절연테이프(22)를 매개로 하여 부착되는 반도체 칩(23)과, 상기 리이드(21)와 반도체 칩(23)을 와이어 본딩시키는 와이어(24)와, 상기 리이드(21)와 반도체 칩(23)을 몰딩하는 몰딩재(25)를 포함한다.Referring to the drawings, the semiconductor package 20 includes a lead 21, a semiconductor chip 23 attached through an insulating tape 22 adhered to a tip of the lead 21, and the lead 21. ) And a wire 24 for wire bonding the semiconductor chip 23, and a molding material 25 for molding the lead 21 and the semiconductor chip 23.
이러한 구조를 가지는 반도체 패키지(20)는 반도체 리드프레임에 다운셋(down set) 또는 업셋(up set)공정을 통하여 상기 리이드(21)의 팁부분이 소정각도로 절곡되어 있다. 또한, 상기 리이드(21)의 일부는 몰딩재(25)로 몰딩후 외부로 노출되어 외부단자의 역할을 하게 된다.In the semiconductor package 20 having such a structure, the tip portion of the lead 21 is bent at a predetermined angle through a down set or up set process in the semiconductor lead frame. In addition, a part of the lead 21 is exposed to the outside after molding with the molding material 25 to serve as an external terminal.
그런데 종래의 기술에 따른 반도체 패키지는 다음과 같은 문제점이 있다.However, the semiconductor package according to the related art has the following problems.
이러한 플립칩 실장에 따른 반도체 패키지는 리드프레임이 두께가 얇기 때문에 스탬핑 공정을 통하여 리드를 형성하게 될때에 금형의 타발에 의한 변형이 쉽게 발생하게 된다. 또한, 반도체 칩이 리이드의 팁부분에 실장되므로, 반도체 칩과 리이드와의 절연을 위하여 개재되는 절연물을 도포해야 하는데, 이러한 절연물의 도포공정은 반도체 패키지를 제조하는 과정에서 부품의 균일한 품질을 유지시키는 것을 어렵게 하고, 제조공정또한 복잡하게 한다.Since the lead frame is thin in the semiconductor package according to the flip chip mounting, deformation due to the punching of the mold is easily generated when the lead is formed through the stamping process. In addition, since the semiconductor chip is mounted on the tip of the lead, an insulator interposed to insulate the semiconductor chip from the lead must be applied, and the coating process of the insulator maintains a uniform quality of the component in the process of manufacturing the semiconductor package. This makes it difficult and complicated the manufacturing process.
본 발명은 상기와 같은 문제점을 해결하기 위하여 창안된 것으로서, 리이드의 일부에 몰딩재를 우선적으로 도포하고 반도체 칩을 장착하여 내부 및 외부단자로 공히 사용가능하도록 구조가 개선된 반도체 리드프레임과, 이를 채용한 반도체 패키지를 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, a semiconductor lead frame having a structure improved to be used as both internal and external terminals by first applying a molding material to a portion of the lead and mounting a semiconductor chip, and Its purpose is to provide an adopted semiconductor package.
도 1은 종래의 제1 실시예에 따른 반도체 패키지를 도시한 단면도,1 is a cross-sectional view showing a semiconductor package according to a first embodiment of the present invention;
도 2는 종래의 제2 실시예에 따른 반도체 패키지를 도시한 단면도,2 is a cross-sectional view showing a semiconductor package according to a second embodiment of the present invention;
도 3a는 본 발명의 제1 실시예에 따른 반도체 리드프레임에 몰딩재가 도포된 이후의 상태를 도시한 단면도,3A is a cross-sectional view illustrating a state after a molding material is applied to a semiconductor lead frame according to a first embodiment of the present invention;
도 3b는 도 3a의 반도체 리드프레임상에 반도체 칩이 부착된 반도체 패키지를 도시한 단면도,3B is a cross-sectional view illustrating a semiconductor package having a semiconductor chip attached to the semiconductor lead frame of FIG. 3A;
도 4a는 본 발명의 제2 실시예에 따른 반도체 리드프레임에 몰딩재가 도포된 이후의 상태를 도시한 단면도,4A is a cross-sectional view illustrating a state after a molding material is applied to a semiconductor lead frame according to a second embodiment of the present invention;
도 4b는 도 4a의 반도체 리드프레임상에 반도체 칩이 부착된 반도체 패키지를 도시한 단면도.4B is a cross-sectional view illustrating a semiconductor package in which semiconductor chips are attached to the semiconductor lead frame of FIG. 4A.
<도면의 주요 부분에 대한 간단한 설명><Brief description of the main parts of the drawing>
10,20...반도체 패키지11,21...리이드10,20 ... Semiconductor Package 11,21 ... Lead
12...다이패드13,22...절연테이프12 ... Dip pad 13,22 ... Insulation tape
15,23..반도체 칩16,24...와이어Semiconductor chips 16, 24 ...
17,25...몰딩재18...솔더 볼17, 25 Molding material 18 Solder ball
30,40...반도체 패키지31,41...리이드30,40 ... Semiconductor Package 31,41 ... Lead
32,42...다이패드33,43...제1 몰딩재32, 42 ... Diap 33, 43 ... 1st molding material
35,45...반도체 칩36,46...와이어35,45 ... semiconductor chip 36,46 ... wire
37,47...제2 몰딩재38,48...솔더 볼37,47 ... 2nd molding material 38,48 ... solder ball
400...절연물400 ... Insulation
상기와 같은 목적을 달성하기 위하여 본 발명의 일 측면에 따른 반도체 패키지는,In order to achieve the above object, a semiconductor package according to an aspect of the present invention,
다수개의 리이드;A plurality of leads;
상기 리이드의 상하면중 적어도 어느 한면이상에 형성되는 제1 몰딩재;A first molding material formed on at least one surface of upper and lower surfaces of the lead;
다이패드상에 접착물을 매개로 하여 장착되는 반도체 칩;A semiconductor chip mounted on the die pad via an adhesive;
상기 리이드와 반도체 칩을 와이어본딩시키는 와이어;A wire for wire bonding the lead and the semiconductor chip;
상기 리이드의 일부에 연결되어 외부기판의 단자와 전기적으로 접속되는 솔더 볼; 및A solder ball connected to a part of the lead and electrically connected to a terminal of an external substrate; And
상기 리이드와 반도체 칩을 감싸는 제2 몰딩재;를 포함하는 것을 특징으로 한다.And a second molding material surrounding the lead and the semiconductor chip.
또한, 상기 리이드에는 상기 반도체 칩과 와이어본딩되는 상면에는 적어도 일부분 이상의 영역에, 그 반대면에는 상기 솔더볼과 접속되는 부분을 제외한 영역에 상기 제1 몰딩재가 형성되는 것을 특징으로 한다.The first molding material may be formed on at least a portion of the upper surface of the lead and wire bonded to the semiconductor chip, and at a region other than a portion connected to the solder ball on the opposite surface thereof.
본 발명의 다른 측면에 따른 반도체 리드프레임은,A semiconductor lead frame according to another aspect of the present invention,
다수개로 형성되어 일면이 반도체 칩과 와이어본딩되고, 다른 면이 외부기판의 단자와 전기적으로 접속되는 리이드; 및A lead formed of a plurality of wire-bonded surfaces of the semiconductor chip and electrically connected to a terminal of an external substrate; And
상기 리이드의 상하면중 적어도 어느 한면이상에 형성되는 몰딩재;를 포함하는 것을 특징으로 한다.It characterized in that it comprises a; molding material formed on at least one surface of the upper and lower surfaces of the lead.
또한, 상기 몰딩재는 리이드중에서 반도체 칩과 와이어본딩되는 상면에는 적어도 일부분 이상의 영역에, 그 반대면에는 외부기판의 단자와 접속되는 부분을 제외하고 형성되는 것을 특징으로 한다.In addition, the molding material is formed on at least a portion of the upper surface of the lead wire-bonded with the semiconductor chip, the opposite surface is formed except the portion connected to the terminal of the external substrate.
이하에서 첨부된 도면을 참조하면서 본 발명의 일 실시예에 따른 반도체 리드프레임과 이를 채용한 반도체 패키지를 상세하게 설명하고자 한다.Hereinafter, a semiconductor lead frame and a semiconductor package employing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 3a는 본 발명의 제1 실시예에 따른 반도체 리드프레임에 몰딩재가 도포된 이후의 상태를 도시한 것이다.3A illustrates a state after a molding material is applied to a semiconductor lead frame according to a first embodiment of the present invention.
도면을 참조하면, 반도체 리드프레임은 스탬핑공정이나 에칭공정을 통하여 소정 패턴을 가진 리이드(31)와, 추후 기술될 반도체 칩이 장착되는 다이패드(32)를 포함한다.Referring to the drawings, the semiconductor lead frame includes a lead 31 having a predetermined pattern through a stamping process or an etching process, and a die pad 32 on which a semiconductor chip to be described later is mounted.
이때, 상기 리이드(31)의 상하면에는 제1 몰딩재(33)가 형성되어 있다. 상기 제1 몰딩재(33)는 상기 리이드(31)의 상하면과, 상기 다이패드(32)의 아랫면을 통하여 도포되어 있다. 상기 리이드(31)는 상기 제1 몰딩재(33)에 의하여 상부 및 하부에 일부가 노출되고, 나머지 부분은 모두 상기 제1 몰딩재(33)로 몰딩되어 있다. 이에 따라, 상기 리이드(31)는 내부 및 외부 단자로 사용되는 부분이 노출되어 있는 구조이다.At this time, the first molding member 33 is formed on the upper and lower surfaces of the lead 31. The first molding material 33 is applied through the upper and lower surfaces of the lead 31 and the lower surface of the die pad 32. The lead 31 is partially exposed to the upper and lower portions by the first molding material 33, and the rest of the lead 31 is molded into the first molding material 33. Accordingly, the lead 31 has a structure in which portions used as internal and external terminals are exposed.
도 3b는 도 3a의 반도체 리드프레임을 이용하여 반도체 패키지(30)를 제조한 이후의 상태를 도시한 것이다.3B illustrates a state after fabricating the semiconductor package 30 using the semiconductor lead frame of FIG. 3A.
도면을 참조하면, 상기 반도체 패키지(30)는 리이드(31)와, 다이패드(32)를 포함한다. 상기 리이드(31)의 상하면과 다이패드(32)의 아랫면에는 제1 몰딩재(33)가 몰딩되어 있다. 상기 다이패드(32)의 윗면에는 접착제(34)를 매개로 하여 반도체 칩(35)이 장착되어 있다. 상기 리이드(31)의 윗면에 제1 몰딩재(33)에 의하여 몰딩되지 않은 부분(31a)과, 상기 반도체 칩(35)은 와이어(36)로 와이어 본딩되어 있다. 상기 리이드(31)와 반도체 칩(35)이 와이어본딩된 부분에는 이를 보호하기 위하여 제2 몰딩재(37)가 몰딩되어 있다.Referring to the drawings, the semiconductor package 30 includes a lead 31 and a die pad 32. The first molding material 33 is molded on the upper and lower surfaces of the lead 31 and the lower surface of the die pad 32. The semiconductor chip 35 is mounted on the upper surface of the die pad 32 via the adhesive 34. The portion 31a which is not molded by the first molding material 33 on the upper surface of the lead 31 and the semiconductor chip 35 are wire bonded to the wire 36. A second molding material 37 is molded in the wire-bonded portion of the lead 31 and the semiconductor chip 35 to protect the lead 31 and the semiconductor chip 35.
상기 반도체 칩(35)이 부착되는 부분과 반대되는 리이드(31)에는 상기 제1 몰딩재(33)에 의하여 몰딩되지 않은 부분(31b)이 외부단자로서 역할을 하게 된다. 이 부분(31b)에는 외부기판의 단자와 접속가능한 솔더 볼(38)이 부착된다. 상기 솔더 볼(38)이 부착되기 위하여 상기 리이드(31)의 몰딩되지 않은 부분(31b)에 범프역할을 하는 도전재(39)가 채워질 수가 있다.In the lead 31 opposite to the portion to which the semiconductor chip 35 is attached, a portion 31b which is not molded by the first molding material 33 serves as an external terminal. The part 31b is attached with a solder ball 38 which can be connected to a terminal of an external substrate. In order to attach the solder ball 38, the conductive material 39 that serves as a bump may be filled in the unmolded portion 31b of the lead 31.
이처럼, 상기 리이드(31)는 그 상하면에 제1 몰딩재(37)가 형성되어 있고, 몰딩되지 않은 한 부분(31a)은 내부단자로 역할을 수행하기 위하여 반도체 칩(35)과 와이어본딩되고, 몰딩되지 않은 다른 부분(31b)은 솔더 볼(38)이 부착되어 외부단자로서 기능을 수행하게 된다. 즉, 상기 리이드(31)는 내부단자측이 상기 제2 몰딩재(37)에 의하여 몰딩되기 이전에 일부 외부로 노출되어 있는 구조이다. 또한, 상기 제1 몰딩재(37)는 상기 리이드(31)와 반도체 칩(35)간의 절연물로서 역할을 하고 있다.As such, the lead 31 has a first molding material 37 formed on the upper and lower surfaces thereof, and an unmolded portion 31a is wire-bonded with the semiconductor chip 35 to serve as an internal terminal. The other unmolded portion 31b is attached to the solder ball 38 to function as an external terminal. That is, the lead 31 has a structure in which the inner terminal side is partially exposed to the outside before being molded by the second molding material 37. In addition, the first molding material 37 serves as an insulator between the lead 31 and the semiconductor chip 35.
이와 같은 구조를 가지는 반도체 패키지(30)는 상기 솔더 볼(38)이 외부 기판의 단자와 상호 열융착되어 외부 기판의 단자는 솔더 볼(38)과, 각 리이드(31)와, 와이어(36)를 통하여 상기 반도체 칩(35)과 전기적으로 접속이 가능하여 신호를 상호 전달하게 된다.In the semiconductor package 30 having the above structure, the solder balls 38 are thermally fused to the terminals of the external substrate so that the terminals of the external substrate are the solder balls 38, the respective leads 31, and the wires 36. It is possible to electrically connect with the semiconductor chip 35 through the mutual signal transfer.
도 4a는 본 발명의 제2 실시예에 따른 반도체 리드프레임에 몰딩재가 도포된 이후의 상태를 도시한 것이다.4A illustrates a state after a molding material is applied to a semiconductor lead frame according to a second exemplary embodiment of the present invention.
도면을 참조하면, 반도체 리드프레임은 스탬핑 공정을 통하여 다운 셋 또는 업셋으로 팁부가 절곡된 리이드(41)와, 추후 기술될 반도체 칩이 장착되는 다이패드(42)를 포함한다. 상기 리이드(41)의 아랫면에는 제1 몰딩재(43)가 형성되어 있다. 상기 제1 몰딩재(43)는 상기 리이드(41)의 윗면에는 형성되지 않고 아랫면에만 형성되어 있고, 상기 리이드(41)의 아랫면에서도 일부가 상기 제1 몰딩재(43)에 의하여 몰딩되지 않은 부분(41a)이 형성되어 있다. 이 부분은 외부단자로서 역할을 하게 된다. 이에 따라, 상기 리이드(41)는 내부단자는 외부로 완전히 노출되고, 외부단자는 몰딩되지 않은 부분(41a)만 외부로 노출되는 구조이다.Referring to the drawings, the semiconductor lead frame includes a lead 41 having a tip portion bent in a downset or upset through a stamping process, and a die pad 42 on which a semiconductor chip to be described later is mounted. The first molding member 43 is formed on the lower surface of the lead 41. The first molding member 43 is not formed on the upper surface of the lead 41, but is formed only on the lower surface, and a portion of the first molding member 43 is also not molded by the first molding member 43. 41a is formed. This part acts as external terminal. Accordingly, the lead 41 has a structure in which the inner terminal is completely exposed to the outside, and the outer terminal is exposed to the outside only the unmolded portion 41a.
도 4b는 도 4a의 반도체 리드프레임을 이용하여 반도체 패키지(40)를 제조한 이후의 상태를 도시한 것이다.FIG. 4B illustrates a state after fabricating the semiconductor package 40 using the semiconductor lead frame of FIG. 4A.
도면을 참조하면, 상기 반도체 패키지(40)는 리이드(41)와, 다이패드(42)를 포함한다. 상기 리이드(41)의 아랫면에는 제1 몰딩재(43)가 몰딩되어 있다. 상기 다이패드(42)의 윗면에는 접착제(44)를 매개로 하여 반도체 칩(45)이 장착되어 있다. 이때, 상기 리이드(41)의 팁부에도 절연테이프(400)를 추가적으로 형성시키고, 그 윗면에 상기 반도체 칩(45)의 아랫면을 부착시켜서 칩(45)의 고정을 견고하게 할 수도 있을 것이다. 상기 리이드(41)의 윗면과 반도체 칩(45)은 와이어(46)로 와이어 본딩되어 있다. 상기 리이드(41)와 반도체 칩(45)이 와이어본딩되는 부분에는 이를 보호하기 위하여 제2 몰딩재(47)가 몰딩되어 있다.Referring to the drawings, the semiconductor package 40 includes a lead 41 and a die pad 42. The first molding member 43 is molded on the lower surface of the lead 41. The semiconductor chip 45 is mounted on the upper surface of the die pad 42 via the adhesive 44. In this case, the insulating tape 400 may be additionally formed on the tip of the lead 41, and the lower surface of the semiconductor chip 45 may be attached to an upper surface thereof to firmly fix the chip 45. The upper surface of the lead 41 and the semiconductor chip 45 are wire bonded with a wire 46. A second molding material 47 is molded in the portion where the lead 41 and the semiconductor chip 45 are wire bonded to protect the lead 41 and the semiconductor chip 45.
여기서, 상기 리이드(41)는 제1 몰딩재(43)에 의하여 몰딩되지 않은 부분(41a)은 외부단자로서 역할을 하게 된다. 상기 부분(41a)에는 외부기판의 단자와 전기적으로 접속가능한 솔더 볼(48)이 부착되어 있다. 상기 솔더 볼(48)이 부착되기 위하여 상기 리이드(41)의 몰딩되지 않은 부분(41a)에 도전재(49)가 형성될수가 있다.Here, the portion 41a, which is not molded by the first molding member 43, serves as an external terminal. The portion 41a is attached with a solder ball 48 which can be electrically connected to a terminal of an external substrate. In order to attach the solder ball 48, a conductive material 49 may be formed on the unmolded portion 41a of the lead 41.
이처럼, 상기 리이드(41)는 내부단자가 상기 제2 몰딩재(47)로 몰딩되기 이전에 외부로 완전 노출된 상태이다. 반대로, 외부 단자에 해당되는 상기 솔더 볼(48)이 부착되는 부분(41a)은 상기 리이드(41)가 제1 몰딩재(43)에 의하여 일부 몰딩되어 있지 않고 외부로 노출되어 있다.As such, the lead 41 is completely exposed to the outside before the inner terminal is molded into the second molding material 47. On the contrary, in the portion 41a to which the solder ball 48 corresponding to the external terminal is attached, the lead 41 is not partially molded by the first molding material 43 and is exposed to the outside.
이와 같은 구조를 가지는 반도체 패키지(40)는 상기 반도체 칩(45)이 와이어(46)와, 리이드(41)와, 솔더볼(48)를 통하여 외부 기판의 단자와 전기적으로 연결이 되어 있어서 신호를 상호 전달하게 된다.In the semiconductor package 40 having such a structure, the semiconductor chip 45 is electrically connected to a terminal of an external substrate through the wire 46, the lead 41, and the solder ball 48 so that the signals are mutually connected. Will be delivered.
이상의 설명에서와 같이 본 발명의 반도체 리드프레임과 이를 채용한 반도체 패키지는 리이드를 적어도 한면 이상 몰딩하는 몰딩재를 형성하고, 일부를 노출시켜 내부 및 외부단자를 공히 형성시킴으로써 구조가 보다 단순화가 가능하다. 또한, 리이드가 내부 및 외부단자로 동시에 구현가능하게 됨에 따라서 반도체 패키지의 슬림화가 가능하고, 전기적 성질에 대한 신뢰성이 향상된다.As described above, the semiconductor lead frame and the semiconductor package employing the semiconductor lead frame according to the present invention form a molding material for molding at least one surface of the lead, and partially expose the internal and external terminals, thereby simplifying the structure. . In addition, since the lead can be simultaneously implemented by the internal and external terminals, the semiconductor package can be made slim and the reliability of the electrical properties is improved.
본 발명은 도면에 도시된 일 실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호범위는 첨부된 등록청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
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KR100762913B1 (en) * | 2006-11-21 | 2007-10-08 | 주식회사 하이닉스반도체 | Semiconductor package |
KR100891649B1 (en) * | 2002-08-08 | 2009-04-02 | 삼성테크윈 주식회사 | Method of manufacturing semiconductor package |
US7759807B2 (en) | 2006-11-21 | 2010-07-20 | Hynix Semiconductor Inc. | Semiconductor package having structure for warpage prevention |
CN109378308A (en) * | 2014-12-10 | 2019-02-22 | 上海兆芯集成电路有限公司 | Circuit substrate and packaging structure |
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KR940006164B1 (en) * | 1991-05-11 | 1994-07-08 | 금성일렉트론 주식회사 | Semiconductor device and manufacturing method thereof |
JP2837355B2 (en) * | 1994-09-09 | 1998-12-16 | 川崎製鉄株式会社 | Semiconductor IC chip package, method of manufacturing the same, and lead frame |
JPH08148603A (en) * | 1994-11-22 | 1996-06-07 | Nec Kyushu Ltd | Ball grid array type semiconductor device and manufacture thereof |
JP2845841B2 (en) * | 1996-09-27 | 1999-01-13 | 九州日本電気株式会社 | Semiconductor device |
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KR100891649B1 (en) * | 2002-08-08 | 2009-04-02 | 삼성테크윈 주식회사 | Method of manufacturing semiconductor package |
KR100762913B1 (en) * | 2006-11-21 | 2007-10-08 | 주식회사 하이닉스반도체 | Semiconductor package |
US7759807B2 (en) | 2006-11-21 | 2010-07-20 | Hynix Semiconductor Inc. | Semiconductor package having structure for warpage prevention |
CN109378308A (en) * | 2014-12-10 | 2019-02-22 | 上海兆芯集成电路有限公司 | Circuit substrate and packaging structure |
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