KR20070063582A - Reference circuit - Google Patents

Abstract

A reference circuit (200, 300) comprises a first current generator comprising a first transistor (Q1, 220) operably coupled to a second transistor (Q2, 222) and having respective base current (IbQ1, IbQ2) corresponding to a positive temperature dependence of the reference circuit. A resistance (r3 228) is operably coupled to the first current generator and arranged to provide a second current (Ir3) corresponding to a negative temperature dependence of the reference circuit. A second current generator (m4 224) is operably coupled to the resistance and the first current generator that generates a combined current (I2) as a sum of the second current (Ir3) and base current (IbQ1, IbQ2). In this manner, the output voltage of the curvature compensated voltage and/or current reference circuit is substantially linear and substantially independent of the operating temperature of the circuit.

Description

Reference circuit

The present invention relates to voltage and current reference circuits. The present invention is applicable to, but not limited to, a reference circuit and an apparatus for providing temperature-independent curvature-compensated sub-bandgap voltage and current references.

Voltage reference circuits are required in various electronic circuits to provide reliable voltage values. In particular, the circuits are designed to ensure that a reliable voltage value is formed substantially independent of any temperature changes in the electronic circuit or temperature change effects on components in the electronic circuit. In particular, the temperature stability of the voltage reference is a key factor. This is particularly important in some electronic circuits, for example technologies such as future communication products and system on chip technologies, where the accuracy of all data acquisition functions is required.

In the field of the present invention, the bandgap voltage reference is known to form an output voltage very close to the semiconductor bandgap voltage. Thus, it is understood that the sub bandgap voltage is less than 1.2V for silicon.

In general, there are two known basic components that are used to generate a bandgap voltage reference output. The first component of the electronic circuits is generally the base emitter voltage of a direct bias diode, for example a bipolar junction transistor (BJT) device with a negative temperature coefficient. The second component of the electronic circuits is the voltage difference of the direct bias diodes configured to provide an output proportional to the absolute temperature voltage. Thus, by adjusting the outputs of these components at an appropriate ratio, the sum of the outputs can provide a voltage reference that is almost independent of temperature. In particular, in current electronic circuits, the output voltage of the bandgap voltage reference under the above conditions is approximately 1.2V.

Undesirably, the base emitter voltage of a bipolar transistor does not change linearly with transistor temperature. Thus, it has been found that a simple band gap circuit that combines only two components in this manner has an output parabolic response and secondary temperature-dependency. Therefore, in order to increase the temperature stability of the voltage reference, a secondary compensation circuit is generally provided.

The temperature-dependency of the voltage reference can be seen in the temperature-dependence of the base emitter voltage of the forward bias bipolar transistor, as shown in equation [1].

Where Vgo is the bandgap voltage of the silicon extrapolated to the '0' Kelvin temperature,

VbeR is the base emitter voltage at temperature (Tr),

T is the operating temperature,

T _R is the reference temperature,

n is process dependent, but is a temperature independent parameter, and x is equal to 1 if the current is independent of temperature, if the bias current is PTAT and does not proceed to '0', i.e. the current flowing through the diode is Regardless, Vbe changes according to its temperature parameters. If the current flowing through the diode is temperature-dependent, Vbe changes according to itself and current temperature parameters. Thus, x = 1 if the bias current is linearly proportional to temperature and x = 0 if temperature-dependent.

k is the Boltzmann constant,

q is the electrical charge of the electron.

It is shown that the first term of [1] is constant, the second term is a linear function of temperature, and the last term is a nonlinear function. In the primary bandgap reference circuits, the linear (second) term from [1] is generally compensated for. In [1] the nonlinear terms are not compensated, thus forming the output parabola.

1 shows a schematic diagram 100 of a typical primary bandgap reference circuit, where the output voltage (Vref) 125 is assumed to have accurate primary temperature compensation. The circuit includes positive and negative temperature-dependent current generators based on Q1 120, Q2 122, m4 124, r1 126 and current mirrors 110, 112. The circuit further includes an output stage 130 based on resistors r2 and Q3 as diodes. Q1 120 forms a negative temperature-dependent current. The Vbe difference between Q1 120 and Q2 122 is provided to resistor r1 126. As a result, the Q2 emitter current is proportional to the delta Vbe divided by r1 126 and has a positive temperature-dependency.

Current mirrors m1 110, m2 112 and resistors Q1 120, Q2 122, and m4 124 form negative feedback to compensate for the collector current of Q1 12 and the drain current of m1 110. Current mirrors m2 112 and m3 114 form an m3 drain current proportional to the collector current of Q2 122. Transistor m4 124 and current mirrors m5 116 and m6 118 form an m6 drain current proportional to the base currents of Q1 120 and Q2 122. Both drain currents of m3 114 and m6 118 flow through the output stage, forming a voltage drop in diode Q3 with negative temperature-dependentness and resistor r2 with positive temperature-dependentness. If the temperature coefficients are the same, the output voltage 125 will be temperature compensated.

The correct primary temperature compensation is expressed as follows.

Where VrefBG is the bandgap reference output voltage.

Thus, the typical bandgap reference output voltage 125 is on the order of Vgo and approximately 1.2V with a few millivolts (mV) generated by the nonlinear term from [2].

However, a trend in high performance electrical equipment, especially portable communication equipment, is that a supply voltage of 1.5V or less needs to be used. Thus, in the context of the present invention with battery powered equipment such as an audio player or camera, 1.5V is the starting voltage for the battery voltage source, eg 'A' magnitude. If the battery is 'discharged' the voltage drops below 1V.

U. S. Patent No. 6,157, 245 describes a circuit that uses the generation of three currents with different temperature-dependencies and uses an accurate curvature compensation method. A major disadvantage of the circuit proposed in US Pat. No. 6,157,245 is the proposition of five 'critical matching' kohm resistors (22.35, 244.0, 319.08, 937.1, and 99.9). Large resistance ratios (1:42) and large diffusion ratios (1: 4.5 to 1:42) are a problem and excessive mismatching of resistors is expected.

In addition, the adjustment process for attempting to accurately and critically match the five resistors becomes too expensive for the circuit to be used in practice. Therefore, the circuit cannot be implemented in mass production devices.

Malcovati et al., Published in IEEE Jouranl of Solid-State Circuits. As well as a complex circuit comprising three critical matching bipolar transistor groups.

Accordingly, there is a need in the field of the present invention to subbandgap voltage references that can produce 1.2V portions with temperature stability that is particularly comparable to current subbandgap voltage references.

Accordingly, a preferred embodiment of the present invention is to reduce, alleviate or eliminate one or more of the disadvantages described above, preferably in one or any combination.

According to the invention, the reference circuit claimed in the appended claims is provided.

Exemplary embodiments of the invention are now described with reference to the accompanying drawings.

1 is a known schematic diagram of a typical primary bandgap voltage reference circuit.

2 is a schematic diagram of a primary subbandgap voltage reference circuit using inventive concepts in accordance with an embodiment of the present invention.

3 is a schematic diagram of a primary (precise curvature compensated) subbandgap voltage reference circuit utilizing the inventive concepts in accordance with an improved embodiment of the present invention.

4 is a typical diagram of a primary subbandgap voltage reference versus an accurate curvature compensated subbandgap voltage reference.

5 is a reference voltage distribution diagram using a circuit according to the present invention.

6 is a graph of reference voltage versus temperature for two different samples measured using a circuit in accordance with the present invention.

7 is a graph of adjusted reference voltage versus temperature for two different samples measured using a circuit according to the present invention.

A preferred embodiment of the present invention is described with reference to the design and operation improvement of the sub bandgap voltage reference circuit. However, it is within the intention of the present invention that the inventive concepts described herein are equally applicable to subbandgap current reference circuits.

In particular, in the prior art circuit of FIG. 1, the output voltage is limited by the voltage drop across diode Q3, which cannot be reduced below the value depending on diode size and flowing current (originally 0.6V-0.8V). However, a preferred embodiment of the present invention proposes a circuit which provides an output voltage proportional to the resistor r2 and the current values I1 and I2. In this way, it is possible to adjust to an output voltage of less than 0.6V by selecting appropriate values for r2, I1 and I2.

A preferred embodiment of the present invention consists of bipolar and CMOS transistor circuits arranged to obtain simple curvature compensation for subbandgap references. In particular, these subcircuits are combined in such a way that the reference output voltage is substantially linear and independent of operating temperature. It is contemplated that the concepts of the present invention described herein may be equally applicable to pure bipolar circuit arrangements, based substantially on the typical temperature dependence of bipolar diodes.

Preferred embodiments of the present invention propose respective subcircuits generating three currents. The first current is proportional to the absolute temperature. The second current is proportional to the base emitter voltage of the bipolar transistor. The third current is proportional to and non-temperature dependent of the nonlinear term of the base emitter voltage. In particular, the currents are provided at a temperature independent rate of sum in both the primary as well as the secondary mode. The sum of the three currents is arranged by the output resistor to provide a temperature-independent output voltage.

2 shows a simplified topology of the proposed subbandgap voltage reference circuit 200. The circuit shown in FIG. 2 includes an output stage having a PTAT current generator and Vbe / R current generators 220, 222, current mirrors 210-218, and a resistor r2 230 connected to ground. The PTAT current generator includes NPN transistors Q1 220 and Q2 222, resistor r1 226, NMOS transistor m4 224 and active current mirror circuits CM1 210, 212, and 214.

Resistor r3 228 forms a current proportional to Vb3 of Q1 220 divided by the value of resistor r3 228. As a result, drain current I2 of m4 224 is the sum of Q1 220, Q2 222, and the base of resistor r3 228. Currents I1 and I2 thus have positive and negative temperature-dependence. Both currents I1 and I2 flowing through resistor r2 230 produce a proportional output voltage 225 in the bandgap range.

The current mirror circuit CM1 causes the collector currents of the transistors Q1 and Q2 to be the same (generally, the collector currents of Q1 and Q2 can be related as M: K). The expression for PTAT current depends on the collector current, which depends on the base emitter voltage.

In particular, the circuit topology of FIG. 2 provides a number of new and improved features over the known circuit of FIG. 1.

(Iii) The reference voltage can be freely adjusted to any convenient value from zero (ground potential) to Vcc (supply voltage potential) by changing the value of the r2 resistor without affecting the temperature stability of the circuit.

(Ii) Simple temperature compensation current reference is easily obtained. Source current is available at the output terminals of the circuit if the r2 resistor is removed. Preferably, the sink current can be formed by the use of NPN or NMOS current mirrors.

(Iii) The sub bandgap voltage reference of FIG. 2 can be easily "upgraded" to the correct curvature compensation network as described below. Thus, the temperature stability of the circuit is substantially improved.

The exact curvature compensation description provided in the preferred embodiment of the present invention is provided below.

A typical primary bandgap output voltage is expressed as follows.

Where Ics is the saturation current of the collector,

'm' is a non-ideal element,

Vt is the thermal voltage, Vt = kT / q, and is expressed as follows (assuming Icqi = IcQ2 = I1).

Where I1 is the PTAT current,

N is the emitter region of Q2 and Q1.

In FIG. 2, the Vbe / R current generator includes NPN transistors Q1 220 and Q2 222 with a resistor r1 226, an NMOS transistor m4 224 and a current mirror circuit CM2 216, 218. Thus, the Vbe / R current generator produces the following output current.

Where I2 is the Vbe / R current,

VbeQ1 is the base emitter voltage of transistor Q1 220,

IbQ1 and IbQ2 are the base currents of Q1 220 and Q2 222, respectively.

Compared with the circuits of FIGS. 1 and 2, it can be seen that the transistor m4 124 of FIG. 1 is used only as a "beta helper" if it provides a base drive to Q1 120 and Q2 122. Can be. Preferably, however, the m4 transistor 224 in the FIG. 2 circuit provides additional functionality, namely Vbe / R current generation. Thus, transistor m4 224 of FIG. 2 performs two functions.

(Iii) produce negative temperature currents;

(Ii) provide Q1, Q2 base currents for simultaneous compensation for nonlinearity.

Thus, functional integration, i.e. the increased functionality of m4 in the preferred embodiment, is a key factor for creating new quality device performance without undue complexity of circuit design. In particular, in FIG. 2 the I1 and I2 currents are provided at a rate that is primarily temperature independent.

If (VbeQ1 / r3) >> (IbQ1 + IbQ2), the temperature-independent condition can be derived from the tie equations [1], [4] and [5] as shown in equation [6].

Where 'e' is the linearized temperature coefficient of the base emitter voltage,

VbeQ1R is the base emitter voltage of transistor Q1 at temperature T _R.

The sum of I1 and I2 currents flows through the output resistor r2 and forms a temperature-independent voltage drop (in the primary).

Here, VrefsBG is an output voltage of the sub bandgap reference.

Therefore, the output voltage of the proposed first subbandgap reference is VrefBG * r2 / r3 with similar parabolic curvature caused by nonlinear term from equation [7]. Typical temperature-independence of the output voltage of the primary subbandgap reference is shown in FIG. 4.

Referring now to FIG. 3, a simplified schematic diagram of an improved embodiment of the secondary compensation circuit of the present invention is shown. In summary, the circuit provided in FIG. 3 is similar to the circuit shown in FIG. 2 but has an additional compensation network. The additional network includes PMOS transistors m7 and m8 340, a diode connected bipolar transistor Q3 330 and a resistor r4 350. All these additional elements combine in the manner shown in FIG. 3 to achieve accurate curvature compensation, as described above.

From equation [1], the base emitter voltage of Q1 biased by PTAT current I1 of equation [4] can be provided as follows.

Here, 'x' is equal to '1' because the bias current is PTAT.

Diode connected bipolar transistor Q3 is biased by the sum of three currents I1, I2 and I3 in an improved embodiment. The sum of I1 and I2 is independent of the compensation in the first order (as shown in equations [4], [5] and [6]). As shown below, the I3 current increases the temperature-independence of the sum of the three currents I1, I2 and I3. Thus, the base emitter voltage of the Q3 transistor is provided as follows.

Here, 'x' is equal to '0' because the bias current is independent of temperature.

The difference between the base emitter voltages of Q1 and Q3 can be derived from equations [8] and [9].

Where VbeQ1R is the base emitter voltage of transistor Q1 at temperature T _R ,

VbeQ3R is the base emitter voltage of transistor Q3 at temperature T _R.

If the first term of equation [10] is equal to zero, the difference between the base emitter voltage between Q1 and Q3 is proportional only to the curvature voltage to be compensated for.

In order to equalize the VbeQ1R and VbeQ3R values, the emitter current densities of Q1 and Q3 at the reference temperature must be equivalent. The current flowing through Q1 is I1. The current flowing through Q3 is I1 + I2 (in the primary). However, I2 = I1 in T = T _R. Thus, the simplest way to equalize VbeQ1R and VbeQ3R is to use Q3 as two Q1 transistors connected in parallel as shown in FIG.

Therefore, it is as follows.

The voltage difference expressed in equation [11] is applied to the resistor r4 pins, forming a nonlinear current I3.

In FIG. 2, the sum of the nonlinear current I3 and the Vbe / R current I2 flows through both the m4 transistor and the output resistor r2 due to the current mirror circuit CM2. Thus, transistor m4 forms a new additional function as it gains some in generating nonlinear current.

Using equations [1], [4], [5], [6] and [12], the expression for the reference voltage can be derived as follows.

In particular, there are two nonlinear terms in equation [13]. According to a preferred embodiment of the present invention, accurate curvature compensation can be achieved when both nonlinear terms are removed in [13].

The expression of equation [14] describes an accurate and simple curvature compensation condition for the sub bandgap voltage reference shown in FIG. As noted above, 'n' is a temperature-independent processing parameter and typically has a value ranging from '3.6' to '4.0'.

Therefore, the expression for the reference voltage under the conditions defined in equation [14] is as follows.

Where Vref is the curvature compensated subbandgap reference output voltage.

Thus, it can be seen from equation [15] that the exact curvature compensation technique, as proposed in the present invention, substantially eliminates temperature-dependent and algebraic terms at the theoretical level. The reference voltage is determined by the resistor ratio and is preferably minimally affected by the actual value of the resistor.

4 to 7, experimental results are obtained from a circuit implementing the proposed correct curvature compensation method. The results are obtained from a circuit implemented in submicron BiCMOS technology (SmartMOS 5HV +). Preferably, the practical implementation of the proposed circuit does not require op amps or complex circuits for curvature compensation, and achieves a temperature coefficient of 2.9 ppm / k and a -76 dB power rejection rate. To achieve low temperature coefficients, 4 bit linear and 2 bit algebraic (nonlinear) adjustment circuits were used.

Referring to FIG. 4, a diagram 400 illustrates an accurate curvature compensated subbandgap voltage reference 420 using a first order subbandgap voltage reference 410 versus the inventive concepts in accordance with a preferred embodiment of the present invention. The reference voltage of is shown.

In FIG. 4, the diagram 400 of the accurate curvature compensation subbandgap voltage reference shows that the temperature stability of the curvature compensation voltage reference 420 exceeds the stability of the uncompensated 410 by a significant amount.

In particular, the unexpected curvature 410 has a non-parabolic characteristic that can be caused by thermal leakage currents (a person skilled in the art will recognize that this may be included in the model of the actual transistors). Thus, those skilled in the art will recognize that voltage or region mismatches or resistor mismatches or temperature coefficients in current mirrors or transistor emitter regions can cause other unexpected curvature errors.

Referring to FIG. 5, distribution chart 500 shows a count of reference voltages using a circuit using an accurate curvature compensation method in accordance with the present invention. The distribution diagram 500 of FIG. 5 shows 20 samples measured at room temperature during the default calibration state, where samples were taken from the same wafer. Indeed, distribution 500 operates the concepts of the present invention and shows that the sub bandgap reference voltage can be generated very accurately. The mean value and standard deviation of the reference distribution were evaluated.

Referring to FIG. 6, graph 600 shows experimental results for reference voltage vs. temperature before adjustment. The graph shows three adjustment options measured over the temperature range. The first graph includes four additional adjustment steps in the default value 610, the second graph includes the default value in the adjustment steps 620 and the third graph contains four adjustments less than the default value 630. Shows the steps.

In FIG. 6, it can be seen that the curvature is not completely compensated under the default nonlinear adjustment condition 620. Thus, the nonlinear adjustment process is preferably performed to achieve the minimum temperature coefficient of the reference voltage. After using an accurate adjustment method in accordance with the inventive concepts described above, the graphs show that for nonlinear and nonlinear components of the reference voltage, a minimum temperature coefficient is achieved.

Referring to FIG. 7, graphs 700 of reference voltage vs. temperature adjusted for two different measured samples are shown using a circuit in accordance with the present invention. These sets of samples 710, 720, 730 are shown and represent linear adjustment steps ('N + 1', 'N', and 'N-1') at the minimum temperature compensation (TC) points, respectively. . In Figure 7, it can be seen that the parabolic curvature of the reference voltage is completely removed.

Although the above description has been described with reference to positive metal oxide semiconductor (PMOS) transistor technology, those skilled in the art will appreciate that PMOS devices can be replaced by PNP bipolar transistor technology with suitable characteristics. Similarly, one skilled in the art will recognize that NPN bipolar transistors (or indeed HBT NPN transistors) can replace negative metal oxide semiconductor (NMOS) transistors in the above description.

Thus, in summary, known prior art reference circuits include the generation of a single current that is positively temperature-dependent and arranged to flow through an output stage. In contrast, preferred embodiments of the present invention provide two currents (in FIG. 2, one having positive temperature-dependentness and one negative temperature) to produce a temperature-independent (and preferably curvature compensated) output voltage. -Have a dependency) or three currents (with additional curvature compensation current).

It will be understood that the above-described reference circuit and operation are intended to provide one or more of the following advantages.

(Iii) The preferred circuit uses only three critically matched resistors related to the desired 1: 3: 10 ratio due to the specific functional integration achieved.

(Ii) The preferred circuit does not use op amps or other complex circuits to achieve simple curvature compensation.

(Iii) A preferred circuit for producing the sum of the second current and base currents IbQ1, IbQ2 of the first current generator provides the output voltage of the reference circuit substantially independent of the operating temperature of the circuit.

(Iii) The output voltage can be freely adjusted to any convenient value from ground potential to supply voltage potential without changing the temperature stability of the circuit.

(Iii) The provision of a curvature compensation network allows the output voltage of the reference circuit to compensate for nonlinearity at the output voltage and is substantially independent of the operating temperature of the circuit.

(Iii) The minimum supply voltage is not limited to output voltage values that may be less than 1.2V.

Although specific and preferred implementations of embodiments of the invention have been described above, it is clear that those skilled in the art can readily apply variations and modifications of the concepts of the invention.

In particular, it will be appreciated that the above description for simplicity has described embodiments of the present invention with reference to other functional units of the processing system. However, it will be apparent that any suitable distribution of functions between other functional units may be used without departing from the present invention. Thus, references to specific functional units are only shown as references to means suitable for providing the described functionality rather than indicative of precise logical or physical structure, construction or partitioning.

Claims (17)

A first current comprising first transistors Q1, 220 operatively coupled to second transistors Q2, 222 and having respective base currents IbQ1, IbQ2 corresponding to a positive temperature-dependency of the reference circuit. In the reference circuit (200, 300) comprising a generator, A resistor (r3 228) operably coupled to the first current generator and arranged to provide a second current (Ir3) corresponding to a negative temperature-dependency of the reference circuit; And A second current generator (m4 224) operably coupled to the first current generator that generates a combined current I2 as the resistance and the sum of the second current Ir3 and the base currents IbQ1 and IbQ2. Characterized in that, the reference circuit (200, 300). 2. The reference circuit of claim 1, wherein the reference circuits 200, 300 are further arranged to use curvature compensation, wherein the reference circuits 200, 300 are the sum of the base currents IbQ1, IbQ2 and the second current. A reference circuit 200, characterized in that it is input to a curvature compensation network Q3 330, r4 350 which generates a third current Ir4 proportional to the nonlinear term of the transmitter voltage to compensate for the nonlinearity of 225, 325. , 300). The sum of the base currents IbQ1 and IbQ2, the second current I2, and the third current Ir4 is input to an output resistor r2 to form a curvature compensation temperature-independent output voltage. Reference circuits (200, 300), characterized in that to switch currents so as to. 4. A reference circuit according to claim 2 or 3, characterized in that the sum of the base currents IbQ1, IbQ2, the second and third currents is independent of temperature in both the primary and secondary modes. (200, 300). 5. Reference circuit (200, 300) according to any of the preceding claims, characterized in that the reference circuit is a sub-bandgap reference circuit. 6. A current mirror circuit as claimed in any preceding claim, characterized by a current mirror circuit operably coupled to the first current generator and the second current generator and allowing the collector currents of the plurality of transistors to be arranged substantially identically. Reference circuits 200 and 300 are used. 7. The reference circuit (200, 300) according to any one of the preceding claims, wherein the current mirror circuit is a BJT or MOS current mirror. 8. The method of claim 1, wherein the temperature-independence

Characterized in that derived from, the reference circuit (200, 300). 9. The at least two PMOS transistors of claim 1, wherein the reference circuits 200, 300 are operably coupled to a diode connected bipolar transistor Q3 330 and a resistor r4 350. reference circuit (200, 300), characterized in that it is configured to provide a second compensation comprising an additional network with m7, m8). 10. The circuit of claim 9, wherein the second current mirror circuit has a third PMOS transistor, The gate terminal of the third PMOS transistor is connected to the drain and gate terminals of the second diode-connected PMOS transistor of the first current mirror, A source of the third PMOS transistor is connected to a supply voltage bus, And the drain of said third PMOS transistor is connected to an output node. 11. The reference circuit (200, 300) of claim 10, wherein the second current mirror circuit has a fourth PMOS transistor, and the drain and gate of the fourth PMOS transistor are connected to the drain of the first PMOS transistor. ). 12. The reference circuit (200, 300) of claim 11, wherein the second current mirror circuit has a fifth PMOS transistor having a gate connected to the drain and gate terminals of the fourth PMOS transistor. 13. The reference circuit (200, 300) of claim 12, wherein the sources of the fourth and fifth PMOS transistors are connected to a supply voltage bus. 14. The reference circuit (200, 300) of claim 12 or 13, wherein the drain of the fifth PMOS transistor is coupled with the drain of the third PMOS transistor at an output node. 15. The sixth and seventh aspect of claim 9 wherein the reference circuit generates a second temperature-dependent voltage and comprises a sixth PMOS transistor, a seventh PMOS transistor, and an NPN transistor. The gates of the PMOS transistors are connected to the drain and gate terminals of the second PMOS transistor and the fourth diode-connected PMOS transistor, respectively. 16. The reference circuit (200, 300) of claim 15, wherein the source of the sixth and seventh PMOS transistors is connected to the supply voltage bus. 17. The circuit of claim 16, wherein the drains of the sixth and seventh PMOS transistors are connected to the base and collector terminals of the NPN transistor with an emitter grounded. .

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