KR20070060944A - Flat panel display and driving method thereof - Google Patents

Abstract

A flat panel display device and a driving method thereof are provided to minimize power consumption by selectively driving a gray amplifier in response to input data. A flat panel display device includes a timing controller(150), a gradation unit(140), and a source driver(120). The timing controller receives N-bit input data(DIN[5:0]) and outputs 2^N control signals. The gradation unit outputs a gradation voltage in response to the control signals from the timing controller. The source driver drives a panel by the gradation voltage from the gradation unit in response to a horizontal synchronous signal and a data signal from the timing controller. The timing controller includes a decoder for decoding the input data, a first latch for outputting the input data in response to an output signal of the decoder, and a second latch for receiving an output signal from the first latch and outputting the control signal in response to the horizontal synchronous signal.

Description

Flat Panel Display and Driving Method {FLAT PANEL DISPLAY AND DRIVING METHOD THEREOF}

1 is a block diagram showing the configuration of a flat panel display device according to the prior art.

FIG. 2 is a waveform diagram illustrating a control signal of the flat panel display shown in FIG. 1.

3 is a block diagram showing a configuration of a flat panel display device according to an embodiment of the present invention.

4 is a detailed configuration diagram of the timing controller shown in FIG. 3.

FIG. 5 is a waveform diagram showing a control signal of the timing controller shown in FIG. 4; FIG.

FIG. 6 is a waveform diagram illustrating a control signal of the flat panel display shown in FIG. 3.

<Explanation of symbols for the main parts of the drawings>

10, 110: Panel

20, 120: source driver

30, 130: Gate driver

40, 140: gradation unit

50, 150: Timing Controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly to a flat panel, more particularly a thin film transistor (TFT) panel display and a driving method thereof.

Recently, as the number of portable digital devices such as mobile phones, portable multi-media players (PMPs), digital cameras, and the like has increased, power consumption of each device has become a very important issue. In addition, it is required to reduce power consumption even in a display device which is an information window of a portable digital device, such as a drive IC for driving a liquid crystal display (LCD).

1 is a block diagram showing the configuration of a TFT panel display device according to the prior art.

Referring to FIG. 1, a display device according to the related art may include a panel 10, source and gate drivers 20 and 30 for driving the panel 10, and a source driver 20. A gradation unit 40 for controlling the operation of the source driver 20 by supplying the gradation voltage and a timing controller 50 for controlling the operation of the gradation unit 40 are provided.

The timing controller 50 receives, for example, 6 bits (DIN [5: 0]) input data and sequentially calculates and processes the horizontal synchronization signal HSYNC, the input data signal, and the source driver control signal. 20) The vertical synchronizing signal VSYNC and the gate driver control signal are output to the gate driver 30. Further, a gray bit control signal of 1 bit is output to the gray scale unit 40.

The grayscale unit 40 operates 64 gray amplifiers (not shown) by the 1-bit control signal of the timing controller 50 to generate 64 grayscale voltages and output them to the source driver 20.

The source driver 20 receives the horizontal synchronization signal HSYNC and 64 data signals from the timing controller 50, and any one of 64 gray voltages output from the gray scale unit 40 in response to a 6-bit data signal. Select and output the data line to the data line of the panel 10.

The gate driver 30 receives the vertical synchronizing signal VSYNC and the gate driver control signal from the timing controller 50 and transfers the gray voltage transferred to the data line to the corresponding cell through the TFT.

The panel 10 includes a cell array in which cells are arranged at intersections of data lines and gate lines.

Operation characteristics of the display device according to the related art having such a configuration will be described with reference to FIG. 2.

Referring to FIG. 2, the gray scale 40 may receive a front porch and a back porch in the vertical sync signal VSYNC period in response to the gray amplifier control signal AMPcs output from the timing controller 50. The gray scale voltage is generated and output during the period except the porch). The source driver 20 uses the gray voltage transmitted from the gray scale unit 40 in response to the data signal and the source driver control signal during the horizontal synchronizing signal HSYNC period inputted from the timing controller 50, to control the panel 10. Transfer to the data line. The gate driver 30 transfers a gray voltage transferred to the data line to the gate line in response to the vertical synchronization signal VSYNC and the gate driver control signal output from the timing controller 50. As a result, the panel 10 is driven.

However, in the display device according to the related art, one-bit gray amplifier control input from the timing controller 50 during the section except the front porch and back porch sections within the vertical sync signal VSYNC period. Since all gray amplifiers constituting the grayscale unit 40 are operated by the signal AMPcs, power consumption is large.

In general, when all the image data displayed is white or black, one gray amplifier, for example, the first gray amplifier having a gray level having a first level or the first gray amplifier having a 64th level Only the 64th gray amplifier which outputs the gradation voltage needs to be operated. However, as described above, in the display device according to the related art, power consumption is large because all gray amplifiers constituting the gray scale unit 40 are operated.

Accordingly, an object of the present invention is to provide a panel display device and a driving method thereof capable of minimizing power consumption.

According to an aspect of the present invention, there is provided a panel, a timing controller for receiving input data of N bits (where N is an integer) and outputting 2 ^N control signals, and outputting from the timing controller. A gradation unit for outputting a gradation voltage in response to a control signal, and a source driver for driving the panel with the gradation voltage output from the gradation unit in response to a horizontal synchronization signal and a data signal output from the timing controller; Provides a flat panel display.

According to another aspect of the present invention, there is provided a panel, a timing controller for receiving input data of N bits (where N is an integer) and outputting a control signal, and in response to the control signal. Driving of a flat panel display device comprising a gradation unit for outputting a gradation voltage, and a source driver for driving the panel using the gradation voltage in response to a horizontal synchronizing signal input from the timing controller, the input data, and the control signal. The method may further include generating 2 ^N control signals by receiving the N bits of input data during the horizontal synchronization signal period, and independently operating the gray amplifier of the grayscale unit in response to the 2 ^N control signals. Generating the gray voltage, and driving the panel using the gray voltage. It provides a method of driving a flat panel display device also.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example

3 is a block diagram illustrating a configuration of a flat panel display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the flat panel display according to the exemplary embodiment of the present invention outputs 2 ^N gray amplifier control signals GAMPcs to independently control each gray amplifier (not shown) configured in the gray scale unit 140. Timing controller 150. Here, 'N' is an integer and indicates the number of bits of the input data DIN. For example, when the input data DIN is 6 bits, the gray amplifier control signals GAMPcs are 2 ⁶ , that is, 164. Each gray amplifier control signal GAMPcs independently drives each gray amplifier constituting the gray scale unit 140.

4 is a diagram illustrating the configuration of the timing controller 150 as an example.

Referring to FIG. 4, the timing controller 150 generates a decoder 151 for decoding and outputting the input data DIN, and outputs the input signal D in response to the output signal of the decoder 151. A first latch LATCH1 for outputting and a second latch LATCH2 for outputting the output signal of the first latch LATCH1 as a gray amplifier control signal GAMPcs in response to the horizontal synchronizing signal HSYNC. do. In addition, the first latch LATCH1 is reset by the delayed horizontal synchronization signal DHSYNC in which the horizontal synchronization signal HSYNC is delayed to a predetermined delay value, thereby resetting the output signal to '0' to thereby reset the second latch LTHCH2. Will output The waveform diagram of the delay horizontal synchronization signal DHSYNC is shown in FIG.

An operation characteristic of the timing controller 150 having such a configuration will be described below with reference to FIG. 6.

When the input data DIN is 6 bits ([5: 0]), the decoder 151 decodes the 6-bit input data DIN and outputs 64 output data DOUT1 to DOUT64, respectively. The first latch LATCH1 outputs the input signal D as an output signal in response to the output data DOUT1 to DOUT64 output from the decoder 151. At this time, since the input signal D is always at a high level '1', '1' is output. The second latch LATCH2 outputs the output signal of the first latch LATCH1 as a gray amplifier control signal GAMPcs in response to a low level '0' of the horizontal synchronization signal HSYNC. That is, 64 gray amplifier control signals GAMPcs1 to GAMPcs63 respectively corresponding to the output data DOUT1 to DOUT64 of the decoder 151 are output. On the other hand, the first latch LATCH1 is reset by the delay horizontal synchronizing signal DHSYNC to reset the output signal to a low level. The second latch LATCH2 maintains the previous control signals GAMPcs1 to GAMPcs64 until the horizontal synchronization signal HSYNC enters a low level.

In the above-described operation, the input data DIN is analyzed during one period of the horizontal synchronization signal HSYNC to generate 64 gray amplifier control signals GAMPcs and output them to the gray scale unit 140.

Operation characteristics of the display device of the present invention having such a configuration will be described with reference to FIG.

Referring to FIG. 6, the timing controller 150 analyzes N input data DIN inputted during one period of the horizontal synchronizing signal HSYNC and responds to the 2 ^N gray amplifier control signals in response to the input data DIN. Create and print GAMPcs). The gray scale 140 is a front porch and a back porch section within the vertical sync signal VSYNC period in response to the 2 ^N gray amplifier control signals AMPcs output from the timing controller 150. The grayscale voltage corresponding to the input data DIN is generated and output during the interval except for. The source driver 120 transmits to the data line of the panel 110 by using the gray voltage transmitted from the gray scale 140 in response to the data signal during the horizontal sync signal HSYNC period input from the timing controller 150. . The gate driver 130 transfers the gray voltage transferred to the data line to the gate line in response to the vertical sync signal VSYNC output from the timing controller 150. As a result, the panel 110 is driven.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, power consumption can be minimized by operating only the gray amplifier selectively selected in response to the input data, instead of simultaneously driving the plurality of gray amplifiers constituting the gradation unit all at once.

In addition, the present invention can reduce the power consumption than the gray amplifier operation control scheme using the vertical synchronization signal by controlling the operation of the gray amplifier constituting the gradation unit with the horizontal synchronization signal.

Claims (6)

panel; A timing controller that receives input data of N bits (where N is an integer) and outputs 2 ^N control signals; A gradation unit outputting a gradation voltage in response to a control signal output from the timing controller; And A source driver for driving the panel with the gray voltage output from the gray scale part in response to a horizontal sync signal and a data signal output from the timing controller Flat panel display comprising a. The method of claim 1, The timing controller, A decoder for decoding the input data; A first latch outputting an input signal in response to an output signal of the decoder; And A second latch receiving the output signal of the first latch and outputting the control signal in response to the horizontal synchronization signal Flat panel display comprising a. The method of claim 2, And the first latch is reset by a delay signal of the horizontal synchronization signal. The method of claim 2 or 3, And the second latch outputs the control signal in response to a falling edge of the horizontal synchronization signal. The method of claim 4, wherein The gradation portion a flat panel display device consisting of 2 ^N of gray amplifiers that operate independently in response to a control of the ^N 2 signal. A timing controller that receives a panel, input data of N bits (where N is an integer), and outputs a control signal, a gradation part that outputs a gradation voltage in response to the control signal, and a horizontal input from the timing controller A driving method of a flat panel display device comprising a source driver for driving the panel using the gray voltage in response to a synchronization signal. Generating 2 ^N control signals by receiving the N bits of input data during the horizontal synchronization signal period; Generating the gradation voltage by operating the gray amplifier of the gradation unit independently of each other in response to the 2 ^N control signals; And Driving the panel using the gray voltage; Driving method of a flat panel display device comprising a.

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