KR20070059731A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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KR20070059731A
KR20070059731A KR1020050118917A KR20050118917A KR20070059731A KR 20070059731 A KR20070059731 A KR 20070059731A KR 1020050118917 A KR1020050118917 A KR 1020050118917A KR 20050118917 A KR20050118917 A KR 20050118917A KR 20070059731 A KR20070059731 A KR 20070059731A
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film
layer
sacrificial layer
sacrificial
semiconductor device
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KR1020050118917A
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Korean (ko)
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서일석
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주식회사 하이닉스반도체
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Publication of KR20070059731A publication Critical patent/KR20070059731A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for fabricating a semiconductor device is provided to obtain optimum effect with little effort by preventing a tungsten layer from being influenced by a heat treatment. A gate pattern in which a gate insulation layer(32), a polysilicon layer(33) and a sacrificial layer are sequentially stacked is formed on a semiconductor substrate(31). The sacrificial layer can be made of photoresist. An interlayer dielectric is formed on the resultant structure. The interlayer dielectric is planarized by using a target having an exposed sacrificial layer. The sacrificial layer is removed to form a groove by an oxygen plasma strip process. A thick tungsten layer is formed which buries at least the groove from which the sacrificial layer is removed. A light oxide process is carried out.

Description

반도체 소자 제조 방법{METHOD FOR FORMING SEMICONDUCTOR DEVICE} Semiconductor device manufacturing method {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

도 1은 종래 기술의 문제점을 나타낸 TEM 사진,1 is a TEM photograph showing a problem of the prior art,

도 2a 내지 도 2h는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 도시한 단면도. 2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체 기판 32 : 게이트 절연막31 semiconductor substrate 32 gate insulating film

33 : 폴리실리콘막 34 : 희생막33: polysilicon film 34: sacrificial film

35 : 산화막 36 : 게이트 스페이서35 oxide film 36 gate spacer

37 : 층간절연막 38a : 텅스텐막37 interlayer insulating film 38a tungsten film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 텅스텐 산화에 자유로운 게이트 패턴을 갖는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of manufacturing a semiconductor device having a gate pattern free from tungsten oxidation.

디바이스가 고집적화 됨에 따라 도전층 패턴의 어려움도 있지만, 게이트 저항 문제도 발생한다. 그래서, 과거 폴리실리콘 만을 사용하던 시절에서 최근 폴리실리콘막과 텅스텐실리사이드를 적층으로 사용하고 있으며, 다음 세대에서는 폴리실리콘막과 텅스텐막을 적층으로 사용한다. 그런데, 텅스텐막을 사용하는 경우 여러가지 문제점이 발생한다. 그 문제점들 중에 하나가 텅스텐막의 산화이다.As devices become more integrated, there are challenges in conducting layer patterns, but also gate resistance problems. Therefore, in the past when only polysilicon was used, polysilicon film and tungsten silicide are recently used for lamination, and in the next generation, polysilicon film and tungsten film are used for lamination. By the way, when using a tungsten film, various problems arise. One of the problems is the oxidation of the tungsten film.

게이트 식각 후, 데미지 레이어(Damage layer)를 제거하기 위하여 라이트 산화(Light Oxidation)으로 처리하고 있으나, 텅스텐막을 도전층으로 사용할 경우, 일반적인 고온 분위기에서 라이트 산화를 진행하면, 텅스텐막의 산화가 발생하므로 선택적인 산화 방법을 고려하여 개발하고 있는 추세이다. After the gate is etched, it is treated by light oxidation to remove the damage layer.However, when the tungsten film is used as the conductive layer, the oxidation of the tungsten film occurs when the light oxidation is performed in a general high temperature atmosphere. Considering the oxidation method, the trend is being developed.

그러나, 이러한 방법도 텅스텐 산화에 자유로운 방법이 아니다. 후속 공정에서, 소스/드레인 영역을 형성하기 위하여 산화막/질화막 스페이서를 형성하고, 이온 주입을 진행한 후, 열공정을 진행할 경우, 텅스텐이 파티클(Particle)이나 크랙(Crack) 등으로 드러나는 경우, 여전히 텅스텐막의 산화가 발생한다.However, this method is also not free of tungsten oxidation. In the subsequent process, when the oxide / nitride spacers are formed to form the source / drain regions, the ion implantation proceeds, and the thermal process proceeds, when tungsten is exposed to particles or cracks, it is still Oxidation of the tungsten film occurs.

도 1은 종래 기술의 문제점을 나타낸 TEM 사진으로써, 도 1을 참조하면 텅스텐막의 이상 산화로 인한 텅스텐막 측면부가 과도 산화된 것을 알 수 있다.1 is a TEM photograph showing a problem of the prior art. Referring to FIG. 1, it can be seen that the side surface of the tungsten film is excessively oxidized due to abnormal oxidation of the tungsten film.

상술한 바와 같이, 게이트 패턴을 형성한 후 라이트 산화를 진행하면, 텅스텐막의 이상 산화로 인해 후속 공정인 자기정렬콘택 페일(Self Align Contact fail)과 같은 문제가 발생하여 소자의 수율의 저하와 동작 특성이 저하되는 문제가 발생한다.As described above, when the light oxidation is performed after the gate pattern is formed, problems such as self alignment contact fail, which are subsequent processes, may occur due to abnormal oxidation of the tungsten film, resulting in deterioration of device yield and operation characteristics. This deterioration problem occurs.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 라이트 산화시 텅스텐 산화를 방지하는데 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device suitable for preventing tungsten oxidation during light oxidation.

상기 목적을 달성하기 위한 특징적인 본 발명의 반도체 소자 제조 방법은 반도체 기판 상에 게이트 절연막, 폴리실리콘막 및 희생막이 차례로 적층된 게이트 패턴을 형성하는 단계, 상기 게이트 패턴을 포함하는 전면에 층간절연막을 형성하는 단계, 상기 희생막이 드러나는 타겟으로 상기 층간절연막을 평탄화하는 단계, 상기 희생막을 제거하여 홈을 형성하는 단계, 적어도 상기 희생막이 제거된 홈을 매립하는 두께의 텅스텐막을 형성하는 단계, 및 라이트 산화를 실시하는 단계를 포함한다.In another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a gate pattern in which a gate insulating film, a polysilicon film, and a sacrificial film are sequentially stacked on a semiconductor substrate, and forming an interlayer insulating film on the entire surface including the gate pattern. Forming a groove, forming a groove by removing the sacrificial film, forming a tungsten film having a thickness at least filling the groove from which the sacrificial film is removed, and light oxidation Performing the step.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2h는 본 발명의 실시예에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 소자분리 및 웰 형성 공정과 같은 소정 공정이 진행된 반도체 기판(31) 상에 게이트 절연막(32), 폴리실리콘막(33) 및 희생막(34)이 적층된 게이트 패턴을 형성한다. 폴리실리콘막(33)은 게이트 전도막이고, 희생막(34)은 포토레지스트를 사용한다.As shown in FIG. 2A, a gate pattern in which a gate insulating layer 32, a polysilicon layer 33, and a sacrificial layer 34 are stacked on a semiconductor substrate 31 on which a predetermined process such as device isolation and well formation is performed. To form. The polysilicon film 33 is a gate conductive film, and the sacrificial film 34 uses a photoresist.

도 2b에 도시된 바와 같이, 게이트 패턴에 대해 라이트 산화를 실시하여 반도체 기판(31) 및 게이트 패턴의 표면을 따라 산화막(35)을 형성한다.As shown in FIG. 2B, light oxidation is performed on the gate pattern to form the oxide film 35 along the surfaces of the semiconductor substrate 31 and the gate pattern.

도 2c에 도시된 바와 같이, 산화막(35) 상에 스페이서용 절연막을 증착하고, 건식 식각을 실시하여 게이트 패턴 측벽에 부착된 게이트 스페이서(36)를 형성한다. 게이트 스페이서(36)는 산화막, 질화막 또는 이들의 적층된 구조(예컨대, O-N-O 구조)를 사용한다.As shown in FIG. 2C, an insulating film for a spacer is deposited on the oxide layer 35, and dry etching is performed to form a gate spacer 36 attached to the sidewall of the gate pattern. The gate spacer 36 uses an oxide film, a nitride film, or a stacked structure thereof (eg, an O-N-O structure).

도 2d에 도시된 바와 같이, 게이트 패턴을 포함하는 반도체 기판(31)의 전면에 층간절연막(37)을 증착한다. 이 때, 층간절연막(37)은 BSG(Boro-Silicate-Glass)막, BPSG(Boro-Phospho-Silicate-Glass)막, PSG(Phospho-Silicate-Glass)막, TEOS(Tetra-Ethyl-Ortho-Silicate)막, HDP(High Density Plasma) 산화막, SOG(Spin On Glass)막 또는 APL(Advanced Planarization Layer)막 등을 이용하며, 산화막 계열 이외에 무기 또는 유기 계열의 저유전율막을 이용할 수 있다. As shown in FIG. 2D, an interlayer insulating film 37 is deposited on the entire surface of the semiconductor substrate 31 including the gate pattern. At this time, the interlayer insulating film 37 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho-Silicate) film. ) Film, HDP (High Density Plasma) oxide film, SOG (Spin On Glass) film or APL (Advanced Planarization Layer) film, and the like, in addition to the oxide film-based low dielectric constant film may be used.

도 2e에 도시된 바와 같이, 화학적·기계적 연마(Chemical Mechanical Polishing; CMP) 또는 에치 백(Etch Back)을 실시하여 희생막(34)이 드러나는 타겟으로 층간절연막(37)을 평탄화한다. 층간절연막(37)의 평탄화는 전면 식각(Etch Back) 또는 화학적·기계적 연마(Chemical Mechanical Polishing; CMP)를 사용한다. 이하, 층간절연막(37)은 층간절연막(37a)로 약칭한다. As illustrated in FIG. 2E, chemical insulating polishing (CMP) or etching back is performed to planarize the interlayer insulating layer 37 to a target on which the sacrificial layer 34 is exposed. The planarization of the interlayer insulating film 37 uses etching back or chemical mechanical polishing (CMP). Hereinafter, the interlayer insulating film 37 is abbreviated as an interlayer insulating film 37a.

도 2f에 도시된 바와 같이, 희생막(34)을 제거하여 폴리실리콘막(33)의 상부를 오픈하는 홈(H)을 형성한다. 이때, 희생막(34)은 산소 플라즈마 스트립 공정으로 제거한다.As shown in FIG. 2F, the sacrificial layer 34 is removed to form a groove H that opens the upper portion of the polysilicon layer 33. At this time, the sacrificial layer 34 is removed by an oxygen plasma strip process.

도 2g에 도시된 바와 같이, 폴리실리콘막(33) 상부에 적어도 희생막이 제거되어 형성된 홈을 매립하는 두께의 텅스텐막(38)을 증착한다.As shown in FIG. 2G, a tungsten film 38 having a thickness filling a groove formed by removing at least a sacrificial film is deposited on the polysilicon film 33.

도 2h에 도시된 바와 같이, 화학적·기계적 연마 또는 전면 식각을 실시하여 층간절연막(37a)의 표면이 드러나는 타겟으로 텅스텐막(38)을 평탄화 식각한다. As shown in FIG. 2H, the tungsten film 38 is planarized and etched with a target on which the surface of the interlayer insulating film 37a is exposed by performing chemical and mechanical polishing or full surface etching.

따라서, 게이트 절연막(32) 상에 폴리실리콘막(33) 및 텅스텐막(38a)이 차례로 적층된 게이트 패턴을 형성할 수 있다. Therefore, the gate pattern in which the polysilicon film 33 and the tungsten film 38a are sequentially stacked on the gate insulating film 32 can be formed.

상술한 바와 같이, 희생막을 갖는 게이트 패턴을 형성하고, 그 희생막을 제거한 후, 제거한 영역에 게이트용 도전층을 매립하는 형태로 게이트 패턴을 형성하므로써, 라이트 산화 의한 텅스텐막의 이상 산화를 미리 방지하여 종래 문제가 되었던 SAC 페일과 같은 문제를 방지할 수 있다. 즉, 라이트 산화를 먼저 실시한 후 텅스텐막을 증착함으로써, 라이트 산화에 의한 텅스텐막의 이상 산화를 완전히 방지할 수 있다.As described above, by forming a gate pattern having a sacrificial film, removing the sacrificial film, and forming a gate pattern in a form in which the gate conductive layer is embedded in the removed region, abnormal oxidation of the tungsten film by light oxidation is prevented in advance. This can prevent problems such as SAC failing, which became a problem. That is, by performing light oxidation first and depositing a tungsten film, abnormal oxidation of the tungsten film by light oxidation can be completely prevented.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 텅스텐막이 열공정으로부터 자유로워 텅스텐막 산화가 발생하지 않는다는 점에서, 크리티컬한 공정이 아니므로 적은 노력으로 최적의 효과를 얻을 수 있다.The present invention described above is not a critical process in that the tungsten film is free from the thermal process so that tungsten film oxidation does not occur. Therefore, the optimum effect can be obtained with little effort.

또한, 텅스텐막의 이상 산화에 의한 소자 특성 저하를 완전히 막을 수 있으므로, 소자의 수율을 향상시키고, 관리 유지에 유용하다.In addition, since the deterioration of the device characteristics due to abnormal oxidation of the tungsten film can be completely prevented, it is useful for improving the yield of the device and maintaining it.

Claims (5)

반도체 기판 상에 게이트 절연막, 폴리실리콘막 및 희생막이 차례로 적층된 게이트 패턴을 형성하는 단계;Forming a gate pattern in which a gate insulating film, a polysilicon film, and a sacrificial film are sequentially stacked on the semiconductor substrate; 상기 게이트 패턴을 포함하는 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire surface including the gate pattern; 상기 희생막이 드러나는 타겟으로 상기 층간절연막을 평탄화하는 단계;Planarizing the interlayer dielectric layer with a target on which the sacrificial layer is exposed; 상기 희생막을 제거하여 홈을 형성하는 단계; Removing the sacrificial layer to form a groove; 적어도 상기 희생막이 제거된 홈을 매립하는 두께의 텅스텐막을 형성하는 단계; 및Forming a tungsten film having a thickness at least filling the groove from which the sacrificial film has been removed; And 라이트 산화를 실시하는 단계Performing light oxidation 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 희생막은 포토레지스트로 형성하는 반도체 소자 제조 방법.The sacrificial film is a semiconductor device manufacturing method of forming a photoresist. 제2항에 있어서,The method of claim 2, 상기 희생막은 산소 플라즈마 스트립으로 제거하는 반도체 소자 제조 방법.And removing the sacrificial layer with an oxygen plasma strip. 제1항에 있어서,The method of claim 1, 상기 텅스텐막을 형성하는 단계는,Forming the tungsten film, 상기 적어도 상기 희생막이 제거된 홈을 매립하는 단계;Filling the grooves from which the at least the sacrificial layer has been removed; 상기 층간절연막의 표면이 드러나는 타겟으로 화학적·기계적 연마 또는 전면 식각을 실시하는 단계를 포함하는 반도체 소자 제조 방법.And chemically or mechanically polishing or etching the entire surface with the target on which the surface of the interlayer insulating layer is exposed. 제1항에 있어서,The method of claim 1, 상기 게이트 패턴은 양측벽에 스페이서를 부착한 반도체 소자 제조 방법.The gate pattern is a semiconductor device manufacturing method having a spacer on both side walls.
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