KR20070056675A - Method for manufacturing thin film transistor array panel - Google Patents

Abstract

A method for manufacturing a thin film transistor substrate is provided to prevent the leakage current caused by partially exposing a semiconductor layer when a conductive layer positioned on a channel region of the semiconductor layer is removed, by reflowing a photoresist pattern to cover a data line on the semiconductor layer in order not to expose the semiconductor layer. A gate line is formed on a substrate(110). A gate insulating layer(140), an impurity-undoped amorphous silicon layer, an impurity-doped amorphous silicon layer, and a conductive layer are sequentially deposited over the gate line. A photoresist pattern is formed on the conductive layer, wherein the photoresist pattern has a first part and a second part thicker than the first part. The conductive layer is etched by using the photoresist pattern as a mask to form a conductive pattern. In succession, the impurity-doped amorphous silicon layer and the impurity-undoped amorphous silicon layer are etched by using the photoresist pattern as a mask to form an ohmic contact pattern and a semiconductor pattern. The first part of the photoresist pattern is removed. The second part of the photoresist pattern is reflowed. The conductive pattern is etched by using the reflowed photoresist pattern to form a data line(171) and a drain electrode(175). The ohmic contact pattern is etched by using the reflowed photoresist pattern to form ohmic contact layers. The reflowed photoresist pattern is removed. A passivation layer covers the data line and the drain electrode, wherein the passivation layer has a contact hole exposing the drain electrode. A pixel electrode is formed on the passivation layer, wherein the pixel electrode is connected to the drain electrode through the contact hole.

Description

Method of manufacturing thin film transistor array panel {METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2 and 3 are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines II-II and III-III, respectively.

4, 15, and 18 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 and 6 are cross-sectional views illustrating the thin film transistor array panel of FIG. 4 taken along lines V-V and VI-VI.

7 to 14 are cross-sectional views sequentially shown according to a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention.

16 and 17 are cross-sectional views of the thin film transistor array panel of FIG. 15 taken along lines XVI-XVI and XVII-XVII.

19 and 20 are cross-sectional views of the thin film transistor array panel of FIG. 18 taken along lines XIX-XIX and XX-XX.

<Description of Major Codes in Drawings>

52, 54: photosensitive film pattern 83: connecting bridge

110: insulated substrate

121: gate line 124: gate electrode

131: sustain electrode lines 133a and 133b: sustain electrode

140: gate insulating film 150: intrinsic amorphous silicon layer

151 and 154: semiconductor 160: impurity amorphous silicon layer

161, 163, and 165: ohmic contact members

171: data line 173: source electrode

175: drain electrode 180: protective film

191: pixel electrode 81, 82: contact auxiliary member

The present invention relates to a method of manufacturing a thin film transistor array panel.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween to apply voltage to the electrodes. The display device controls the amount of light transmitted by rearranging the liquid crystal molecules of the liquid crystal layer.

Among the liquid crystal display devices, which are currently mainly used are structures in which electric field generating electrodes are provided on two display panels, respectively. Among these, a plurality of pixel electrodes are arranged in a matrix form on one display panel (hereinafter referred to as a 'thin film transistor display panel'), and one common electrode is used on another display panel (hereinafter, referred to as a 'common electrode display panel'). The shape of the structure covering the front is mainstream. The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching the voltage applied to the pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a voltage to be applied to the pixel electrode are selected. A data line to transfer is formed on the display panel.

The thin film transistor serves as a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element that individually controls each light emitting element in an active organic light emitting diode (AM-OLED) that is a self-luminous element.

The thin film transistor array panel includes a plurality of thin films including a metal layer including a gate line and a data line, a semiconductor, and an insulating layer, and each thin film is patterned using a separate mask.

However, as one more mask is added, the process time and cost are remarkably increased since the photoresist coating, exposure, development and cleaning processes must be repeated. Therefore, it is necessary to reduce the number of possible masks.

Accordingly, a method of etching the data metal film and the semiconductor with one mask has been proposed.

However, when the data metal film and the semiconductor are etched with one mask, the semiconductor remains on the entire lower surface of the data metal film. In addition, when the channel portion is etched, the width of the semiconductor and the semiconductor under the data line may be changed to expose the lower semiconductor. In this case, when the semiconductor is exposed to a light source such as a backlight, a light leakage current is generated, which may deteriorate the characteristics of the thin film transistor array panel and may be visually recognized as an afterimage from the outside.

Accordingly, an object of the present invention is to provide a thin film transistor array panel in which the generation of light leakage current is reduced and no afterimage occurs.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including: forming a gate line on a substrate, a gate insulating layer on the gate line, an amorphous silicon layer not doped with impurities, and an amorphous silicon layer doped with impurities And laminating a conductive layer, forming a photoresist pattern including a first portion and a second portion thicker than the first portion on the conductive layer, and etching the conductor using the photoresist pattern as a mask to form a conductor pattern. Forming a resistive contact pattern and a semiconductor by etching the amorphous silicon layer doped with impurities and the amorphous silicon layer not doped with impurities, removing the first portion of the photoresist pattern, and the second photoresist pattern Reflowing the portion, the conductor pattern is etched using the first reflowed photoresist pattern as a mask to form a data line and Forming a lane electrode, etching the resistive contact pattern using the first reflowed photoresist pattern as a mask to form a resistive contact member, removing the photoresist pattern, covering the data line and the drain electrode, and exposing the drain electrode Forming a passivation layer including a contact hole, and forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer.

The data layer may comprise copper or copper alloys, aluminum or aluminum alloys, silver or silver alloys.

Reflowing the photoresist pattern may be performed at 130 to 150 ° C.

The photoresist pattern is an alkali-soluble resin and a ballast structure of formula (I).

Where R ₁ and R ₂ are alkyl groups, and R ₁ and R ₂ may be the same or different from each other.

The photosensitive compound may be a diazide compound.

The photoresist pattern may further include a heat resistance control additive.

The heat resistance controlling additive is the first compound of formula (II)

Wherein R is a methyl group, an ethyl group, a propyl group, and a second compound of formula (III)

Wherein R ₁ is a methyl group, an ethyl group, a propyl group, a butyl group, a pentyl group, a hexyl group, and R ₂ is hydrogen (H) or a methyl group.

The heat resistance controlling additive may have an average molecular weight of 200 to 400.

The photoresist pattern may include 5 to 30% by weight of alkali-soluble resin, 2 to 10% by weight of the photosensitive compound, 0.5 to 3% by weight of heat resistance control additive, and the remaining amount of solvent.

Alkali-soluble resins may be novolac resins containing meta (m) -cresol and para (p) -cresol and having an average molecular weight of 2,000 to 5,000.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views illustrating the thin film transistor array panel of FIG. 1 taken along lines II-II and III-III, respectively.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding downward and an end portion 129 having a large area for connection with another layer or an external driving circuit. A gate driving circuit (not shown) for generating a gate signal may be mounted on a flexible printed circuit film (not shown) attached to the substrate 110 or directly mounted on the substrate 110, It may be integrated into the substrate 110. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The storage electrode line 131 receives a predetermined voltage, and includes a stem line extending substantially in parallel with the gate line 121 and a plurality of pairs of storage electrodes 133a and 133b separated therefrom. Each of the storage electrode lines 131 is positioned between two adjacent gate lines 121, and the stem line is closer to the lower side of the two gate lines 121.

Each of the sustain electrodes 133a and 133b has a fixed end connected to the stem line and a free end opposite thereto. The fixed end of one sustain electrode 133a has a large area, and its free end is divided into two parts, a straight part and a bent part. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The gate line 121 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, or copper-based metal such as copper (Cu) or copper alloy. It can be made of a resistive conductor.

However, they may have a multilayer structure including two conductive films (not shown) having different physical properties. One of the conductive films is made of a metal having low resistivity, such as aluminum-based metal, silver-based metal, or copper-based metal, so as to reduce signal delay or voltage drop.

In contrast, other conductive films are made of other materials, particularly materials having excellent physical, chemical, and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, tantalum, and titanium. Examples of such a combination include a molybdenum bottom film, a copper (alloy) top film, and an aluminum (alloy) bottom film and a molybdenum (alloy) top film. However, the gate line 121 and the storage electrode line 131 may be made of various other metals or conductors.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 mainly extends in the longitudinal direction and includes a plurality of projections 154 extending toward the gate electrode 124. The linear semiconductor 151 has a wider width in the vicinity of the gate line 121 and the storage electrode line 131 and covers them widely.

A plurality of linear and island ohmic contacts 161 and 165 are formed on the semiconductor 151. The ohmic contacts 161 and 165 may be made of a material such as n + hydrogenated amorphous silicon in which n-type impurities such as phosphorus (P) are heavily doped, or may be made of silicide. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and disposed on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is about 30 ° to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 transmits a data signal and mainly extends in the vertical direction to cross the gate line 121. Each data line 171 also crosses the storage electrode line 131 and is formed between a set of adjacent storage electrodes 133a and 133b. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and an end portion 179 having a large area for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with respect to the gate electrode 124. Each drain electrode 175 has one end portion having a large area and the other end portion having a rod shape. The wide end portion overlaps the storage electrode line 131, and the rod-shaped end portion is partially surrounded by the bent small electrode 173.

One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor 151 form one thin film transistor (TFT). A channel of the transistor is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 have a triple layer structure including a lower layer 171p and 175p, an intermediate layer 171q and 175q, and an upper layer 171r and 175r. The lower films 171p and 175p are made of refractory metals or alloys thereof such as molybdenum, chromium, tantalum and titanium, and the intermediate films 171q and 175q are made of aluminum-based metals having low resistivity, silver-based metals and copper. The upper layers 171r and 175r are made of a refractory metal or an alloy thereof having excellent contact properties with ITO or IZO. Examples of such a triple film structure include a molybdenum (alloy) lower film, an aluminum (alloy) interlayer, and a molybdenum (alloy) upper film.

The data line 171 and the drain electrode may have a double layer structure including a refractory metal lower layer (not shown) and a low resistance upper layer (not shown) or a single layer structure made of the aforementioned materials. . Examples of the double film structure include a chromium or molybdenum (alloy) bottom film and an aluminum (alloy) top film. However, the data line 171 and the drain electrode 175 may be made of various metals or conductors.

2 and 3, for the data line 171 and the drain electrode 175 including the source electrode 173 and the end portion 179, the lower layer has the alphabet letter P, the middle layer has the alphabet letter q, and the upper layer has the alphabet letter r. In addition to the reference numerals.

The side of the data line 171 and the drain electrode 175 may also be inclined at an inclination angle of about 30 ° to about 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 thereon, and lower the contact resistance therebetween.

The semiconductor 151 has a planar shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. That is, the linear semiconductor 151 is formed under both the data line 171 and the drain electrode 175 and the ohmic contact layers 161, 163, and 165 thereunder, and the source electrode 173 and the drain electrode ( 175).

A passivation layer 180 is formed on the data line 171, the drain electrode 175, and the exposed semiconductor 154.

The passivation layer 180 is made of an inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or a low dielectric insulator. The dielectric constant of the organic insulator and the low dielectric insulator is preferably 4.0 or less. Examples of the low dielectric insulator include a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). : F, etc. can be mentioned. The passivation layer 180 may be formed by having photosensitivity among the organic insulators, and the surface of the passivation layer 180 may be flat. However, the passivation layer 180 may have a double layer structure of the lower inorganic layer and the upper organic layer so as not to damage the exposed portion of the semiconductor 151 while maintaining excellent insulating properties of the organic layer.

In the passivation layer 180, a plurality of contact holes 182 and 185 exposing the end portion 179 and the drain electrode 175 of the data line 171 are formed, respectively, and the passivation layer 180 and the gate insulating layer are formed. The plurality of contact holes 181 exposing the end portion 129 of the gate line 121 and a plurality of exposing portions of the sustain electrode line 131 near the fixed end of the sustain electrodes 133a and 133b or the free end are formed in the 140. Contact holes 183a and 183b are formed.

A plurality of pixel electrodes 191, a plurality of overpasses 83, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. These may be made of a transparent conductive material such as ITO or IZO or a reflective metal such as aluminum, silver or an alloy thereof.

The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives a data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied has a liquid crystal between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. The direction of the liquid crystal molecules in the layer (not shown) is determined. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 including the storage electrodes 133a and 133b. A capacitor formed by the pixel electrode 191 and the drain electrode 171 electrically connected to the pixel electrode 191 overlapping the storage electrode line 131 is called a storage capacitor, and the storage capacitor enhances the voltage holding capability of the liquid crystal capacitor.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

The connecting leg 83 crosses the gate line 121, and exposes the exposed portion of the storage electrode line 131 through a pair of contact holes 183a and 183b positioned opposite to each other with the gate line 121 interposed therebetween. The sustain electrode 133b is connected to the exposed end of the free end. The sustain electrode lines 131 including the sustain electrodes 133a and 133b may be used to repair defects in the gate line 121, the data line 171, or the thin film transistor together with the connecting leg 83.

Next, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 20.

4, 15, and 18 are layout views sequentially illustrating a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 5 and 6 illustrate the thin film transistor array panel of FIG. 4 as a VV line and a VI-VI line. 7 to 114 are cross-sectional views sequentially shown according to a method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 16 and 17 are XVI of the thin film transistor array panel of FIG. 15. 19 is a cross-sectional view taken along the -XVI line and the XVII-XVII line, and FIGS. 19 and 20 are cross-sectional views of the thin film transistor array panel of FIG. 18 taken along the XIX-XIX line and the XX-XX line.

First, as shown in FIGS. 4 to 6, a conductive layer made of copper is formed on an insulating substrate 110 made of transparent glass or plastic, and then wet etching to wet the gate electrode 124 and the end portion. A plurality of gate lines 121 including 129 and a plurality of storage electrode lines 131 including sustain electrodes 133a and 133b are formed.

Subsequently, as shown in FIGS. 7 and 8, the gate insulating layer 140 made of silicon nitride (SiNx) on the gate line 121 and the storage electrode line 131, and the intrinsic amorphous silicon (a-) doped with impurities are not doped. The Si) layer 150 and the doped amorphous silicon (n + a-Si) layer 160 are formed by a plasma enhanced chemical vapor deposition (PECVD) method. The intrinsic amorphous silicon layer 150 is formed of hydrogenated amorphous silicon, and the like, and the doped amorphous silicon layer 160 is made of amorphous silicon or silicide doped with a high concentration of n-type impurities such as phosphorus (P). Form.

Subsequently, molybdenum (Mo), aluminum (Al), and molybdenum (Mo) are stacked on the amorphous silicon layer 160 doped with impurities to form a data conductive layer 170 including triple layers 170p, 170q, and 170r. do.

Next, a photosensitive film is coated on the data conductive layer 170.

The photoresist film is made of a photosensitive composition having low heat resistance and excellent reflow characteristics. Such a photosensitive composition is demonstrated illustratively.

The photosensitive composition which can be applied to this embodiment includes an alkali-soluble resin and a photosensitive compound having a ballast structure.

As an alkali-soluble resin, a novolak resin is typically mentioned.

Novolak resins are generally polymer polymers obtained by reacting a phenol monomer and an aldehyde compound in the presence of an acid catalyst.

Here, as the phenol monomer, meta (m) -cresol and para (p) -cresol may be synthesized in a specific ratio, and as the aldehyde compound, formaldehyde, p-formaldehyde, benzaldehyde, nitrobenzaldehyde, acetaldehyde 1 type, or 2 or more types selected from etc. can be mixed and used. In addition, an acidic catalyst added during the reaction of the phenol monomer with the aldehyde compound may be selected from, for example, hydrochloric acid, nitric acid, sulfuric acid, formic acid or oxalic acid.

The average molecular weight of the novolak resin suitable for application in this example is about 2,000 to 5,000. When the average molecular weight is less than 2,000, the sensitivity is low, making it difficult to form a fine pattern. When the average molecular weight is more than 5,000, the reflow characteristic of the photosensitive film may be lowered and the adhesion with other films may be weakened.

The alkali-soluble resin is preferably contained in 5 to 30% by weight relative to the total content of the photosensitive composition.

The photosensitive compound is a compound that reacts to light upon exposure to cause a photochemical reaction.

In this embodiment, as a photosensitive compound that can increase the fluidity of the photosensitive film together with the photochemical reaction, a ballast structure of formula (I)

(Wherein R ₁ and R ₂ are alkyl groups and R ₁ and R ₂ may be the same or different)

Use a compound having a.

The ballast structure can impart flexibility to the compound and increase the fluidity of the photosensitive composition because alkyl groups are connected between a plurality of benzene rings as shown in the structural formula.

In addition, a diazide compound such as, for example, quinone diazide may be bonded to the hydroxy group (-OH) of the ballast structure to exhibit photosensitive characteristics.

Examples of the compound in which the diazide compound is bonded to the ballast structure include 2,2'-methylenebis [6-[(2-hydroxy-5-methylphenyl) methyl] -4-methyl-1,2-naphthoquinone Diazide-5-sulfonate (2,2'-methylene bis [6-[(2-hydroxy-5-methyl phenyl) methyl] -4-methyl-1,2-naphtoquinonediazide-5-sulfonate) .

The photosensitive compound may be contained in an amount of 2 to 10% by weight based on the total content of the photosensitive composition. When the photosensitive compound is contained in less than 2% by weight, the rate of exposure decreases during exposure, and when it exceeds 10% by weight, the rate of increase rapidly increases and does not form a good profile.

In addition, the present invention may include a heat resistance control additive to reduce the heat resistance of the photosensitive film.

The heat resistance controlling additive is a compound added to reduce the heat resistance of the photosensitive composition so that it can be reflowed at a temperature lower than the original reflow temperature.

As the heat resistance regulating additive, a first bisphenol-based compound represented by the formula (II)

(Where R is a methyl group, an ethyl group, or a propyl group)

Or a second bisphenol compound represented by the formula (III)

(Wherein R ₁ is a methyl group, ethyl group, propyl group, butyl group, pentyl group, hexyl group, and R ₂ is hydrogen (H) or methyl group)

Can be mentioned.

The heat resistance regulating additive may be contained in 0.5 to 3% by weight based on the total content of the photosensitive composition.

In addition to the above components, the photosensitive composition may further include other additives, such as plasticizers, stabilizers or surfactants, as necessary.

Alkali-soluble resins, photosensitive compounds and various additives are used in the form of solutions dissolved in organic solvents. Examples of the organic solvent include ethyl acetate, butyl acetate, diethylene glycol dimethyl ether, diethylene glycol dimethyl ethyl ether, and methyl methoxy propionic acid. (methyl methoxy propionate), ethyl ethoxy propionate, ethyl lactate, propylene glycol methyl ether acetate, propylene glycol methyl ether, propylene Propylene glycol propyl ether, methyl cellosolve acetate, ethyl cellosolve acetate, diethylene glycol methyl acetate, diethylene glycol ethyl acetate diethylene glycol ethyl acetate, acetone, methyl isobutyl ketone, Cyclohexanone, dimethyl formamide, N, N-dimethyl acetamide, N-methyl-2-pyrolidone, γ-butyrolactone, diethyl ether, ethylene glycol dimethyl ether, diglyme, tetrahydrofurane, methanol, methanol ethanol, propanol, isopropanol, methyl cellosolve, ethyl cellosolve, diethylene glycol methyl ether, diethylene glycol ethyl ether It may be selected from glycol ethyl ether, dipropylene glycol methyl ether, toluene, toluene, xylene, hexane, heptane, octane, and the like.

The solvent is contained in the remaining amount excluding the alkali-soluble resin, the photosensitive compound, and various additives based on the total content of the photosensitive composition, preferably 60 to 90% by weight.

Subsequently, the photosensitive film made of the photosensitive composition is exposed and developed to form a first photoresist pattern 52 and a second photoresist pattern 54 that is thinner than the first photoresist pattern 52.

At this time, after the photosensitive film is developed, a separate heat treatment (post bake) is not performed. In general, the heat treatment in this step is performed to firmly fix the photosensitive film patterned by the developer onto the substrate. However, when heat-treating the photoresist film having low heat resistance as described above, reflow of the photoresist film is caused to destroy the profile of the initially formed photosensitive pattern. In this case, the profile and the inclination angle of the photoresist formed in the channel region may be changed, resulting in poor subsequent etching, and in some cases, may affect the thin film transistor characteristics such as a short.

Accordingly, after the photoresist is developed, an etching step is performed immediately without performing a separate heat treatment.

For convenience of description, the data layer 170 of the portion where the wiring is to be formed, the amorphous silicon layer 160 doped with impurities, the intrinsic amorphous silicon layer 150 are referred to as the wiring portion A, and the gate electrode 124 The portion where the channel is formed above is called a channel portion B, and the region excluding the wiring portion A and the channel portion B is called the remaining portion C.

Among the photoresist patterns 52 and 54, the first photoresist pattern 52 positioned in the wiring portion A is formed thicker than the second photoresist pattern 54 positioned in the channel portion B, and the photoresist of the remaining portion C is Remove everything. In this case, the ratio of the thickness of the first photoresist pattern 52 to the thickness of the second photoresist pattern 54 should be different depending on the process conditions in the etching process, which will be described later. It is preferable to set it as 1/2 or less of the thickness of the 1st photosensitive film pattern 52.

As described above, there may be various methods of forming the thickness of the photoresist film differently according to the position. A semi-transparent area as well as a transparent area and a light blocking area may be formed in the exposure mask. For example. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process.

Next, as shown in FIGS. 9 and 10, the data layer 170 exposed to the remaining portion C is removed by wet etching using the first photoresist pattern 52 to remove the plurality of data patterns 174. Form.

The semiconductor layers 151 and 154 are subsequently dry-etched by dry etching the amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 doped with impurities remaining in the remaining portion C in succession, and the impurities are doped. An amorphous silicon layer 164 is formed.

Next, as shown in FIGS. 11 and 12, the second photoresist pattern 54 present in the channel portion B is removed using an etch back process. At this time, since the first photoresist pattern 52 is also removed by the thickness of the second photoresist pattern 54, it becomes thin. Therefore, the width of the photoresist pattern 52 is smaller than the width of the data pattern 174 to expose the data pattern 174.

Next, as shown in FIGS. 13 and 14, the first photoresist pattern 52 is heat-treated at about 130 to 150 ° C. to reflow. As described above, the photoresist pattern 52 may be easily reflowed in the above temperature range because it includes the photosensitive compound having a ballast structure and a heat resistance control additive. Therefore, the reflowed first photoresist pattern 52a completely covers the exposed data pattern 174 and the side surfaces of the data pattern 174.

At this time, since the first photoresist pattern 52a also flows into the channel B portion, the width of the channel B portion is adjusted so that the first photoresist pattern 52a does not completely cover the channel portion, thereby maintaining the channel width.

Next, the data pattern 174 is etched using the remaining first photoresist layer pattern 52a as a mask, and is separated into a source electrode 173 and a drain electrode 175, and between the source electrode 173 and the drain electrode 175. The amorphous silicon pattern 164 doped with impurities is exposed in the channel region of the substrate. In this case, since the side surface of the portion of the data pattern 174 to be the data line 171 is protected by the first photoresist pattern 52a, the data line is separated when the source electrode 173 and the drain electrode 175 are separated. Since the portion 171 is not removed, the lower semiconductor under the data line 171 is not exposed.

Next, as shown in FIGS. 15 to 17, the exposed portion of the amorphous silicon pattern 164 doped with impurities is dry-etched. At this time, the dry etching uses a chlorine-containing gas such as Cl ₂ , HCl, BCl ₃ , CCl ₄ , SiCl ₂ H ₂ .

Then, the first photosensitive film pattern 52 is removed.

Next, as shown in FIGS. 18 to 20, the passivation layer 180 is formed to cover the protrusion 154 of the semiconductor that is not covered by the data line 171 and the drain electrode 175.

Subsequently, the passivation layer 180 is etched to form a plurality of contact holes 181, 182, 183a, 183b, and 185.

 Finally, as shown in FIGS. 1 to 3, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 180 by sputtering, and then patterned to form the pixel electrode 191 and the contact auxiliary members 81 and 82. And a connecting leg 83.

As described above, when the photoresist film of the channel portion is removed, the photoresist film on the data line may also be removed to expose the data lines. However, by reflowing the photoresist film, the data lines may be prevented from being exposed. Therefore, when the conductor of the channel part is removed, the data line is removed together so that the lower semiconductor is not exposed, so that the exposed semiconductor does not generate leakage current by light.

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (10)

Forming a gate line on the substrate, Stacking a gate insulating film, an amorphous silicon layer not doped with impurities, an amorphous silicon layer doped with impurities, and a conductive layer on the gate line; Forming a photoresist pattern on the conductive layer, the photoresist pattern including a first portion and a second portion having a thickness greater than the first portion; Etching the conductor using the photoresist pattern as a mask to form a conductor pattern; Subsequently etching the amorphous silicon layer doped with the impurity and the amorphous silicon layer not doped with the impurity to form an ohmic contact pattern and a semiconductor; Removing a first portion of the photoresist pattern, Reflowing a second portion of the photoresist pattern; Etching the conductor pattern using the first reflowed photoresist pattern as a mask to form a data line and a drain electrode; Etching the ohmic contact pattern using the first reflowed photoresist pattern as a mask to form an ohmic contact member; Removing the photoresist pattern; Forming a passivation layer covering the data line and the drain electrode and including a contact hole exposing the drain electrode; Forming a pixel electrode connected to the drain electrode through the contact hole on the passivation layer Method of manufacturing a thin film transistor array panel comprising a. In claim 1, And the data layer comprises copper or a copper alloy, aluminum or an aluminum alloy, silver or a silver alloy. In claim 1, The reflowing of the photoresist pattern may be performed at 130 to 150 ° C. In claim 1, The photosensitive film pattern is an alkali-soluble resin, and Balast structure of formula (I)

(Wherein R ₁ and R ₂ are alkyl groups and R ₁ and R ₂ may be the same or different) Photosensitive compound having Method of manufacturing a thin film transistor array panel comprising a. In claim 4, The photosensitive compound is a diazide compound manufacturing method of a thin film transistor array panel. In claim 4, The photoresist pattern may further include a heat resistance control additive. In claim 6, The heat resistance regulating additive is a first compound of formula (II)

(Where R is a methyl group, an ethyl group, or a propyl group) And Second compound of formula (III)

(Wherein R ₁ is a methyl group, ethyl group, propyl group, butyl group, pentyl group, hexyl group, and R ₂ is hydrogen (H) or methyl group) The manufacturing method of the thin film transistor array panel containing at least one of the. In claim 6, The heat resistance control additive is a method of manufacturing a thin film transistor array panel having an average molecular weight of 200 to 400. In claim 6, The photosensitive film pattern is a method of manufacturing a thin film transistor array panel comprising 5 to 30% by weight alkali-soluble resin, 2 to 10% by weight photosensitive compound, 0.5 to 3% by weight heat resistance control additive and the remaining amount of solvent. In claim 9, The alkali-soluble resin is a method of manufacturing a thin film transistor array panel containing a meta (m) -cresol and para (p) -cresol and a novolak resin having an average molecular weight of 2,000 to 5,000.

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