KR20070054408A - Method for manufacturing in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device capable of stably maintaining device characteristics by preventing an electric field from being concentrated on both sides of the gate electrode, forming a gate electrode on a substrate and performing an oxidation process It provides a method of manufacturing a semiconductor device comprising the step of selectively increasing the thickness of both sides of the gate oxide film constituting the gate electrode. In addition, providing a substrate defined by a high voltage region in which a high voltage transistor is to be formed and a low voltage region in which a low voltage transistor is to be formed; Forming a gate conduction layer on the high voltage gate oxide layer and the low voltage gate oxide layer, selectively etching a portion of the gate conductive layer and the high voltage gate oxide layer in the high voltage region to form a high voltage gate in the high voltage region Forming an electrode, performing an oxidation process to selectively increase both side thicknesses of the high voltage gate oxide film, and selectively etching a portion of the gate conductive film and the low voltage gate oxide film in the low voltage region to form the low voltage domain It provides a semiconductor device manufacturing method comprising forming a low-voltage gate electrode.

 High voltage transistor, gate oxide, thickness, thermal oxidation.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING IN SEMICONDUCTOR DEVICE}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

1, 20: substrate

2, 21: field oxide film

3, 7, 22, 25, 21a: gate oxide film

4, 9, 12, 23, 27, 31: photoresist pattern

5, 10, 13, 24, 28, 32: etching process

8, 26: polysilicon film

11, 33: low voltage gate electrode

15, 30: high voltage gate electrode

HV: high voltage region

LV: low voltage region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a VLSI (Very Large Scale Integration) semiconductor device for implementing a high voltage transistor and a low voltage transistor in one chip.

Recently, in accordance with the high integration of semiconductor devices, semiconductor memory cells, high voltage transistors and low voltage transistors for driving the cells are implemented in one chip.

Hereinafter, a method of manufacturing a semiconductor device in which a high voltage transistor and a low voltage transistor are implemented in one chip according to the related art will be described with reference to FIGS. 1A to 1F.

First, as shown in FIG. 1A, a field oxide film 2 is formed on a substrate 1 by performing a LOCOS (LOCal Oxidaton of Silicon) process, whereby a high voltage region (Hv, High Voltage) and a low voltage at which a high voltage transistor is to be formed. A low voltage region LV in which a transistor is to be formed is defined.

Subsequently, an oxidation process is performed to form the gate oxide film 3 on the surface of the substrate 1 in the high voltage and low voltage regions HV and LV.

Subsequently, as shown in FIG. 1B, a photoresist is performed to form the photoresist pattern 4 having the structure of opening the low voltage region LV on the gate oxide film 3. Then, an etching process 5 using the photoresist pattern 4 as an etching mask is performed to etch the exposed gate oxide film 3 (hereinafter, referred to as a high voltage gate oxide film) in the low voltage region LV.

As a result, the high voltage gate oxide film 3 formed to have a thickness of T ₁ remains only in the high voltage region HV.

Subsequently, as shown in FIG. 1C, an oxide process is performed to form a gate oxide film 7 (hereinafter, referred to as a low voltage gate oxide film) on the exposed surface of the substrate 1 in the low voltage region LV. At this time, the thickness T ₂ of the low voltage gate oxide film 7 is thinner than the thickness T ₁ of the high voltage gate oxide film 3.

Subsequently, a strip process is performed to remove the photoresist pattern 4 (see FIG. 1B). Subsequently, a polysilicon film 8 used as a gate conductive film is deposited on the upper surface of the entire structure including the high voltage gate oxide film 3 and the low voltage gate oxide film 7.

Subsequently, as shown in FIG. 1D, a photoresist is performed to form the photoresist pattern 9 on the polysilicon film 8. The photoresist pattern 9 is used to define a gate electrode of the low voltage transistor, and has a structure in which a part of the low voltage region LV is open.

Subsequently, an etching process 10 using the photoresist pattern 9 as an etching mask is performed to sequentially etch the polysilicon film 8 and the low voltage gate oxide film 7 in the low voltage region LV. As a result, the gate electrode 11 (hereinafter referred to as a low voltage gate electrode) of the low voltage transistor is formed in the low voltage region LV.

Subsequently, as shown in FIG. 1E, a strip process is performed to remove the photoresist pattern 9, and then a photo process is performed to form another photoresist pattern 12. Here, the photoresist pattern 12 is used to define a gate electrode of the high voltage transistor, and has a structure in which a part of the high voltage region HV is opened.

Next, an etching process 13 using the photoresist pattern 12 as an etching mask is performed to sequentially etch the polysilicon film 8 and the high voltage gate oxide film 3 in the high voltage region HV. As a result, the gate electrode 15 of the high voltage transistor (hereinafter, referred to as a high voltage gate electrode) is formed in the high voltage region HV.

Subsequently, as shown in FIG. 1F, a strip process is performed to remove the photoresist pattern 12 (see FIG. 1E). As a result, the high voltage gate electrode 15 and the low voltage gate electrode 11 having the high voltage gate oxide film 3 and the low voltage gate oxide film 7 having different thicknesses are exposed.

In general, the high-voltage gate oxide film 3 should have a thickness of the oxide film at the center portion smaller than the oxide film thickness at both sides thereof. In the case of a high voltage transistor, when the thickness at both sides of the gate oxide film is thin, an electric field is concentrated at both sides of the high voltage gate oxide film 3, that is, at the interface where the high voltage gate oxide film 3 is in contact with the drain. This is because the operation characteristics of the semiconductor device change as hot carriers increase.

However, the high voltage gate oxide film 3 of the semiconductor device formed in accordance with the prior art has a uniform thickness between the center portion and both sides in Es and changes the operating characteristics of the semiconductor element as the electric field is concentrated at both sides.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of stably maintaining device characteristics by preventing an electric field from being concentrated on both sides of a gate electrode. have.

According to an aspect of the present invention, there is provided a semiconductor device including forming a gate electrode on a substrate, and selectively increasing a thickness of both sides of a gate oxide layer forming the gate electrode by performing an oxidation process. Provided is a device manufacturing method.

In addition, according to another aspect of the present invention, there is provided a substrate including a high voltage region in which a high voltage transistor is to be formed and a low voltage region in which a low voltage transistor is to be formed, and the substrate surface of the high voltage and low voltage region. Forming a high voltage gate oxide film and a low voltage gate oxide film on the high voltage gate oxide film and the low voltage gate oxide film, respectively, and depositing a gate conductive film on the high voltage gate oxide film and the low voltage gate oxide film, and the gate conductive film and the high voltage gate in the high voltage region. Selectively etching a portion of an oxide film to form a high voltage gate electrode in the high voltage region, and performing an oxidation process to selectively increase both side thicknesses of the high voltage gate oxide film, and to form the gate conductive film in the low voltage region. And the low voltage gate And selectively etching a portion of an oxide film to form a low voltage gate electrode in the low voltage region.

In the present invention, the step of selectively increasing the thickness of both side portions of the gate oxide layer is performed by a thermal oxidation process to form an oxide film having a buzz bead shape on each side of the gate oxide layer.

According to the present invention described above, the thickness of both side portions of the gate oxide film constituting the gate electrode when the gate electrode is formed in the semiconductor device is selectively increased to vary the thickness between the center portion and both sides of the gate oxide film, thereby concentrating on both sides of the gate oxide film. The electric field can be dispersed and relaxed.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be on another layer or substrate it may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. Here, a semiconductor device manufacturing method for forming a high voltage transistor and a low voltage transistor on one chip will be described as an example.

First, as shown in FIG. 2A, by performing a LOCOS process to form a field oxide film 21 in a portion of the substrate 20, a high voltage region HV and a low voltage transistor in which a high voltage transistor is to be formed in the substrate 20. Defines a low voltage region LV to be formed.

Subsequently, an oxidation process is performed to form a gate oxide film 22 on the surface of the substrate 20 in the high voltage and low voltage regions HV and LV.

Subsequently, as illustrated in FIG. 2B, a photoresist is performed to form a photoresist pattern 23 having a structure for opening the low voltage region LV on the gate oxide film 22. Next, an etching process 24 using the photoresist pattern 23 as an etching mask is performed to etch the exposed gate oxide layer 22 (hereinafter, referred to as a high voltage gate oxide layer) in the low voltage region LV.

As a result, the high voltage gate oxide film 22 formed to have a thickness of T ₁ remains only in the high voltage region HV.

Subsequently, as illustrated in FIG. 2C, an oxide process is performed to form a gate oxide film 25 (hereinafter, referred to as a low voltage gate oxide film) on the exposed surface of the substrate 20 in the low voltage region LV. At this time, the thickness T ₂ of the low voltage gate oxide film 25 is thinner than the thickness T ₁ of the high voltage gate oxide film 22. This is because a gate oxide film thicker than a low voltage transistor is required due to the operation characteristics of the high voltage transistor.

Subsequently, a strip process is performed to remove the photoresist pattern 4 (see FIG. 2B). Subsequently, a polysilicon film 26 used as a gate conductive film is deposited on the upper surface of the entire structure including the high voltage gate oxide film 22 and the low voltage gate oxide film 25. In this case, the polysilicon layer 26 is deposited by a low pressure chemical vapor deposition (LPCVD) method using a doped or undoped silicon layer.

For example, the doped polysilicon film is formed using SiH ₂ and PH ₃ or Si ₂ H ₆ and PH ₃ gases. On the other hand, in the case of the undoped polysilicon film, impurities are added during the subsequent LDD ion implantation process or the source / drain ion implantation process to dope the polysilicon film 26.

Subsequently, as shown in FIG. 2D, a photoresist is performed to form a photoresist pattern 27 having a structure in which a part of the high voltage region HV is opened. Here, the photoresist pattern 27 is for defining the gate electrode of the high voltage transistor.

Subsequently, an etching process 28 using the photoresist pattern 27 as an etching mask is performed to sequentially etch the exposed polysilicon layer 26 and the high voltage gate oxide layer 21 in the high voltage region HV. As a result, the gate electrode 21 (hereinafter referred to as a high voltage gate electrode) of the high voltage transistor is formed in the high voltage region HV.

Subsequently, as shown in FIG. 2E, a strip process is performed to remove the photoresist pattern 27. Then, a thermal oxidation process is performed to increase the thickness of both sides of the high voltage gate oxide film 21 (see FIG. 2D). For example, a high voltage gate oxide film 21a having a bud's beak type oxide film formed on both sides is formed through a thermal oxidation process.

That is, by forming the high voltage gate oxide film 21a having the Buzzvik-type oxide film formed on both sides, the thickness of the high voltage gate oxide film 21a is thicker on both sides than the center portion, so that the high voltage gate oxide film 21a is concentrated on both sides of the high voltage gate oxide film 21a. The electric field can be dispersed and relaxed.

Although not shown in the drawings, during the thermal oxidation process, a separate oxide film may be deposited at a high temperature along a step of an upper portion of the entire structure including the high voltage gate electrode 30. For this reason, an oxide film in the form of a buzz bend is formed on both sides. Thereafter, the deposited oxide film may be removed through a separate cleaning process.

At this time, since the thermal oxidation process is performed before the gate electrode of the low voltage transistor is formed, the thickness of the low voltage gate oxide film 25 forming the gate electrode of the low voltage transistor is not affected.

Subsequently, as illustrated in FIG. 2F, a photo process is performed to form the photoresist pattern 31. The photoresist pattern 31 is used to define a gate electrode of the low voltage transistor, and has a structure in which a part of the low voltage region LV is open.

Subsequently, an etching process 32 using the photoresist pattern 31 as an etching mask is performed to sequentially etch the polysilicon layer 26 and the low voltage gate oxide layer 25 exposed to the low voltage region LV. As a result, the gate electrode 33 (hereinafter referred to as a low voltage gate electrode) of the low voltage transistor is formed in the low voltage region LV.

Subsequently, as shown in FIG. 2G, a strip process is performed to remove the photoresist pattern 31 (see FIG. 2F). As a result, the high voltage gate electrode 30 and the low voltage gate electrode 33 are exposed.

Subsequently, although not shown in the drawings, spacers are formed on both sidewalls of the high voltage gate electrode 30 and the low voltage gate electrode 33, and then a source / drain ion implantation process using the spacers as a mask is performed to obtain the high voltage gate electrode ( The source / drain regions may be formed in the substrate 20 exposed on both sides of the 30 and the low voltage gate electrode 33, respectively.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, when forming the gate electrode of the semiconductor device, the thickness of both side portions of the gate oxide film forming the gate electrode is selectively increased to vary the thickness between the center portion and both sides of the gate oxide film. The electric field concentrated on both sides can be dispersed and relaxed.

Therefore, the snap-back characteristic can be improved.

Further, according to the present invention, the thickness of both sides of the gate oxide film is selectively increased to form a gate oxide film whose thickness on both sides is thicker than the thickness at the center portion, so that when the high voltage is applied to the drain in the off state, The deterioration of device characteristics due to coupling can be reduced.

In addition, according to the present invention, a semiconductor device having stable device characteristics is formed by reducing the hot carrier generation by forming a gate oxide film having a thickness at both sides that is thicker than a thickness at the center portion to increase the gate oxide film thickness at a portion in contact with the drain. It can manufacture.

Claims (4)

Forming a gate electrode on the substrate; And Selectively increasing the thickness of both sides of the gate oxide layer forming the gate electrode by performing an oxidation process Semiconductor device manufacturing method comprising a. The method of claim 1, In the step of selectively increasing the thickness of both sides of the gate oxide film, a thermal oxidation process is performed to form an oxide film having a buzzvik shape on each side of the gate oxide film. Providing a substrate defined by a high voltage region where a high voltage transistor is to be formed and a low voltage region where a low voltage transistor is to be formed; Forming a high voltage gate oxide film and a low voltage gate oxide film having different thicknesses on the surface of the substrate in the high voltage and low voltage regions, respectively; Depositing a gate conductive film on the high voltage gate oxide film and the low voltage gate oxide film; Selectively etching a portion of the gate conductive layer and the high voltage gate oxide layer in the high voltage region to form a high voltage gate electrode in the high voltage region; Performing an oxidation process to selectively increase both side thicknesses of the high voltage gate oxide film; And Selectively etching a portion of the gate conductive layer and the low voltage gate oxide layer in the low voltage region to form a low voltage gate electrode in the low voltage region Semiconductor device manufacturing method comprising a. The method of claim 3, wherein In the step of selectively increasing the thickness of both sides of the high voltage gate oxide film, a thermal oxidation process is performed to form a oxide film in the form of a buzz bead on both sides of the high voltage gate oxide film.

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