KR20070052877A - Pre-branch pattern generator for test system of semiconductor apparatus - Google Patents

Abstract

A pre-branching pattern generator for testing systems of semiconductor devices is presented.

The pattern generating apparatus of the present invention is to be read out of a test pattern written in a pre-branch programming language and a pattern memory in which a pattern program including a branch position is stored according to whether each test pattern is true or false, or an instruction stored in the pattern memory. A command counter that designates an instruction and branches to a true point or a false point according to the comparison result of the comparator, and designates a branch instruction of the pattern memory by the program counter designating a branch instruction of the pattern memory. When a calculation command is included, a comparator for providing the calculation contents to the calculator, a calculator for performing the calculation command at the request of the comparator, and a result of execution of the calculator are stored, and a register file for providing the calculation result to the comparator and the calculator. Include.

According to the present invention, since a pattern program for a test system is prepared using a high-level language such as C, which facilitates user interface, the semiconductor device can be tested more simply and easily.

Semiconductor, test, pattern generator

Description

Pre-Branch Pattern Generator for Test System of Semiconductor Apparatus

1 is a configuration diagram of a test system of a general semiconductor device;

2 is a configuration diagram of a general pattern generator;

3 is a block diagram of a pattern generator according to the present invention;

4 is a detailed configuration diagram of the program counter shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

200: pattern generator 210: program counter

220: pattern memory 230: comparison unit

240: calculator 250: register file

2110: multiplexer 2120: output register

2130: interrupt register 2140: return register

The present invention relates to a pattern generator, and more particularly to a pre-branch pattern generator for a test system of a semiconductor device.

With high integration of semiconductor devices, manufacturing processes become more stringent, and the operating speed of semiconductor devices is rapidly increasing. In addition, the performance of the semiconductor device depends on the performance of the system using the semiconductor device, and therefore, supplying a semiconductor device without defects and initial detection of defects therefor has become another research subject.

A test method using a pattern generator that generates a test pattern according to a predetermined algorithm, reads data written in a semiconductor device, in particular, a memory device, determines the read data, and outputs the result as one of the test methods of the semiconductor device. Can be mentioned.

1 is a configuration diagram of a test system of a general semiconductor device, and illustrates a test system using a pattern generator.

As shown in the drawing, the test system 100 includes a control unit 110 that controls an overall operation, a pattern generator 120 and a pattern generator 120 that generate and output a test pattern according to the control of the controller 110. The input driver 130 through which the generated test pattern is input, and through the output driver 140 and the output driver 140 that receive processing results according to the test pattern input to the test board 160 through the input driver 130. Comparing unit 150 for comparing the output signal and the predetermined signal is provided.

Here, the pattern generator 120 is an apparatus that operates by describing a pattern to be tested based on a language technical expression. Currently, the pattern generator 120 implements the pattern generator 120 using machine language of a computer. Algorithm Language Pattern Generator) is mainly used.

The ALPG pattern generator is used to compile a program written in machine language into a binary file. The compiled binary file includes a pattern flow control part, an address data generation part, a timing generation part, and the like. The machine instructions of the pattern flow control part include, for example, NOP (Not operation), JMP (Jump), CAL (Call), RET (Return), SET, HOLD, etc. JST), an instruction (JIR) which means to repeat the number of index registers by 1, and the like can be variously modified. In addition, the address data generation portion generates comparison of registers, operation scrambling, and the like, and the timing generation portion generates a specified timing according to each pattern flow.

An example of a pattern program expressed in machine language is shown in [Table 1].

TABLE 1

Pattern flow control part Address generation part Timing Generation Part One SET R0 = 1, 2 SET A = 0, 3 SET D = 1 4 LAB1 NOP           / D,    T = ACT 5 NOP    T = NOP 6 NOP    T = READ 7 JMP LAB1 (100) A = A + R0    T = PRE 8 NOP

[Table 1] shows the pattern for the test through the read operation of the memory device, / D means the pattern to change the data once according to one read operation, and the address is referenced from 0th to 100th. . In addition, looping is performed while repeating from 4 to 7 lines, the number of loops is determined at the time of the jump command (7 lines), and 8 lines are executed after 100 loops are completed.

2 is a configuration diagram of a general pattern generator.

As illustrated, the pattern generator 120 may include a program counter 1210, a pattern memory 1220, a branch control unit 1230, a loop index 1240, a comparison unit 1250, an operation unit 1260, and a register file ( 1270).

Referring to Table 1, the operation of the pattern generator shown in FIG. 2 will be described. First, a pattern program as shown in Table 1 is stored in the pattern memory 1220, and the program counter 1210 designates a command to be read from the pattern memory 1220. When the program counter 1210 specifies the branch instruction (line 7 of Table 2) of the pattern memory 1220, it is loaded into the branch control unit 1230, and the branch control unit 1230 is the loop index 1240 and the comparison unit. 1250, it is determined whether to branch. In addition, the operation unit 1260 performs an operation such as increasing or decreasing an address with reference to an instruction (eg, A = A + R0) of an address data generation portion stored in the pattern memory 1220. In addition, the execution result of the calculator 1260 is stored in the register file 1270.

In this way, the current pattern generator is a post-structure because the content of whether the branch is always present at the rear and performs the looping with reference to this.

However, when the pattern program is written in machine language, its contents have a huge and complicated disadvantage. Therefore, an attempt has been made to generate a pattern with a high-level language expression such as C language, which is easy for user interface.

When [Table 1] is expressed in a high-level language, it is shown in [Table 2].

TABLE 2

For (R0 = 0; R0 <100; R ++) {/ D T = ACT T = NOP T = READ A = R0 T = PRE}

In [Table 2], / D means a pattern that changes data once every read operation. As such, a high-level language such as the C language has an advantage that a user can easily recognize, and thus can easily understand the test pattern program. However, patterns written in high-level languages also need to be converted back to machine language in order to operate on hardware, which causes a problem of reordering or complicating the compilation process. This is because the machine language has the branching position of the pattern at the bottom while the C language has the branching position of the pattern at the front, so that the compatibility is not perfect during the compilation process.

In other words, high-level languages such as C language have excellent user interfacing, but when converting them into machine language, errors may occur due to the difference in structure between machine language and C language. There is a problem that can only be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the user interface is prepared by writing a test pattern program in a high-level language in which a branch position is located in front, and simultaneously describing a branch position according to branch conditions at the time of compilation with instructions. There is a technical problem to provide this easy pre-branching pattern generator.

The pattern generator for a test system of a semiconductor device according to an embodiment of the present invention for achieving the above-described technical problem is a pattern generator for a test system of a semiconductor device for generating and outputting a test pattern, A pattern memory for storing a test pattern written in a program language and a pattern program including a branch position according to whether each test pattern is true or false; A program counter for designating a command to be read among the commands stored in the pattern memory, and branching to a true point or a false point according to a comparison result of the comparator to designate a command of a corresponding position; A comparator for determining whether to branch according to the program counter designating a branch instruction of the pattern memory, and for providing calculation contents to a calculation unit when a branch instruction includes a calculation instruction; An operation unit configured to perform an operation command in response to a request of the comparison unit; And a register file that stores an execution result of the operation unit and provides an operation result to the comparison unit and the operation unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a pattern generator according to the present invention.

The pattern generating apparatus 200 according to the present invention is a pattern memory 220 in which a preprogrammed high-level language (for example, C language) is written and a pattern program in which a branch position is designated according to whether each pattern is true or false is stored. ) Designates a command to be read among the commands stored in the pattern memory 220, and branches to a true point (TP) or a false point (FP) according to the comparison result of the comparator 230. The program counter 210 designating the instruction of the position, the program counter 210 determines whether to branch according to the designation of the branch instruction of the pattern memory 220, and if the operation instruction is included in the branch instruction operation unit 240 In accordance with the request of the comparator 230, the comparator 230 to provide a calculation operation performed by the operation unit 240 and operation unit 1260 is stored and the operation results are stored in the comparator 230 and the operation unit ( Registers provided by Contains file 1270.

Here, in the pattern memory 220, conditional statements for branching, for example, IF statements, IF-ELSE statements, FOR statements, and the like are described in a pre-branch structure, and each conditional statement is true or false. In this case, the position of the pattern memory 220 to be branched is described, and the position of the pattern memory 220 to be branched according to whether it is true or false to perform a given instruction, and to which position of the pattern memory 220 to be branched sequentially is sequentially described. The pattern program is stored.

An example of such a pattern program is shown in [Table 3] to [Table 5].

TABLE 3

TP FP One if (Xa <300) +1 +4 2 {T = A +1 +0 3                     T = R +1 +0 4       X = Xa / D T = P +4 +0 } Else 5 {T = A +1 +0 6                     T = R +1 +0 7      X = Xb / D T = P +1 +0 } 8

TABLE 4

TP FP One if (Xa <300) +1 +2 2 {X = Xa T = T0 +1 +0 } 3

TABLE 5

TP FP One for (Xa = S0) +2 +0 2 for (Xa <S6; Xa ++) +1 +6 3 for (Ya = S0) +2 4 for (Ya <S6; Ya ++) +1 +2 5    {T = A +1 6                      T = R +1 7      X = Xa, Y = Ya / D T = P -3     } 8

In Tables 3 to 5, TP and FP represent the increase or decrease of the address address when they are true or false, respectively, and may be described as an absolute address.

First, [Table 3] shows the IF ~ ELSE syntax in the form of a pattern program for use in the present invention. The comparison unit 230 determines whether Xa is less than 300. It moves to the position where A is substituted for T, increases the address by 1, and moves to the position where R is substituted for T, then X is substituted for X, P is substituted for T, and 4 is increased. Accordingly, since the symbol {} indicating the end of the program is recognized, the read test operation is terminated. On the other hand, the comparison unit 230 determines whether Xa is less than 300, and if false, branches to the position where the address is increased by 4, that is, ELSE syntax, and performs the subsequent process.

[Table 4] shows the IF syntax in the form of a pattern program for use in the present invention. If the comparison unit 230 determines whether Xa is less than 300, and if true, the position where the address is increased by one, that is, Xa is added to X. Assign and move to the position where T0 is assigned to T, and exit. If false, the program terminates.

[Table 5] shows the FOR syntax in the form of a pattern program for use in the present invention. When the comparison unit 230 checks whether Xa is S0, and if it is true, it checks whether the address is increased by 2, that is, Ya is S0. Go to location. Then, the comparison unit 230 checks whether Ya is S0, and if it is true, increases the address by 2 and substitutes A for T, then substitutes R for T, then substitutes Xa for X and Ya for Y, After moving to the position where P is substituted, the address moves to the position where the address is reduced by 3 to repeat the process of T = A, T = R, T = P, that is, the read operation on the test board. If it is found that Ya is less than S6, and if it is false, the address is moved to the position where the address is reduced by two, and branching is made to the position to confirm whether Xa is less than S6. After increasing, the loop is repeated repeatedly. If false, the loop is determined to be completed, and the program is moved to the position where the address is increased by 6 and terminated.

As described above, in the present invention, a pattern program is created in a high-level language having a transposition branch structure, and at this time, a compilation is performed so that a position to branch is described depending on whether the execution result of each pattern is true or false. Is stored in the pattern memory 220.

When the program counter 210 designates a command stored in the pattern memory 220 during the semiconductor device test, the comparator 230 determines whether a branch is present and the branch position, and provides the program counter 210 to the program counter 210. Reference numeral 210 designates a specific location of the pattern memory 220 according to a case in which the comparison unit 230 determines the true or false, and provides the selected command to the test board. In addition, when the instruction loaded into the comparing unit 230 by the program counter 210 includes an operation instruction, this is performed by the calculating unit 240, and the result is stored in the register file 250 so that subsequent comparison and Will be referenced in the operation.

FIG. 4 is a detailed circuit diagram of the program counter shown in FIG. 3.

Program counter 210 applied to the present invention is a plurality of data input terminals (IN_A, IN_B, IN_C, IN_D), comparison control signal input terminal (COMPARE), interrupt control signal input terminal (INTERRUPT), return control signal input terminal ( The output signal of the multiplexer 2110 and the multiplexer 2110 that receives the data signal and the control signal through the RETURN) and outputs any one signal through the output terminal OUT_O, and then outputs the output signal (PC_OUT). As the output register 2120 and the interrupt setting signal INT_SET are enabled, the true register signal TP is stored, and the interrupt instruction is transmitted to the data input terminal IN_C of the multiplexer 2110 for output. An interrupt register 2130 for outputting an interrupt command through the terminal OUT_O, and receives and stores an output signal of the output register 2120 as the interrupt setting signal is enabled. As the block provides a return instruction to the data input terminal (IN_D) of the multiplexer 2110 and includes a return register (2140) for outputting a return command through the terminal chulryeo (OUT_O).

Here, a true point signal is input to the data input terminal IN_A and a false point signal is input to the data input terminal IN_B.

The program counter 210 is for outputting a signal of either TP or FP by the comparison signal. If an interrupt control signal or a return control signal is generated during operation, the program counter 210 converts the interrupt signal or the return signal into a high priority signal. Treat it as an interrupt command or return command rather than a TP or FP signal.

Here, each of the registers 2120, 2130, and 2140 operates in synchronization with a clock signal, and the RUN_HOLD signal is a signal for determining the progress and stop of pattern progress.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

According to the present invention, since a pattern program for a test system is prepared using a high-level language such as C, which facilitates user interface, the semiconductor device can be tested more simply and easily. In addition, the branch position can be specified by simple compilation only when the pattern of the pre-branch structure is generated, so that it can be applied without changing hardware, and it is easy to develop, maintain, maintain and add test equipment, and reduce costs.

Claims (6)

A pattern generator for a test system of a semiconductor device for generating and outputting a test pattern, A pattern memory configured to store a test pattern written in a pre-branch programming language and a pattern program including a branch position according to whether each test pattern is true or false; A program counter for designating a command to be read among the commands stored in the pattern memory, and branching to a true point or a false point according to a comparison result of the comparator to designate a command of a corresponding position; A comparator for determining whether to branch according to the program counter designating a branch instruction of the pattern memory, and for providing calculation contents to a calculation unit when a branch instruction includes a calculation instruction; An operation unit configured to perform an operation command in response to a request of the comparison unit; And A register file that stores an execution result of the operation unit and provides an operation result to the comparison unit and the operation unit; Pre-branching pattern generator for a test system of a semiconductor device comprising a. The method of claim 1, The pattern memory may branch according to at least one conditional statement for branching, the position of the pattern memory to branch if each conditional statement is true or false, and perform a given instruction by branching according to whether it is true or false. A pre-branching pattern generator for a test system of semiconductor devices, characterized by storing a pattern program describing the location of the memory. The method of claim 2, And the conditional phrase includes at least one of an IF statement, an IF ~ ELSE statement, and a FOR statement. The method of claim 1, The program counter outputs any one of a signal input through a data input terminal, a comparison control signal input terminal, an interrupt control signal input terminal, and a return control signal input terminal to which a true point signal and a false point signal are input through an output terminal. Multiplexer; An interrupt register for storing the true point signal as the interrupt setting signal is enabled and transmitting and outputting an interrupt command for transmitting the enable signal to the multiplexer as the interrupt control signal is enabled; A return register for storing an output signal of the multiplexer and transmitting a return command to the multiplexer so that the interrupt setting signal is enabled; And An output register for temporarily storing and outputting an output signal of the multiplexer; Pattern generating device for a test system of a semiconductor device comprising a. The method of claim 1, And the true point and the false point are increments or decrements of the address address. The method of claim 1, And the true point and the false point are absolute addresses of addresses.

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