KR20070052508A - Apparatus and method for interfacing between the modules in communication system - Google Patents

Abstract

The present invention relates to an interface device and a method between a control module and an external module in a communication system. The interface device according to the present invention includes a multiport memory for storing data exchanged between a control module and a plurality of external modules in a unique address area of a corresponding external module, and recording an update address value of the multiport memory. An index register, and a management logic for controlling access to the multiport memory and the index register of the control module and the plurality of external modules. As described above, the present invention can simplify the signal processing structure and reduce the software load.

Control module, external module, interface, interrupt, register bank

Description

Interface device and method between module in communication system {APPARATUS AND METHOD FOR INTERFACING BETWEEN THE MODULES IN COMMUNICATION SYSTEM}

1 is a view showing an interface device between a control module and an external module in a communication system according to the prior art.

2 illustrates an interface device between a control module and an external module in a communication system according to an embodiment of the present invention.

3 is a diagram illustrating an interrupt request processing procedure of a register bank according to an embodiment of the present invention.

4 is a diagram illustrating an interrupt processing procedure of a control module according to an embodiment of the present invention.

5 is a diagram illustrating an interrupt processing procedure of an external module according to an embodiment of the present invention.

The present invention relates to an inter-module interface device and method in a communication system, and more particularly, to an interface device and method between a control module and an external module in a communication system.

In general, in a communication system, control logic and external device logic are directly connected to interface data and addresses.

1 illustrates an interface device between a control module and an external module in a communication system according to the related art. As shown in the drawing, the interface device according to the related art includes a control module 100, an address decoder 102, and a plurality of external modules 104-1 to 104-4. Here, it is assumed that there are four external modules 104-1 to 104-4. Hereinafter, a case in which data is transmitted from the control module 100 to the external module 104-2 will be described by way of example.

Referring to FIG. 1, first, the control module 100 outputs data to be transmitted to the external module 104-2 on a data bus, and outputs an address on which the data is to be written on an address bus. . The address decoder 102 decodes an address input through the address bus and generates a chip selection (CS) signal for selecting the corresponding external module 104-2. The external module 104-2 receives and processes data and addresses carried on the data bus and the address bus by a chip select signal from the address decoder 102.

On the other hand, as shown, the control module 100 and the external modules (104-1 to 104-4) is connected to the interrupt signal line in a one-to-one, the control module 100 is the external modules ( 104-1 to 104-4) to receive and process the interrupt directly.

However, the above structure has the following problems.

First, when a control module (eg CPU) controls an external module or requests an interrupt from an external module to a control module, both modules must be in processing mode because data and address are directly interfaced.

Second, when more than one control module accesses one external module, it is not possible to immediately check the value set in another control module or the interrupt requested by another control module.

Third, in case of assigning interrupts for each external module, if the number of external modules increases, the number of interrupt signals should be increased. If the number of interrupts provided by the control module is exceeded, as many interrupts as desired can't be used. Additional circuitry must be configured.

Fifth, when adding a control module, additional bus and logic should be configured for the control module. At this time, the external module that does not match the bus system supported by the additional CPU is controlled separately using the GPIO (general purpose I / O) of the CPU, in this case may cause additional software load,

In recent years, communication systems have been equipped with a large number of control modules and external logic modules (external modules) to support more functions or to accommodate more users. In this case, the direct connection between the control module and the external module as described above has a problem of inefficiency in consideration of complexity, circuit integration, efficient operation and expansion.

Accordingly, an object of the present invention is to provide an interface device and method between a control module and an external module in a communication system.

Another object of the present invention is to provide an apparatus and method for interfacing a control module and an external module with a register bank in a communication system.

Still another object of the present invention is to provide an apparatus and a method for a control module to efficiently control an external module and efficiently handle interrupts from an external module in a communication system.

According to an aspect of the present invention for achieving the above object, in the communication system in the interface device between the control module and the external module, the unique address of the external module for the data exchanged between the control module and the plurality of external modules A multiport memory for storing in an area, an index register for recording an update address value of the multiport memory, and for controlling access of the multiport memory and the index register of the control module and the plurality of external modules It is characterized by including the management logic.

According to another aspect of the invention, in the signal processing method in the interface device between the control module and the external module, when the interrupt request of the external module, the interrupt request message input from the external module to the external module in the multi-port memory Storing the updated address value in an index register; generating an interrupt request signal through an interrupt request signal line with a control module; And reading out the interrupt request message stored in the address area by access and outputting the interrupt request message to the control module.

Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed descriptions of well-known functions or configurations will be omitted if it is determined that the detailed description of the present invention may unnecessarily obscure the subject matter of the present invention. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.

Hereinafter, a method for interfacing a control module and an external module with a register bank in a communication system will be described.

2 illustrates an interface device between a control module and an external module in a communication system according to an embodiment of the present invention.

As illustrated, the interface device according to the present invention includes a control module 200, a register bank 202, and a plurality of external modules 204-1 to 204-3. Here, it is assumed that there are three external modules 204-1 to 204-3. On the other hand, the register bank 202 includes a management logic (212), a multi-port memory (222) and an index register (232). In particular, the management logic 121 is a control signal necessary for the control module 200 and the external module 204 as well as logic for writing and reading data to the multi-port memory 222 and the index register 232. It can be configured to include logic to generate (eg IRQ signal).

In general, since the operation of processing an interrupt request includes both an operation of transferring data from an external module to a control module and an operation of transferring data from the control module to an external module, the following description is provided for an interrupt request generated from an external module. Let's take a look at the operation processing the.

Referring to FIG. 2, when an interrupt request is required, the corresponding external module 204 outputs a status (interrupt occurrence status) signal to a control signal bus and outputs an interrupt request message to a data bus. . Then, the register bank 202 recognizes a status signal input from the control signal bus and stores an interrupt request message input from the data bus in the multiport memory 222. At this time, the interrupt request message is stored in a unique address area allocated for the external module 204.

At this time, the address where the interrupt request message is recorded is updated in the index register 232. For example, the corresponding address value itself may be updated in the index register 232. Alternatively, the index register 232 may be configured as a bitmap to set a bit flag corresponding to the corresponding address. As such, when the interrupt register 232 is updated, the management logic 212 generates an interrupt request (IRQ) signal to the control module 200.

When the interrupt request signal is received, the control module 200 generates a chip selection (CS) signal to the register bank 202 to access the index register 232. In addition, the control module 200 determines whether an access right is currently granted to the control module 200. When the access right is granted, the control module 200 accesses the index register 232 and checks the external module 204 that requested the interrupt.

The control module 200 reads the interrupt request message by accessing the address recorded in the index register 232, and analyzes the read interrupt request message to confirm the state or request of the external module 204. After that process is executed.

In addition, when there are a plurality of control modules, the plurality of control modules have priority to access the register bank 202, which is performed by the management logic 212 of the register bank 202. . In other words, the management logic 212 determines the priority of the control modules, and grants access to the control module that currently has priority.

If control data (eg, interrupt processing result data) to be transmitted to the external module 204 exists after the interrupt request processing, the control module 200 outputs the control data to be transmitted to the external module 204 on a data bus. The address on which the control data is to be written is output to the address bus.

Then, the register bank 202 writes control data input through the data bus into an address area (multi-port memory) input through the address bus. That is, the control data is stored in a unique address area allocated for the external module 204. Thereafter, the management logic 202 of the register bank 202 outputs a control signal for requesting data reading to the external module 204.

On the other hand, the external module 204 receiving the control signal for requesting the data read access the address assigned to itself in the multi-port memory 222 reads the control data transmitted from the control module 200, The read control data is analyzed to perform a corresponding process.

As described above, the present invention configures the interface between the control module and the external module through a memory (register bank), so that the hardware can be flexibly changed in the case where no response is required or more memory should be allocated. Although not described in detail, since the external modules 204-1 to 204-3 are connected to a common bus, the management logic 212 registers the external modules 204-1 to 204-3. Bank 202 includes logic for arbitrating access.

3 illustrates an interrupt request processing procedure of a register bank according to an embodiment of the present invention.

Referring to FIG. 3, the register bank 202 first checks whether an interrupt request status signal is input from the external module 204 in step 301. When the interrupt request status signal is input, the register bank 202 proceeds to step 303 in which an interrupt request message input from the external module 204 through the data bus is assigned to the external module 204. Save to the area.

In this case, the register bank 202 records the address where the interrupt request message is recorded in the index register 232 in step 305. This update operation of the index register 232 is performed by the management logic 212 of the register bank 202.

The register bank 202 generates an interrupt request (IRQ) to the control module 202 by updating the index register 232 in step 307. In step 309, the register bank 202 reads the interrupt request message from the memory address by the access of the control module 202 and outputs the interrupt request message to the control module 200 through a data bus.

The register bank 202 allocates the control data (interrupt processing result data) input through the data bus by the access of the control module 202 to the external module 204 in step 311. Store at the address.

After storing the control data, the register bank 202 outputs a data read request to the external module 204 through a control signal bus in step 313. In operation 315, the register bank 202 reads the control data from the memory address by the access of the external module 204 and outputs the control data to the external module 204 through a data bus.

4 illustrates an interrupt processing procedure of a control module according to an embodiment of the present invention.

Referring to FIG. 4, the control module 200 first checks whether an interrupt request (IRQ) signal is input from the register bank 202 in step 401. Upon detecting the interrupt request signal, the control module 200 generates a chip select (CS) signal to the register bank 202 in step 403, and determines whether there is an access right to the register bank 202. The access rights are granted in the register bank 202 as described above.

If there is the access right, the control module 200 checks the updated address (address) by accessing the index register 232 of the register bank 202 in step 405. In operation 407, the control module 200 accesses the obtained address and reads the interrupt request message generated by the external module 204.

After reading the interrupt request message, the control module 200 executes an interrupt processing routine in response to the interrupt request message in step 409, and executes the result and control data through the data bus in step 411. 202).

5 illustrates an interrupt processing procedure of an external module according to an embodiment of the present invention.

Referring to FIG. 5, the external module 204 first checks whether an interrupt occurs in step 501. When the interrupt occurs, the external module 204 generates an interrupt request status signal to the register bank 202 through a control signal bus in step 503. In operation 505, the external module 204 generates an interrupt request message to the register bank 202 through the data bus.

In step 507, the external module 204 checks whether a data read request signal is input through the control signal bus. When the data read request signal is input, the external module 204 reads the control data generated by the control module 200 by accessing a corresponding address of the register bank 202 in step 509. In step 511, the external module 204 performs a corresponding process corresponding to the control data.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

As described above, the present invention has a merit that the signal processing structure can be simplified more easily and the software load can be reduced in an apparatus in which a plurality of control modules control an external module. In addition, the number of external module interrupts exceeding the interrupt port provided by the control module can be processed. In addition, the control module interfaces with only one bus form with a register bank regardless of which bus structure module is connected to the outside, thereby making it possible to consistently and simply write software.

Claims (10)

In an interface device between a control module and an external module in a communication system, A multi-port memory for storing data exchanged between the control module and the plurality of external modules in a unique address area of the corresponding external module; An index register for recording an update address value of the multiport memory; And a management logic for controlling access of the multi-port memory and the index register of the control module and the plurality of external modules. The method of claim 1, And when there are a plurality of control modules, the management logic controls access priority of the plurality of control modules. The method of claim 1, An interrupt request (IRQ) signal line is connected between the control module and the management logic. When an interrupt request message is written to the multiport memory, the management logic generates an interrupt request signal to the control module. Device characterized in that. The method of claim 1, Upon receiving the interrupt request signal from the management logic, the control module checks the updated address by accessing the index register, and reads the interrupt request message generated by an external module by accessing the confirmed address. . The method of claim 1, And the index register comprises a bitmap, and bit flags constituting the bitmap are mapped one-to-one with address regions of the multiport memory. In the signal processing method in the interface device between the control module and the external module, When the interrupt request is detected by an external module, storing an interrupt request message input from the external module in a unique address area allocated for the external module in the multiport memory; Writing the updated address value to an index register; Generating an interrupt request signal through an interrupt request signal line with the control module; Reading out the interrupt request message stored in the address area by the access of the control module and outputting the interrupt request message to the control module. The method of claim 6, Storing interrupt processing result data from the control module in the address area by access of the control module; Generating a data read request to the external module; And reading out the interrupt processing result data from the address area by accessing the external module and outputting the interrupt processing result data to the external module. The method of claim 6, Determining the priority of the control module and granting the access right according to the determined priority when the access of the control module is detected. The method of claim 6, The control module detecting the interrupt request signal checks the updated address by accessing the index register, and reads the interrupt request message generated by an external module by accessing the confirmed address. The method of claim 6, And the index register comprises a bitmap, and bit flags constituting the bitmap are mapped one-to-one with address regions of the multiport memory.

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