KR20070049778A - Method for manufacturing of cmos image sensor - Google Patents

Abstract

The present invention relates to a method for manufacturing a CMOS image sensor that simplifies the process and improves the sensitivity of the image sensor, comprising the steps of: forming an isolation layer on a semiconductor substrate defined by a salicide region and an egg salicide region; Forming a transistor comprising a gate electrode and a source / drain impurity region in the salicide region and the egg salicide region of the substrate, forming a salicide barrier layer in the egg salicide region of the semiconductor substrate; Forming a metal silicide film on the surface of the gate electrode and the source / drain impurity region formed in the silicide region, forming a barrier layer on the entire surface of the semiconductor substrate including the metal silicide film, and forming an interlayer insulating film on the entire surface of the semiconductor substrate. Forming, and the egg flesh A gate electrode and a metal silicide film, the surface of the salicide region of the side area to the C ₄ F ₈ and CHF ₃ gas so as to expose a predetermined portion of the main reaction gas the interlayer insulating film, the barrier layer, making use of the side barrier layer at the same time, by selectively removing the contact And forming a hole.

CMOS image sensor, salicide, contact hole, etch selectivity, USG

Description

Method for manufacturing of CMOS image sensor

1 is an equivalent circuit diagram of one pixel of a general CMOS image sensor

2 is a layout view of one pixel of a general CMOS image sensor

3A to 3E are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

4A to 4D are cross-sectional views illustrating a method of manufacturing the CMOS image sensor according to the present invention.

Explanation of symbols for the main parts of the drawings

101 semiconductor substrate 102 device isolation film

103: gate insulating film 104: gate electrode

105: insulating film sidewall 107: TEOS film

108: metal silicide film 109: USG film

110: interlayer insulating film 111: photosensitive film

112: contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary metal oxide silicon (CMOS) image sensor, and more particularly to a method of manufacturing a CMOS image sensor to simplify the process and improve the sensitivity of the image sensor.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a charge coupled device (CCD) and a CMOS image sensor. .

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required.

In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog-to-digital conversion circuit (A / D converter), and the like into a charge coupling device chip, which makes it difficult to downsize the product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device.

The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output.

That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages such as relatively low power consumption, a simple manufacturing process with a relatively small number of photo process steps, and the like.

In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization.

Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors.

Here, the equivalent circuit and the layout (lay-out) of the unit pixel of the 3T type CMOS image sensor will be described.

FIG. 1 is an equivalent circuit diagram of a general 3T CMOS image sensor, and FIG. 2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

As shown in FIG. 1, a unit pixel of a general 3T CMOS image sensor includes one photodiode (PD) and three nMOS transistors T1, T2, and T3.

The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.

The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply line supplied with a reference voltage VR, and the gate of the first nMOS transistor T1 has a reset signal RST. It is connected to the reset line supplied.

Further, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, the drain of the third nMOS transistor T3 is connected to a read circuit (not shown in the drawing) via a signal line, The gate of the third nMOS transistor T3 is connected to a column select line to which a selection signal SLCT is supplied.

Here, the first nMOS transistor T1 is a reset transistor Rx for resetting photocharges collected in the photodiode PD, and the second nMOS transistor T2 is a source follower buffer amplifier. A source floor transistor Dx acting as a buffer amplifier, and the third nMOS transistor T3 is a selection transistor Sx capable of addressing as a switching role.

Meanwhile, a part of the reset transistor Rx including the photodiode PD is an non-salicide region, and the other part is a salicide region.

As shown in FIG. 2, in the unit pixel of a general 3T CMOS image sensor, an active region 10 is defined so that one photodiode 20 is formed in a wide portion of the active region 10. Gate electrodes 30, 40, and 50 of three transistors are formed in the active region 10 of the remaining portion, respectively.

That is, a reset transistor Rx is formed by the gate electrode 30, a source floor transistor Dx is formed by the gate electrode 40, and a selection transistor Sx is formed by the gate electrode 50. Is formed.

Here, impurity ions are implanted into the active region 10 of each transistor except for the lower portion of each gate electrode 30, 40, 50 to form a source / drain region of each transistor.

Accordingly, a power supply voltage Vdd is applied to a source / drain region between the reset transistor Rx and the source floor transistor Dx, and a source / drain region on one side of the select transistor Sx is a read circuit (not shown). Not shown).

Although not shown in the drawing, each of the gate electrodes 30, 40, and 50 described above is connected to each signal line, and each signal line is connected to an external driving circuit having a pad at one end thereof.

3A to 3E are schematic process cross-sectional views showing a method of manufacturing a CMOS image sensor according to the prior art.

As shown in FIG. 3A, the device isolation film 62 is formed in the semiconductor substrate 61 defined by the salicide region and the egg salicide region.

 In addition, the gate insulating layer 63 and the conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire surface of the semiconductor substrate 61 on which the device isolation layer 62 is formed, and optionally the conductive layer and the gate insulating layer ( 63), the gate electrode 64 is formed in the salicide region and the egg salicide region, respectively.

The gate insulating layer 63 may be formed by a thermal oxidation process or may be formed by CVD.

Next, an insulating film is formed on the entire surface of the semiconductor substrate 61 including the gate electrode 64, and an etch back process is performed on the entire surface to form insulating film sidewalls 65 on both sides of the gate electrode 64.

The source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 61 by using the gate electrode 64 and the insulating film sidewall 65 as a mask, so that the surface of the semiconductor substrate 61 on both sides of the gate electrode 64 is implanted. The source / drain impurity region 66 is formed in the inside.

Meanwhile, an LDD region may be formed in the surface of the semiconductor substrate 61 on both sides of the gate electrode 64 before forming the insulating film sidewall 65.

As shown in FIG. 3B, a TEOS film 67 is formed on the entire surface of the semiconductor substrate 61 including the gate electrode 64 and formed in the salicide region so as to remain only in the salicide region through photo and etching processes. The TEOS film 67 is selectively removed.

Here, the TEOS film 67 remaining in the egg salicide region serves to mask the egg salicide region when forming a metal salicide film in the salicide region.

Subsequently, a high melting point metal film is deposited on the entire surface of the semiconductor substrate 61, and a salicide process is performed to react silicon and metal of the gate electrode 64 and the source / drain impurity region 66 formed in the salicide region. A metal salicide film 68 is formed.

Subsequently, a silicon nitride (SiN) film 69 is formed as a barrier layer on the entire surface of the semiconductor substrate 61 including the gate electrode 64.

As shown in FIG. 3C, an interlayer insulating film 70 is formed on the entire surface of the semiconductor substrate 61, the first photosensitive film 71 is coated on the interlayer insulating film 70, and then exposed and developed. The first photoresist layer 71 is selectively patterned.

Next, the patterned first photoresist layer 71 is used as a mask to selectively pattern the gate electrode 64 formed in the salicide region and the interlayer insulating layer 70 formed on the source / drain impurity region 66. The first contact hole 72 is formed.

When the first contact hole 72 is formed, CO, which is a polymer gas, is added to etch the interlayer insulating layer 70.

As shown in FIG. 3D, the first photosensitive film 71 is removed, the second photosensitive film 73 is applied to the entire surface of the semiconductor substrate 61, and then the second photosensitive film 73 is exposed and developed. ) Is optionally patterned.

Subsequently, the second contact hole 74 is formed by selectively removing the interlayer insulating layer 70 on the gate electrode 64 formed in the egg salicide region using the patterned second photoresist layer 73 as a mask. .

When the second contact hole 74 is formed, CO, which is a polymer gas, is added to etch the interlayer insulating layer 70.

As shown in FIG. 3E, the second photoresist layer 73 is removed and the barrier layer under the first and second contact holes 72 and 74 is used by using the interlayer insulating layer 70 as a mask. The silicon nitride film 69 and the TEOS film 67 are selectively removed.

However, the manufacturing method of the CMOS image sensor according to the prior art as described above has the following problems.

That is, when forming the contact hole, as the selectivity of the contact portion is increased, CO, which is a polymer gas, is added, which has a restriction on its use as a harmful rider.

In addition, in the case of the egg salicide region, since the TEOS film (salicide prevention layer) exists under the barrier layer, the process is performed by forming a contact hole through a separate etching process by different masks of the egg salicide region and the salicide region. Complex.

In addition, in the case of an image sensor, a silicon nitride film having a high dielectric constant is used as a barrier layer, resulting in deterioration of optical characteristics.

The present invention is to solve the above-mentioned problems, environmentally friendly by improving the etch selectivity of the gate electrode and the salicide layer, while increasing the process margin, while simultaneously etching the salicide region and the egg salicide region at the same time contact hole The purpose of the present invention is to provide a method for manufacturing CMOS image sensor to reduce the number of processes by reducing the cost and to prevent degradation of optical characteristics of the image sensor.

In addition, an object of the present invention is to provide a method for manufacturing a CMOS image sensor to prevent degradation of the optical properties of the image sensor.

The method for manufacturing the CMOS image sensor according to the present invention for achieving the above object comprises the steps of forming an isolation layer on a semiconductor substrate defined by a salicide region and an egg salicide region, and a salicide region of the semiconductor substrate; Forming a transistor comprising a gate electrode and a source / drain impurity region in the egg salicide region, forming a salicide barrier layer in the egg salicide region of the semiconductor substrate, and forming a gate electrode in the silicide region of the semiconductor substrate And forming a metal silicide film on the surface of the source / drain impurity region, forming a barrier layer on the entire surface of the semiconductor substrate including the metal silicide film, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and I gate electrode of the salicide region Salicylate and a metal silicide film, the surface of the side region at the same time, selectively removing the interlayer insulating film, the barrier layer, the side layer raised to the C ₄ F ₈ and CHF ₃ gas as a main reaction gas so as to expose a predetermined portion forming a contact hole, It is characterized by including the formation.

Hereinafter, a method of manufacturing the CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

4A to 4D are schematic cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the present invention.

As shown in FIG. 4A, the device isolation film 102 is formed in the semiconductor substrate 101 defined by the salicide region and the egg salicide region.

Although not shown in the drawings, a method of forming the device isolation layer 102 will be described below.

First, a pad oxide film, a pad nitride film, and a TEOS (Tetra Ethyl Ortho Silicate) oxide film are sequentially formed on a semiconductor substrate, and a photoresist film is formed on the TEOS oxide film.

Subsequently, the photoresist is exposed and developed using a mask defining an active region and a device isolation region to pattern the photoresist. At this time, the photoresist of the device isolation region is removed.

The pad oxide film, the pad nitride film and the TEOS oxide film of the device isolation region are selectively removed using the patterned photoresist as a mask.

Subsequently, the semiconductor substrate in the device isolation region is etched to a predetermined depth using the patterned pad oxide film, the pad nitride film, and the TEOS oxide film as a mask to form a trench. Then, all of the photosensitive film is removed.

Subsequently, a thin sacrificial oxide film is formed on the entire surface of the substrate on which the trench is formed, and an O ₃ TEOS film is formed on the substrate to fill the trench. In this case, the sacrificial oxide film is also formed on the inner wall of the trench, and the O ₃ TEOS film proceeds at a temperature of about 1000 ° C. or more.

Subsequently, the O ₃ TEOS film is removed on the entire surface of the semiconductor substrate so as to remain only in the trench region by a chemical mechanical polishing (CMP) process to form a device isolation layer 102 in the trench. Next, the pad oxide film, the pad nitride film, and the TEOS oxide film are removed.

 In addition, a gate insulating film 103 and a conductive layer (for example, a high concentration polycrystalline silicon layer) are sequentially deposited on the entire surface of the semiconductor substrate 101 on which the device isolation layer 102 is formed, and optionally the conductive layer and the gate insulating film ( 103 is removed to form gate electrodes 104 in the salicide region and the egg salicide region, respectively.

The gate insulating layer 103 may be formed by a thermal oxidation process or may be formed by a CVD method.

Next, an insulating film is formed on the entire surface of the semiconductor substrate 101 including the gate electrode 104, and an etch back process is performed on the entire surface to form the insulating film sidewall 105 on both sides of the gate electrode 104.

In addition, source / drain impurity ions are implanted into the entire surface of the semiconductor substrate 101 using the gate electrode 104 and the insulating film sidewall 105 as a mask, so that the surface of the semiconductor substrate 101 on both sides of the gate electrode 104 is implanted. Source / drain impurity regions 106 are formed in the trenches.

Meanwhile, an LDD region may be formed in the surface of the semiconductor substrate 101 on both sides of the gate electrode 104 before the insulating film sidewall 105 is formed.

As shown in FIG. 4B, the TEOS film 107 is formed on the entire surface of the semiconductor substrate 101 including the gate electrode 104, and formed in the salicide region so as to remain only in the salicide region through photo and etching processes. The TEOS film 107 is selectively removed.

Here, the TEOS film 107 remaining in the egg salicide region serves to mask the egg salicide region when forming a metal salicide film in the salicide region.

Subsequently, a high melting point metal film is deposited on the entire surface of the semiconductor substrate 101, and the metal is reacted with silicon in the gate electrode 104 and the source / drain impurity region 106 formed in the salicide region by performing a salicide process. The metal salicide film 108 is formed.

The high melting point metal film for forming the metal salicide film 108 may be Ti, Ta, Ni, Co, or the like.

Subsequently, a USG film 109 is formed on the entire surface of the semiconductor substrate 101 including the gate electrode 104 as a barrier layer to a thickness of 300 to 600 Å.

As shown in FIG. 4C, an interlayer insulating film 110 is formed on the entire surface of the semiconductor substrate 101, the photosensitive film 111 is coated on the interlayer insulating film 110, and then the photosensitive film is exposed and developed. Selectively pattern 111.

In this case, the interlayer insulating layer 110 uses TEOS, BPSG, or the like.

Subsequently, the interlayer insulating layer 110 may be exposed to a predetermined portion of the gate electrode 104 and the metal salicide layer 68 formed in the salicide region and the egg salicide region by using the patterned photoresist layer 111 as a mask. ), The USG film 109 and the TEOS film 107 are selectively removed to form the contact hole 112.

Here, when forming the contact hole 112 is formed using an etching gas of C ₄ F ₈ , CHF ₃ .

Meanwhile, the process for forming the contact hole 112 will be described in more detail as follows.

That is, 600 ~ 1400 W (source power ) / 600 ~ 1400 W (Bias power) / 3 ~ 12sccm C 4 F 8/4 ~ 15sccm CHF 3/200 ~ 300 sccm Ar / 10 ~ 30sccm N 2/2 ~ 10sccm O _{From the} results obtained in the range of 2/5 to 25 ° C., the main influence factor (variable) in the selectivity of the gate electrode 104, the metal salicide film 108, and the interlayer insulating film 110 is the bias power (Bias Power). ), And when the bias power proceeds to 1170W, a selectivity of 20 or more can be obtained regardless of other variables.

Based on these results, after confirming the profile of the contact hole 112 after etching the bias power at 1200 W, Ar 250 sccm, and temperature 20 ° C, the slope increases as the C ₄ F ₈ / CHF ₃ ratio increases. It can be seen.

The conditions for example in conditions of _{1000W / 1200W / 4sccm C 4 F} 8 / 5sccm CHF 3 / 300sccm Ar / 20sccm N 2 / 3sccm O 2/15 ℃ of are shown in Table 1 below.

Etching Speed (Å / min) Selectivity Poly-Si Ti-Salicide TEOS / BPSG TEOS / Poly-Si TEOS / Ti-Sal Measures 265 275 5645/7955 21 21

In addition, the contact hole 112 may be formed in two steps.

That is, primarily in the 1000 ~ 1400W (source power) / 800 ~ 1000W (Bias power) / 5 ~ 25sccm C 4 F 8/200 ~ 300sccm Ar / 10 ~ 30sccm N 2/2 ~ 10sccm O 2/15 ~ 25 ℃ after proceeding, 1000 ~ 1400W (source power) / 800 ~ 1000W (Bias power) / 3 ~ 12sccm C 4 F 8/4 ~ 20sccm CHF 3/200 ~ 300sccm Ar / 10 ~ 30sccm N 2/2 ~ 10sccm O 2 Proceed second to / 15 ~ 25 ℃ and simultaneously etch to the barrier layer.

As shown in FIG. 4D, the photosensitive film 111 is removed, and metal wirings are formed on the semiconductor substrate 101 using a conventional manufacturing process although not shown in the drawing.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The method of manufacturing the CMOS image sensor according to the present invention as described above has the following effects.

First, using C ₄ F ₈ , CHF ₃ etching gas without using CO gas can form a contact hole having a high apect ratio between each layer and no streaking .

Second, in manufacturing an image sensor, by using USG instead of SiN, which has a high refractive index, as a barrier layer, optical properties are improved and etching is performed at once to a poly-Si (or salicide) contact surface as an electrode. The process can be simplified.

Claims (5)

Forming an isolation layer in the semiconductor substrate defined by the salicide region and the egg salicide region; Forming a transistor including a gate electrode and a source / drain impurity region in a salicide region and an egg salicide region of the semiconductor substrate; Forming a salicide barrier layer in the egg salicide region of the semiconductor substrate; Forming a metal silicide film on surfaces of the gate electrode and the source / drain impurity region formed in the silicide region of the semiconductor substrate; Forming a barrier layer on an entire surface of the semiconductor substrate including the metal silicide layer; Forming an interlayer insulating film on the entire surface of the semiconductor substrate; The interlayer insulating film, the barrier layer, and the salicide prevention layer are selectively selected simultaneously using C ₄ F ₈ and CHF ₃ gas as the main reaction gases so that the gate electrode of the egg salicide region and the surface of the metal silicide film of the salicide region are partially exposed. And forming a contact hole by removing the contact hole. The method of claim 1, wherein the contact hole is 600 ~ 1400 W (source power) / 600 ~ 1400 W (Bias power) / 3 ~ 12sccm C 4 F 8/4 ~ 15sccm CHF 3/200 ~ 300sccm Ar / 10 ~ 30sccm _{N 2/2 ~ 10sccm O 2} / method of manufacturing a CMOS image sensor as to form in the range of 5 ~ 25 ℃. The method of claim 1, wherein the barrier layer comprises a USG film. The method of claim 1, wherein the barrier layer is formed to a thickness of about 300 to about 600 μs. The method of claim 1, wherein the contact hole is 1000 ~ 1400W (source power) / 800 ~ 1000W (Bias power) / 5 ~ 25sccm C 4 F 8/200 ~ 300Ar / 10 ~ 30sccm N 2/2 ~ 10sccm O 2 / Proceed first at 15 ~ 25 ℃, 1000 ~ 1400W (source power) / 800 ~ 1000W (Bias power) / 3 ~ 12sccm C ₄ F ₈ / 4 ~ 20sccm CHF ₃ / 200 ~ 300sccm Ar / 10 ~ 30sccm N 2/2 ~ 10sccm O 2 / A method of manufacturing a CMOS image sensor characterized in that the secondary to form at 15 ~ 25 ℃.

Images