KR20070044712A - Schottky barrier field effect transistor and manufacturing method at the same of - Google Patents

Abstract

The invention includes a substrate, a source and a drain formed by a Schottky barrier on the substrate, a gate dielectric layer surrounding the source and drain and formed on the substrate, and a gate formed on the gate dielectric layer. A schottky barrier field effect transistor and a manufacturing method thereof are proposed.

Nitride Semiconductors, Schottky Barriers, MOSFETs

Description

Schottky Barrier Field Effect Transistor and manufacturing method at the same of

1A to 1C are cross-sectional views, manufacturing process flow diagrams, and operation modes illustrating the configuration of a Schottky Barrier Field Effect Transistor (FET) according to an embodiment of the present invention, respectively.

2 is a cross-sectional view of a GaN semiconductor used as a substrate of a Schottky barrier FET according to an embodiment of the present invention.

3 is a graph illustrating output characteristics of a Schottky barrier FET according to an embodiment of the present invention.

4 is a graph showing transconductance characteristics of a Schottky barrier FET according to an embodiment of the present invention.

FIG. 5 is a graph showing the relationship between gate voltage (V _Gs ) and drain current (I _DS ) for various gate dielectrics and gate lengths in a Schottky barrier FET according to an embodiment through computer simulation of the present invention.

FIG. 6 is a graph illustrating a relationship between a work function of a gate electrode and a threshold voltage in a Schottky barrier FET according to an embodiment of the present invention.

FIG. 7 is a graph illustrating a change in maximum drain current according to a work function of a source / drain metal in a Schottky barrier FET according to an embodiment through computer simulation of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and does not require doping using a source / drain formed on a substrate as a schottky barrier, and normally off-type Schottky barrier with little power consumption in the standby state. A field effect transistor and a method of manufacturing the same.

Recently, GaN-based semiconductors are not only optical and light-receiving devices such as LEDs (Lighting Emitter Diodes), laser-diodes (LDs), and UV photodetectors, but also high-power high-frequency electronic devices such as hetero-structure field effect transistors (HFETs). It is also used as a prototype as well as an active research on the back.

This is because GaN-based semiconductors have a larger energy gap and higher saturation electron velocity than GaAs, which is widely known as a compound semiconductor, and have excellent characteristics in device operation speed and thermal stability, and also have excellent chemical stability.

In addition, the band discontinuity is large at the interface of the AlGaN / GaN heterojunction and the piezoelectric properties can increase the two-dimensional electron concentration by about 10 times higher than the heterojunction, and further increase the operation speed of the device. As a result, it is expected to be applied to high frequency and high output electronic devices.

However, in the case of HFETs, there is a problem that a relatively large gate leakage current and a risk of current collapse exist due to the AlGaN surface that is not passivated under the gate.

On the other hand, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) provide a normally-off mode transistor operation with lower gate leakage current, which simplifies the driving circuit and lowers power consumption. It is more desirable for applications in power devices and integrated circuits.

On the other hand, p-type doping using Mg, which is generally known in GaN-based semiconductors, exhibits a low hole density and a low hole mobility of typically 10 cm 2 / Vs or less. There was difficulty in growing p-type thin films.

In addition, it was difficult to obtain n-type doping with a p-type GaN layer to form a source and a drain.

Thus, despite its superior characteristics, GaN-based semiconductors are not considered to be desirable semiconductors for MOSFET implementation.

Attempts have been made to implement MOSFETs using GaN-based semiconductors.

Depletion type GaN MOSFETs using various gate dielectrics have a drawback in that they consume power in a normally-on state.

In addition, Irokawa et al. Published an enhancement type n-channel GaN MOSFET using Si ⁺ ion implantation for source / drain regions on Mg doped p-type GaN thin films. However, there is a disadvantage in this case showing only linear mode operation.

Matocha et al. Also announced a normal off-mode GaN MOSFET, which has the disadvantage of having a high leakage current of 2 × 10 ⁻⁷ A and a high threshold vo1tage of 2.7V.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and does not require doping using a source / drain formed on a substrate as a Schottky barrier, and has a Schottky barrier field effect transistor having little power consumption in the standby state. It aims at providing the manufacturing method.

In addition, using a silicon auto-doped p-type GaN layer grown on a silicon substrate, MOSFETs can be formed without the need for ion implantation and activation at temperatures above 1500 ° C, which can alleviate the DIBL problem present in CMOS technology. An object of the present invention is to provide a Schottky barrier field effect transistor and a method of manufacturing the same.

In order to achieve the above object, according to one aspect of the invention,

A Schottky barrier field effect comprising a substrate, a source and a drain formed on the substrate as a Schottky barrier, a gate dielectric layer surrounding the source and drain and formed on the substrate, and a gate formed on the gate dielectric layer Provide a transistor.

The substrate may be selected from any one of GaN, InN, AlN, SiC, InGaN, and AlGaN semiconductors.

The GaN semiconductor substrate may include a Si substrate, a buffer layer formed on the Si substrate, and an artificially undoped GaN layer formed on the buffer layer.

In addition, the buffer layer is characterized in that any one of AlN, GaN, AlGaN, or a combination thereof.

In addition, the source and drain are Ni, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi ₂ , WSi, PtSi, Ir, Zr, Ta, TaN, Cu, Ru, Co or a combination thereof.

In addition, the gate dielectric layer may include Sc ₂ O ₃ , AlN, Ga ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Gd ₂ O ₃ , Al _x Ga _{2 (1-x)} O ₃ , MgO Or a combination thereof.

In addition, the gate is characterized in that using Au.

In addition, the gate is characterized in that using polysilicon.

The schottky barrier may contact the p-type semiconductor substrate having a work function greater than the source and drain when the substrate is a p-type semiconductor, and the source and drain when the substrate is an n-type semiconductor. The n-type semiconductor substrate having a smaller work function than a source and a drain is formed in contact with the source and the drain.

According to another aspect of the invention,

An S / D process step of forming a source / drain as a Schottky barrier on a substrate, forming a gate dielectric layer on the substrate surrounding the source / drain, and a gate process step of forming a gate on the gate dielectric layer It provides a method of manufacturing a Schottky barrier field effect transistor comprising a.

The substrate may be selected from any one of GaN, InN, AlN, SiC, InGaN, and AlGaN semiconductors.

In addition, the source and drain are Ni, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi ₂ , WSi, PtSi, Ir, Zr, Ta, TaN, Cu, Ru, Co or a combination thereof.

In addition, the gate dielectric layer may include Sc ₂ O ₃ , AlN, Ga ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Gd ₂ O ₃ , Al _x Ga _{2 (1-x)} O ₃ , MgO Or a combination thereof.

In addition, the gate is characterized in that using Au.

In addition, the gate is characterized in that using polysilicon.

The method may further include cleaning the substrate before the S / D process and contact opening after the gate process.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to components of each drawing, the same components are denoted by the same reference numerals as much as possible even though they are shown in different drawings. Note that you have to have.

1A to 1C are cross-sectional views showing the configuration of the Schottky Barrier FET 100 according to an embodiment of the present invention, a manufacturing process flowchart, and an operation mode, respectively.

As shown in FIG. 1A, the Schottky barrier FET 100 according to an embodiment of the present invention includes an n-type Si substrate 110 and a buffer layer 120 formed on the n-type Si substrate 110. And an artificially undoped GaN layer 130 formed on the buffer layer 120, a source and a drain 140 formed on both sides of the GaN layer 130, and the source and drain. The gate dielectric layer 150 is formed on the GaN layer 130 and surrounds the 140, and the gate electrode 160 is formed on the gate dielectric layer 150.

Here, the Si substrate 110 is preferable as a substrate of a GaN-based semiconductor because of its low cost, large area availability, and usefulness of implementing an OptoElectronic Integrated Circuit (OEIC) in combination with a well grown Si process.

When the GaN layer is grown on a Si substrate, compared with the conventional growth of the GaN layer on a sapphire or SiC substrate, the crystallinity of the grown GaN layer is not good, which is due to the difference in thermal expansion coefficient between the Si substrate and the GaN layer. Because of the size.

As a result, large tensile strains generated while cooling the growth temperature at high temperatures may cause cracks in the epitaxial layer.

In order to prevent the occurrence of such cracks, the GaN layer 130 which is not artificially doped on the n-type Si substrate 110 is grown using the buffer layer 120. p-type conduction).

Subsequently, 1000 μm thick aluminum (Al) is deposited on the GaN layer 130 as the source and drain 140. The work function of the aluminum layer is 4.3 eV, which is similar to the electron affinity of GaN.

In this case, the current characteristics according to the contact between the source and drain 140 and the GaN layer 130, that is, the contact between the metal and the p-type semiconductor are as follows.

That is, when the GaN layer (p-type semiconductor) having a larger work function than the metal (aluminum) used as the source and drain 140 is in contact with the metal, electrons are metal (source or drain) because the Fermi level on the metal side is high. To the semiconductor (GaN) layer.

The energy barrier at this time becomes a Schottky barrier for holes.

Accordingly, an n-channel enhancement field effect transistor can be implemented without using n-type doping using the source and drain 140 as a schottky barrier.

In addition, a gate dielectric layer 150 surrounding the source and drain 140 and surrounding the GaN layer 130 is deposited to a thickness of 200 Å.

Finally, gold (Au) having a thickness of 1000 Å is deposited on the gate dielectric layer 150 to the gate electrode 160.

The gate dielectric layer 150, which is an intermediate layer, electrically insulates the gate electrode 160, which is a metal, from the GaN layer 130.

As described above, the n-channel increased FET in the Schottky barrier FET 100 according to the embodiment of the present invention has been described. Contacting a metal forms a Schottky barrier for electrons to implement a p-channel increased field effect transistor.

Looking at the manufacturing process of the Schottky barrier FET 100 according to an embodiment of the present invention with reference to Figure 1b in more detail as follows.

Initial cleaning is performed to clean the deposition surface of the GaN layer 130 serving as the substrate (S110).

Here, although p-type GaN semiconductors are used to implement n-channel FETs, p-type semiconductor substrates or n-type semiconductor substrates may be used according to whether n-channel or p-channel is used.

In addition, an InN, AlN, SiC, InGaN, AlGaN semiconductor, or the like may be used as the substrate.

Thereafter, S / D metallization for source / drain formation is performed on the GaN layer 130 (S120).

Here, the S / D metal process deposits 1000 Å thick Al on a p-type semiconductor substrate such as the GaN layer 130, and the deposited Al layer forms a Schottky barrier with a source / drain 140. .

In addition, the material of the source / drain may be Ni, Ti, TiN, Pt, Au, RuO ₂ , V, Ni, W, WN, Hf, HfN, Mo, NiSi, CoSi ₂ , WSi, PtSi, Ir, in addition to Al. Zr, Ta, TaN, Cu, Ru, Co or combinations thereof.

Thereafter, a deposition process is performed to surround the source / drain 140 and deposit the gate dielectric layer 150 on the GaN layer 130 to a thickness of 200 μs (S130).

Here, the gate dielectric layer 150 is a gate insulating film that insulates the gate electrode 160 formed on the upper portion and the GaN layer 130 formed on the lower portion, and the material is Sc ₂ O ₃ , AlN, Ga ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Gd ₂ O ₃ , Al _x Ga _{2 (1-x)} O ₃ , MgO, or a combination thereof.

Subsequently, a gate metallization process for depositing gold (Au) having a thickness of 1000 Å to the gate electrode 160 is performed on the gate dielectric layer 150 (S140).

In addition, when the polysilicon is used as the gate electrode, the threshold voltage may be adjusted according to the doping concentration of the polysilicon, unlike a metal having a work function determined.

Thereafter, a contact open process is performed to apply power to the source and drain (S150).

Referring to Figure 1c, the operation mode (operation mode) of the Schottky barrier FET 100 according to an embodiment of the present invention will be described.

In general, the structure of the FET defines a region (n ⁺ , p ⁺ ) of higher concentration than the substrate on the left and right around the gate region, and when the current flows due to the potential difference between the two regions, the source, the source, Set the outlet to drain.

Here, the contact between the source and drain (metal) and the substrate (semiconductor) according to the present invention serves as a Schottky barrier showing a rectifying characteristic in which a large current flows in the forward bias but little current flows in the reverse bias. Perform.

Thus, i) V _GS = V _DS = 0, where the n-type field effect transistor is cut off.

ii) Increasing V _GS further creates an inversion layer where many electrons gather on the substrate surface under the gate and change this to n-type, creating a channel. The voltage at this time is the threshold voltage V _T.

Here, the case of V _GS > V _T , V _DS = 0, where a channel is formed by forming an inversion layer in which the surface of the original p-type is changed to n-type, and a minute current starts to flow through the channel (Channel inversion). .

iii) V _GS > V _T , V _DS = 0. When V _DS has a positive voltage, the current flowing along the channel increases linearly with the increase of V _{DS with} the FET on. linear region, the pinch-off state, the drain current remains almost constant even if V _DS increases.

Conventional GaN-based semiconductors have not been well utilized in MOSFETs despite their excellence. Hereinafter, an example of implementing an n-channel FET using a GaN-based semiconductor as a substrate of the Schottky barrier FET according to the present invention. This will be described with reference to FIG. 2.

2 is a cross-sectional view of a GaN semiconductor used as a substrate of a Schottky barrier FET in accordance with a preferred embodiment of the present invention.

Referring to FIG. 2, first, etching is performed using dilute BOE (6: 1) to remove the native oxide film on the Si substrate 110.

Here, in the case of using a GaN-based semiconductor, it is possible to grow a nitride semiconductor on a SiC, sapphire, Si substrate, Si substrate is preferable because of the low cost, large area implementation can be utilized a lot.

Thereafter, Al pretreatment is performed after in-situ cleaning of the Si substrate in a chamber at 1050 ° C. and H ₂ atmosphere.

Subsequently, at 1060 ° C., the buffer layer 120 is grown by MOCVD (Metal Organic Chemical Vapor Deposition), and the gallium nitride layer (uid-GaN) 130 which is not artificially doped on the buffer layer 120 is grown. Let's do it.

Here, TMGa (TriMethylGallium) is used as the Ga source, NH ₃ is used as the N source, and H ₂ is used as the carrier gas.

The buffer layer 120 may be formed of any one of aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (Al _X Ga _1-x N), or a combination thereof.

In addition, aluminum arsenide (AlAs), gallium arsenide (GaAs) and the like may also be used.

In addition, the buffer layer 120 may be a single structure (multi-layer buffer) or a single structure (multi-layer buffer), the thickness of the buffer layer in a single structure is preferably in the range of 20 ~ 30nm.

In addition, the grown GaN layer 130 is a thin film without cracks having a thickness of 1.5 μm.

In addition, the pressure of the chamber is maintained at 50 torr during the entire epitaxial layer growth, and the buffer layer 120 in the range of 1050 to 1060 ° C. is grown on the Si substrate.

Here, during epitaxial layer growth on the Si substrate 110, Si is n-type dopant by out-diffusion or auto-doping from the substrate surface into the GaN layer 130. Act as a source

Further, from the Hall measurement data, unlike the normal growth conditions in which the conductivity type of the GaN layer on the silicon substrate is determined to be n-type, the buffer layer 120 on the n-type Si substrate 110 according to the present invention. The artificially undoped gallium nitride layer 130 formed by using the P-type conduction exhibits a very high hole mobility, that is, 65 cm 2 / Vs.

In other words, Si atoms diffused from the n-type Si substrate 110 form SiN in GaN / Si having a tensile strain to act as an acceptor.

3 to 7 are graphs showing the characteristics of the Schottky barrier FET according to an embodiment of the present invention.

3 is a graph illustrating output characteristics of a Schottky barrier FET according to an embodiment of the present invention.

Referring to FIG. 3, the Schottky barrier FET according to an embodiment of the present invention has a gate length L of 10 μm and a gate width W of 30 μm, that is, an aspect ratio W / L. The output characteristic of the output voltage (V _DS ) -output current (I _DS ) relationship can be seen for the form of 3.

Here, as the output voltage V _DS increases, the output current I _DS also increases linearly (linear region), but the output current becomes substantially constant even if the output voltage increases above a predetermined output voltage (saturation region). ).

In addition, while the gate voltage V _Gs was measured in units of 0.5 V within the range of 0 to 3 V, it can be seen that as the gate voltage V _Gs increases, the output current also increases in the saturation region.

4 is a graph showing transconductance characteristics of a Schottky barrier FET according to an embodiment of the present invention.

That is, FIG. 4 shows a drain current that is an output current with respect to a gate voltage V _Gs which is an input voltage of a Schottky barrier FET having an output voltage V _DS of 5 V and an aspect ratio W / L = 10 μm / 10 μm = 1. (I _DS ) shows the transfer characteristics.

Here, the dotted line is a graph showing the simulation result, and the solid line is a graph showing the result of the actual FET, and the difference between them is related to the non-ideal Schottky barrier of the source contact due to the interface state.

When the output voltage V _DS is 5V, the maximum drain current I _DS is 3 mA / mm or more, and the maximum transconductance g _m is 1.6 mS / mm. These results represent the highest values ever known and reported for GaN-based MISFETs.

The high transconductance of the FET is due to the high electron mobility of the channel because silicon ions do not act as important scattering centers, such as inert Mg and Mg ions, in Mg-doped GaN where p-type impurities are replaced with nitrogen atoms. .

FIG. 5 is a graph showing the relationship between gate voltage (V _Gs ) and drain current (I _DS ) for various gate dielectrics and gate lengths in a Schottky barrier FET according to an embodiment through computer simulation of the present invention.

As shown in FIG. 5, the Schottky barrier FET according to the present invention has an off-current of about ㎁, which is much smaller than that of a general GaN HFET, so that there is little power consumption in the standby state (V _G = 0). Normal off-type FETs can be implemented.

In addition, the maximum drain current (on-current) can be implemented to the maximum output current characteristics of several to several tens of mA / mm level.

Leakage currents are typically due to GaN surfaces that are not well passivated under PECVD SiO ₂ , which can improve the device performance of FETs if good gate dielectrics are applied.

That is, referring to FIG. 5, when the thin high-k gate dielectric Al ₂ O ₃ is applied and the short gate length L _g (1 μm) is implemented, the drain current may be increased. It can be seen.

FIG. 6 is a graph illustrating a relationship between a work function of a gate electrode and a threshold voltage in a Schottky barrier FET according to an embodiment of the present invention.

Referring to FIG. 6, it can be seen that by selecting a gate electrode having another work function in the range of 4 to 6 eV, the threshold voltage can be adjusted in the range of 0.58 to 2.24V.

In addition, when polysilicon is used as the gate electrode, the threshold voltage may be adjusted within a range of 0.6 to 1.6V (see hatched square in FIG. 6).

For example, when the threshold voltage is relatively high, the leakage current can be reduced to lower the off-current. On the other hand, when the threshold voltage is relatively low, the off current is increased to the blocking current, and the on-current is also increased. Increases.

FIG. 7 is a graph illustrating a change in maximum drain current according to a work function of a source / drain metal in a Schottky barrier FET according to an embodiment through computer simulation of the present invention.

Referring to FIG. 7, it has a maximum drain current when V _DS = V _GS = 5V (see FIG. 6). The maximum current drain current depends on the work function of the source / drain metal. For the GaN n-channel Schottky barrier FET, the work function of the metal should be lower than 4.3 eV, indicating that the maximum on current is in good condition.

In the above, as the Schottky barrier FET according to an embodiment of the present invention, the n-channel increase type FET using a p-type GaN semiconductor substrate has been mainly described, but is not limited thereto. That is, the p-channel increased FET and the Schottky barrier may be applied to various types of FETs (field effect transistors) that implement the contact of the source / drain substrate with the contact of the metal-semiconductor or the metal compound-substrate.

Therefore, the present invention is not limited to the above-described embodiments, and a person having ordinary skill in the art may change the design or avoid the design without departing from the scope of the technical idea of the present invention. Will be in range.

As described above, the Schottky barrier FET and a method of manufacturing the same according to the present invention do not require a separate doping process by using a source / drain formed on the substrate as a Schottky barrier, and in the standby state, a blocking current At this level, it is possible to provide a normal off-FET with little power consumption.

In addition, the use of GaN semiconductors (a silicon auto-doped p-type GaN layer grown on a silicon substrate) as the substrate of the FET can maximize the use of high-power, high-frequency electronic devices.

In addition, the ion implantation of the GaN semiconductor and the activation process at 1500 ° C or higher can be eliminated, thereby simplifying and facilitating the manufacturing process.

It also helps to alleviate the DIBL problem seen in CMOS technology.

In addition, when Si is used as the substrate, it is possible to flexibly adapt to the trend of larger semiconductors and to implement it at low cost.

Claims (16)

Substrate, Source and drain formed on the substrate as a Schottky barrier; A gate dielectric layer surrounding the source and drain and formed on the substrate; And a gate formed over said gate dielectric layer. The method of claim 1, The substrate is a Schottky barrier field effect transistor, characterized in that selected from any one of GaN, InN, AlN, SiC, InGaN, AlGaN semiconductor. The method of claim 2, And said GaN semiconductor substrate comprises a Si substrate, a buffer layer formed on said Si substrate, and an artificially undoped GaN layer formed on said buffer layer. The method of claim 3, The buffer layer is any one of AlN, GaN, AlGaN, or a combination thereof. The method of claim 1, The source and drain are Ni, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi ₂ , WSi, PtSi, Ir, Zr, Ta, TaN, Cu, Schottky barrier field effect transistor, characterized in that selected from Ru, Co or a combination thereof. The method of claim 1, The gate dielectric layer may include Sc ₂ O ₃ , AlN, Ga ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Gd ₂ O ₃ , Al _x Ga _{2 (1-x)} O ₃ , MgO, or A Schottky barrier field effect transistor selected from any one of combinations. The method of claim 1, Schottky barrier field effect transistor, characterized in that the gate using Au. The method of claim 1, And said gate uses polysilicon. The method of claim 1, The Schottky barrier is When the substrate is a p-type semiconductor, the p-type semiconductor substrate having a larger work function than the source and drain contact the source and drain, And wherein the n-type semiconductor substrate having a work function smaller than the source and drain is in contact with the source and drain when the substrate is an n-type semiconductor. An S / D process step of forming a source / drain as a Schottky barrier on the substrate, Forming a gate dielectric layer on the substrate surrounding the source / drain; And a gate process step of forming a gate on said gate dielectric layer. The method of claim 10, And said substrate is selected from one of GaN, InN, AlN, SiC, InGaN, and AlGaN semiconductors. The method of claim 10, The source and drain are Ni, Ti, TiN, Pt, Au, RuO ₂ , V, W, WN, Hf, HfN, Mo, NiSi, CoSi ₂ , WSi, PtSi, Ir, Zr, Ta, TaN, Cu, A method for manufacturing a Schottky barrier field effect transistor, characterized in that it is selected from Ru, Co or a combination thereof. The method of claim 10, The gate dielectric layer may include Sc ₂ O ₃ , AlN, Ga ₂ O ₃ , SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , Gd ₂ O ₃ , Al _x Ga _{2 (1-x)} O ₃ , MgO, or A method for manufacturing a Schottky barrier field effect transistor, characterized in that selected from any one of combinations. The method of claim 10, The gate is a method of manufacturing a Schottky barrier field effect transistor, characterized in that using Au. The method of claim 10, The gate is a method of manufacturing a Schottky barrier field effect transistor using polysilicon. The method of claim 10, And cleaning the substrate before the S / D process and contacting the gate after the gate process.

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