KR20070038192A - Thin film transistor array substrate and liquid crystal display device having the same - Google Patents

Abstract

Disclosed are a TFT substrate capable of reducing power consumption and a liquid crystal display device having the same. The display unit is divided into a first display area and a second display area. The first driving circuit unit is formed in a periphery adjacent to the first display area to provide a first gate signal to the first display area. The second driving circuit unit is formed at a periphery adjacent to the second display area to provide a second gate signal to the second display area. According to such a TFT substrate and a liquid crystal display device having the same, power consumption of the liquid crystal display device can be reduced by dividing the display unit into a plurality of areas and independently driving each area as necessary, and at the same time using the liquid crystal display device. The power consumption of the display device can be reduced.

Description

Thin film transistor array substrate and liquid crystal display device having the same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME}

1 is a plan view schematically illustrating a TFT array substrate according to an embodiment of the present invention.

2 is a plan view schematically illustrating a TFT array substrate according to another embodiment of the present invention.

3 is a block diagram illustrating a shift register constituting a driving circuit unit according to an exemplary embodiment of the present invention.

4 is an exploded perspective view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100, 300: TFT array substrate 110, 310: display unit

120, 320: peripheral portion 130, 330: first driving circuit portion

140, 340: second driving circuit unit 200, 350, 630: driving chip

400: driving circuit unit 500: liquid crystal display device

600: display panel assembly 610: liquid crystal display panel

620: flexible circuit board 700: backlight assembly

710: light source 720: light guide plate

730 optical sheets 740 reflector

750: reflective film 800: mold frame

900: bottom chassis 1000: top chassis

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate and a liquid crystal display device having the same, and to a thin film transistor array substrate employing a screen division method in order to reduce power consumption.

In general, a liquid crystal display device includes a liquid crystal layer having dielectric anisotropy interposed between an array substrate having an field generating electrode and an opposite substrate coupled thereto. A voltage is applied to the field generating electrode to generate an electric field in the liquid crystal layer, and the desired image is obtained by controlling the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field.

The light at this time may be provided from an artificial light source provided separately, or may be provided from a natural light source.

An artificial light source for a liquid crystal display, that is, a back light device, uses a plurality of fluorescent lamps such as a cold cathode fluorescent lamp (CCFL) or an external electrode fluorescent lamp (EEFL) as a light source, or a plurality of light emitting diodes. use.

The power consumed by these backlights accounts for a large part of the total power consumption of the liquid crystal display. Therefore, in order to reduce the power consumption of the liquid crystal display, it is desirable to increase the power efficiency of the backlight or reduce the use time thereof.

In particular, in the case of a portable display device such as a mobile phone, a portable power source such as a battery is used as a power source, and thus there is a limit in the amount of power supply. What is needed is a way to extend the service life of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to have a plurality of display units capable of displaying different images, respectively, and to provide driving signals efficiently to the respective display units. An array substrate is provided.

Another object of the present invention is to provide a liquid crystal display device having the array substrate.

In order to achieve the above object, an array substrate according to an embodiment of the present invention includes a display portion, a peripheral portion, a first driving circuit portion, and a second driving circuit portion. The display unit is divided into a first display area and a second display area. The peripheral portion is an area surrounding the display portion. The first driving circuit portion is formed in the peripheral portion adjacent to the first display area to provide a first gate signal to the first display area. The second driving circuit part includes a second driving circuit part formed in the peripheral portion adjacent to the second display area to provide a second gate signal to the second display area.

The first and second driving circuit parts include an amorphous silicon thin film transistor.

In order to achieve another object of the present invention, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel and a driving chip. The liquid crystal display panel is divided into a plurality of display parts and a peripheral part surrounding the display parts, and a plurality of driving circuit parts for providing a gate signal to each of the display parts are respectively coupled to the TFT array substrate formed in the peripheral part and opposite to the array substrate. A counter substrate and a liquid crystal layer interposed between the two substrates are provided. The driving chip provides a gate driving signal to the driving circuit units, respectively.

According to such a TFT array substrate and a liquid crystal display device having the same, power consumption of the liquid crystal display device can be reduced by dividing the display unit into a plurality of regions and driving each region independently as necessary. It is possible to reduce the power consumption of the display device using.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically illustrating a TFT array substrate according to an embodiment of the present invention.

Referring to FIG. 1, a TFT array substrate 100 according to an exemplary embodiment of the present invention includes a display unit 110, a peripheral unit 120, a first driving circuit unit 130, and a second driving circuit unit 140. . In the TFT array substrate 100 according to the present invention, a driving chip 200 for providing a gate driving signal to the first and second driving circuit units 130 and 140 may be mounted.

The display unit 110 includes a first display area 111 and a second display area 112. In the exemplary embodiment of the present invention, the display unit 110 is illustrated as being divided into two display regions 111 and 112, but is not limited thereto and may include two or more display regions.

First, the first display area 111 is a main display area, and is formed in a matrix form by first to n-th data lines DL1 to DLm intersecting the first to p-th gate lines GL1 to GLp. A plurality of pixel units PA, and each of the pixel units PA includes a plurality of thin film transistors extending from the gate lines GL1 to GLp and the data lines DL1 to DLm. Transistor; TFT).

The first display area 111 functions as a main display area for displaying a main image when a display device such as a mobile phone employing the TFT array substrate 100 is driven in a first driving mode in which an image is normally displayed. do.

The second display area 112 is a sub display area and is formed in a matrix form by the first to nth data lines DL1 to DLm intersecting the p + 1 to nth gate lines GLp + 1 to GLn. And a plurality of pixel parts PA, each pixel part PA being extended from the gate lines GLp + 1 to GLn and the data lines DL1 to DLn. And a thin film transistor (TFT).

The second display area 112 functions as a sub display area for displaying a standby image such as a date and time, a display of radio wave sensitivity, and a residual amount of battery in a display device such as a mobile phone employing the TFT array substrate 100. Do this.

Accordingly, the second display area 112 may be configured to drive only in the second driving mode displaying only the standby image, and may be configured to display the standby image even in the first driving mode in which the main image is displayed. In this case, the resolution of the first display area 111 may be formed to have a higher resolution than the resolution of the second display area 112. That is, the first display area 111 may be configured as a high resolution area, and the second display area 112 may be configured as a low resolution area.

Here, in the first driving mode, the second display area 112 may display the standby image or may integrally display the main image with the first display area 111.

The peripheral part 120 includes first to fourth peripheral areas SA1, SA2, SA3, and SA4 surrounding the display part 110.

The first driving circuit unit 130 is formed in the first peripheral area SA1 of the peripheral part 120 and receives the first gate signal in response to a gate driving signal such as a clock signal provided from the driving chip 200. The first to pth gate lines are sequentially provided.

The second driving circuit unit 140 is formed in the second peripheral area SA2 of the peripheral part 120 that faces the first peripheral area SA1, and drives a gate such as a clock signal provided from the driving chip 200. The second gate signal is sequentially provided to the p + 1 to nth gate lines in response to the signal.

To this end, the first and second driving circuit units 130 and 140 may be formed by forming TFTs (not shown) on the first and second peripheral areas SA1 and SA2, respectively. The TFT included in the first and second driving circuit parts 130 and 140 may be implemented as an amorphous silicon TFT or a polycrystalline silicon TFT.

As such, when the first and second driving circuit units 130 and 140 are implemented on the TFT array substrate 100, when the first and second driving circuit units 130 and 140 are implemented in the driving chip 200. In comparison with this, the size of the driving chip 200 can be reduced, which has a large cost reduction effect.

Here, the first driving circuit unit 130 and the second driving circuit unit 140 are illustrated as being formed in the first peripheral area SA1 and the second peripheral area SA2, respectively, but the present invention is not limited thereto. That is, the first and second driving circuit parts 130 and 140 may be formed in the second and first peripheral areas SA2 and SA1, respectively, and both may be formed on the first or second peripheral areas SA1 and SA2. May be

The driving chip 200 is mounted on the third peripheral area SA3 of the peripheral part 120 and provides data signals necessary for displaying an image on the display part 110 to the data lines DL1 to DLm. The gate driving signal for driving the first and second driving circuits 130 and 140 in the first and second driving modes is provided.

That is, the driving chip 200 outputs the gate driving signal to the first and second driving circuit units 130 and 140 in the first driving mode, and the gate only to the second driving circuit unit 140 in the second driving mode. By outputting a driving signal, the operation of the first and second driving circuit units 130 and 140 is controlled.

The driving chip 200 may be mounted on the fourth peripheral area SA4 facing the third peripheral area SA3.

2 is a plan view schematically illustrating a TFT array substrate according to another embodiment of the present invention.

Referring to FIG. 2, the TFT array substrate 300 according to another exemplary embodiment of the present invention may include a display unit 310, a peripheral unit 320, a first driving circuit unit 330, a second driving circuit unit 340, and a driving chip ( 350).

The display unit 310 includes a first display area 311 and a second display area 312. In an exemplary embodiment, the display unit 310 is divided into two display areas 311 and 312, but the present invention is not limited thereto and may include two or more display areas.

In addition, the display unit 310 is substantially the same as the display unit 110 illustrated in FIG. 1, that is, the first display area 311 is configured as a high resolution area, and the second display area 312 is configured as a low resolution area. Can be configured. Therefore, detailed description overlapping with FIG. 1 will be omitted.

The peripheral part 320 includes first to fourth peripheral areas SA1, SA2, SA3, and SA4 surrounding the display part 310.

The first driving circuit unit 330 includes a first gate driver 330a and a second gate driver 330b.

The first gate driver 330a is formed in the first peripheral area SA1 of the peripheral part 320, and the second gate driver 330b is formed in the second peripheral area SA2 of the peripheral part 320. In addition, the first and second gate drivers 330a and 330b may be formed in the second and first peripheral areas SA2 and SA1, respectively.

The first gate driver 330a and the second gate driver 330b may include gate lines GL1 formed in the first display area 311 in response to a gate driving signal such as a clock signal provided from the driving chip 350. GL1) sequentially provides first gate signals to odd-numbered gate lines and even-numbered gate lines, respectively.

Therefore, it is possible to prevent the loss of current due to the RC delay generated by providing the first gate signal to the gate lines GL1 to GLp with one driving circuit. In addition, it is possible to extend the time for which one gate line is activated, thereby sufficiently guaranteeing the charging time of the liquid crystal capacitor connected to the TFT formed extending from each of the gate lines GL1 to GLp, thereby having such a configuration. The display quality of a liquid crystal display device provided with a TFT array substrate can also be improved.

The second driving circuit unit 340 includes a third gate driver 340a and a fourth gate driver 340b.

The third gate driver 340a is formed in the first peripheral area SA1 of the peripheral part 320, and the third gate driver 340b is formed in the second peripheral area SA2 of the peripheral part 320. In addition, the third and fourth gate drivers 340a and 340b may be formed in the second and first peripheral areas SA2 and SA1, respectively.

The third gate driver 330a and the second gate driver 330b may include gate lines GLp formed in the second display area 312 in response to a gate driving signal such as a clock signal provided from the driving chip 350. The second gate signal is sequentially provided to odd-numbered gate lines and even-numbered gate lines among +1 to GLn.

Therefore, it is possible to prevent loss of current due to RC delay generated by providing the second gate signal to the gate lines GL1 to GLp with one driving circuit unit. In addition, it is possible to extend the time for which one gate line is activated, thereby sufficiently guaranteeing the charging time of the liquid crystal capacitor connected to the TFT formed by extending from each of the gate lines GLp + 1 to GLn. It is also possible to improve the display quality of the liquid crystal display device provided with the TFT array substrate having the same.

The driving chip 350 is mounted on the third peripheral area SA3 of the peripheral part 320 and data lines DL1 to DLm formed on the display part 310 to output data signals necessary for displaying an image on the display part 310. The gate driving signal is provided to the first and second driving circuit units 330 and 340.

In this case, signal wirings 360 for providing a gate driving signal such as a clock signal to the second driving circuits 330 and 340 are provided in the first and second peripheral areas SA1 and SA2 of the TFT array substrate 300. The driving chip 350 may further include an output pin electrically connected to the signal wire 360.

In addition, the driving chip 350 may be mounted on the fourth peripheral area SA4 facing the third peripheral area SA3.

3 is a block diagram illustrating a shift register constituting a driving circuit unit according to an exemplary embodiment of the present invention. The driving circuit portion shown in FIG. 3 is commonly applied to the first and second driving circuit portions shown in FIGS. 1 and 2.

Referring to FIG. 3, the driving circuit unit 400 includes one shift register including n + 1 stages SRC1 to SRCn + 1 connected dependently to each other. The stages SRC1 to SRCn + 1 are composed of n driving stages SRC1 to SRCn and one dummy stage SRCn + 1. Here, each of the stages SRC1 to SRCn + 1 may be formed by various circuit configurations including an amorphous silicon TFT or a polycrystalline silicon TFT.

Each stage SRC1 to SRCn + 1 has an input terminal IN, a clock terminal CK, a first power supply voltage terminal VSS, a second power supply voltage terminal VDD, a control terminal CT, and an output terminal OUT. ).

The scan start signal STV may be input to the input terminal IN of the first stage SRC1, and the previous stage SRC1 to SRCn of the input terminals IN of the subsequent stages SRC2 to SRCn + 1. Output signals OUT1 to OUTn may be input.

First and second clock signals CK and CKB are applied to the clock terminal CK. The first clock signal CK is applied to odd-numbered stages SRC1, SRC3, ..., and the second clock signal CKB is applied to even-numbered stages SRC2, SRC4, ....

The output terminal OUT of the odd stages SRC1, SRC3,... Outputs the output signals OUT1, OUT3..., Synchronized with the first clock signal CK, and outputs the even stages ( The output terminal OUT of SRC2, SRC4, ... outputs the output signals OUT2, OUT4, ... synchronized with the second clock signal CKB.

In this case, the first clock signal CK and the second clock signal CKB may have opposite phases.

Output terminals OUT of the stages SRC1 to SRCn are connected to corresponding gate lines GL1 to GLn of the display units 110, 120, and 130 illustrated in FIGS. 1 to 2.

On the other hand, the output signal OUT2 to OUTn + 1 of the next stage SRC2 to SRCn + 1 is input to each control terminal CT of each stage SRC1 to SRCn as a control signal. That is, the control signal input to each control terminal CT is a signal delayed by the duty period of its output signal.

Therefore, the output signals OUT1 to OUTn of each stage SRC1 to SRCn have an active period (high state) instantaneously, so that corresponding gate lines are sequentially selected in the active period of each output signal.

In addition, since the next stage of the dummy stage SRCn + 1 does not exist, the vertical start signal STV may be applied to the control terminal CT of the dummy stage SRCn + 1.

Meanwhile, a gate-off voltage and a gate-on voltage are applied to the first power supply voltage terminal VSS and the second power supply voltage terminal VDD of each of the stages SRC1 to SRCn + 1 which are not described.

4 is an exploded perspective view schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display 500 according to the exemplary embodiment of the present invention includes a display panel assembly 600 and a backlight assembly 700.

The display panel assembly 600 includes a liquid crystal display panel 610 and a flexible circuit board 620.

The liquid crystal display panel 610 is a thin film transistor (TFT) substrate 611, an opposing substrate 612 coupled to the TFT substrate 611, and a liquid crystal layer injected between the TFT substrate 611 and the opposing substrate 612. (Not shown).

In the TFT substrate 611, a plurality of pixel portions (not shown) are formed in a matrix form. The pixel portion extends in the first direction D1 on the TFT substrate 611 in gate lines (not shown) and in the second direction D2 orthogonal to the first direction D1. Defined by data lines (not shown) that insulate and intersect with each other.

In addition, the TFT substrate 611 includes a pixel electrode made of indium tin oxide (ITO), which is a conductive material, and includes a gate terminal connected to each of the gate lines, a source terminal connected to each of the data lines; A thin film transistor (TFT) including a drain terminal connected to the pixel electrode is included.

In addition, the TFT substrate 611 includes a plurality of display regions, and a plurality of driving circuit portions for providing a gate signal are formed in each of the display regions. In this case, the driving circuit unit may include a TFT having an amorphous silicon layer or a polycrystalline silicon layer. In this regard, the detailed description thereof will be omitted as described above with reference to FIGS. 1 to 3. The TFTs included in the driving circuit portion may be formed together when forming the TFT constituting the pixel portion.

In addition, a driving chip 630 for providing a data signal to the data lines at a first end of the TFT substrate 611 and a gate driving signal to the driving circuit part is formed by a chip on glass (COG) process. It may be mounted on the substrate 611. The driving chip 630 is formed in the same manner as the driving chips 200 and 350 illustrated in FIGS. 1 and 2, and thus, detailed description thereof will be omitted.

The flexible circuit board 620 is attached to the first end of the TFT substrate 611 and transmits a control signal for controlling the driving chip 630. The flexible circuit board 620 may be equipped with a timing controller or a memory for controlling the timing of the data signal or the gate signal. The flexible circuit board 620 may be electrically connected to wirings on the TFT substrate 611 through an anisotropic conductive film (ACF).

On the opposite substrate 612, red, green, and blue color filters (not shown) expressing a predetermined color using white light may be formed by a thin film process, and a transparent conductive material, for example, indium tin oxide (Indium Tin) A common electrode made of oxide (ITO) or indium zinc oxide (IZO) may be formed to face the pixel electrode.

The liquid crystal layer is arranged by voltages applied to the pixel electrode and the common electrode, thereby changing the polarization state of the light provided from the backlight assembly 700.

The backlight assembly 700 may include a light source 710, a light guide plate 720, optical sheets 730, and a reflector plate 740.

The light source 710 is disposed on one side of the light guide plate 720 to provide light to the light guide plate 710. As the light source 710, a CCFL, an EEFL, or the like may be used, or a light emitting diode having low power consumption may be used.

In the present exemplary embodiment, the light source 710 is disposed on one side of the light guide plate 720, but may be disposed on both sides of the light guide plate 720 or a plurality of light guide plates below the light guide plate 720, if necessary. 720 may be omitted.

The light guide plate 720 may be formed with a light guide pattern (not shown) for guiding light to a display area of the liquid crystal display panel 610 where an image is displayed, as necessary.

The optical sheets 730 are disposed between the light guide plate 720 and the liquid crystal display panel 610, and provide uniform brightness of light passing through the light guide plate 720 to the liquid crystal display panel 610.

The reflecting plate 740 is disposed under the light guide plate 720, and the light provided to the light guide plate 720 reflects light leaked toward the lower direction of the light guide plate 720 to improve light utilization efficiency.

In the present embodiment, the reflective plate 740 having a predetermined thickness has been described as an example, but instead of the reflective plate 740, a thin sheet-shaped reflective sheet may be configured.

In addition, the liquid crystal display 500 according to the exemplary embodiment may further include a selective reflection film 750 disposed between the display panel assembly 600 and the backlight assembly 700.

The selective reflection film 750 selectively transmits or reflects light. Therefore, when the light source 710 formed in the backlight assembly 700 is in an on state, the light emitted from the light source 710 is transmitted through the selective reflection film 750, and the liquid crystal is transmitted using the transmitted light. An image is displayed on the display panel 610. In addition, when the light source 710 is in an off state, external light incident through the liquid crystal display panel 610 is reflected by the selective reflection film 750, and the liquid crystal display panel 610 using the reflected light. By displaying an image, the liquid crystal display panel 610 can display a predetermined necessary standby image with the light source 710 turned off when the liquid crystal display panel 610 is driven in the second driving mode, thereby consuming power. Can be greatly reduced.

In addition, the liquid crystal display 500 according to the exemplary embodiment may further include a mold frame 800, a bottom chassis 900, and a top chassis 1000.

In the mold frame 800, the reflective plate 740, the light guide plate 720, the optical sheets 730, and the liquid crystal display panel 610 are sequentially received. Accordingly, the display panel assembly 600 may be disposed on the backlight assembly 700 and display a predetermined image by using light emitted from the backlight assembly 700.

The bottom chassis 900 is formed of a metal material, and a storage space is formed to form a mold frame 800 in which the reflective plate 740, the light guide plate 720, the optical sheets 730, and the liquid crystal display panel 610 are sequentially received. I receive it.

The top chassis 1000 has an opening 1010 for exposing an effective display area of the liquid crystal display panel 610, and is coupled with the bottom chassis 900 to surround the edge of the liquid crystal display panel 610 to be combined with the display panel assembly. The 600 is fixed to the top of the backlight assembly 700. The top chassis 1000 prevents the liquid crystal display panel 610 from being damaged by the external impact and from being separated from the top of the backlight assembly 700.

According to the TFT array substrate and the liquid crystal display device having the same according to the present invention as described above, the display unit is divided into a plurality of regions, and each region is independently driven as necessary to drive the entire liquid crystal display device. The power consumption of the device can be reduced, and at the same time, the power consumption of the display device using the liquid crystal display can be reduced.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (17)

A display unit partitioned into a first display area and a second display area; A peripheral portion surrounding the display portion; A first driving circuit part formed in the peripheral portion adjacent to the first display area to provide a first gate signal to the first display area; And And a second driving circuit part formed in the peripheral portion adjacent to the second display area to provide a second gate signal to the second display area. The TFT array substrate of claim 1, wherein the first and second driving circuit portions comprise an amorphous silicon thin film transistor. The TFT array substrate of claim 1, wherein the resolution of the first display area is higher than that of the second display area. The display device of claim 1, wherein gate lines to which the gate signal is provided are formed in the first display area. The first driving circuit unit, A first gate driver configured to provide the gate signal to an odd-numbered gate line among the gate lines; And And a second gate driver configured to provide the gate signal to an even-numbered gate line among the gate lines. The TFT array of claim 4, wherein the first gate driver is formed in a first peripheral region of the peripheral region, and the second gate driver is formed in a second peripheral region facing the first peripheral region. Board. The display device of claim 1, wherein gate lines to which the gate signal is provided are formed in the second display area. The second driving circuit unit, A third gate driver configured to provide the gate signal to an odd-numbered gate line among the gate lines; And And a fourth gate driver configured to provide the gate signal to an even-numbered gate line among the gate lines. The TFT array of claim 6, wherein the third gate driver is formed in a first peripheral region of the peripheral region, and the fourth gate driver is formed in a second peripheral region facing the first peripheral region. Board. A plurality of driving circuit portions partitioned into a display portion and a periphery surrounding the display portion and providing a gate signal to the display portion, a TFT array substrate formed on the periphery portion, an opposing substrate coupled to the array substrate, and interposed between the two substrates; A liquid crystal display panel having a liquid crystal layer; And And a driving chip for providing a gate driving signal to the driving circuit units, respectively. The liquid crystal display device of claim 8, wherein the driving circuit units comprise an amorphous silicon thin film transistor. The method of claim 8, wherein the display unit A first display area having a high resolution; And And a second display area having a lower resolution than the first display area. The display device of claim 10, wherein the driving chip has a first driving mode for driving the first and second display areas, and a second driving mode for driving the second display area without driving the first display area. Liquid crystal display device characterized in that. The liquid crystal display market value of claim 11, wherein the first driving mode displays a main image on the first display area and a standby image on the second display area. The liquid crystal display of claim 11, wherein the first driving mode displays a main image on the first display area and the second display area. The liquid crystal display of claim 11, wherein the second driving mode displays a standby image on the second display area. The method of claim 8, wherein the driving circuit portion, A first driving circuit part formed in the peripheral portion adjacent to the first display area to provide a first gate signal to gate lines formed in the first display area; And And a second driving circuit formed in the peripheral portion adjacent to the second display area to provide a second gate signal to gate lines formed in the second display area. The method of claim 15, wherein the first driving circuit unit, A first gate driver configured to provide the gate signal to an odd-numbered gate line among the gate lines; And And a second gate driver configured to provide the gate signal to an even-numbered gate line among the gate lines. The method of claim 15, wherein the second driving circuit unit, A third gate driver configured to provide the gate signal to an odd-numbered gate line among the gate lines; And And a fourth gate driver configured to provide the gate signal to an even-numbered gate line among the gate lines.

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