KR20070035037A - 정보 처리 시스템 및 정보 처리 방법과 컴퓨터 프로그램 - Google Patents

정보 처리 시스템 및 정보 처리 방법과 컴퓨터 프로그램 Download PDF

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Publication number
KR20070035037A
KR20070035037A KR20077000928A KR20077000928A KR20070035037A KR 20070035037 A KR20070035037 A KR 20070035037A KR 20077000928 A KR20077000928 A KR 20077000928A KR 20077000928 A KR20077000928 A KR 20077000928A KR 20070035037 A KR20070035037 A KR 20070035037A
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South Korea
Prior art keywords
information processing
subprocessor
image data
information
program
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Withdrawn
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KR20077000928A
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English (en)
Korean (ko)
Inventor
신지 나까가와
Original Assignee
소니 가부시끼 가이샤
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Application filed by 소니 가부시끼 가이샤 filed Critical 소니 가부시끼 가이샤
Publication of KR20070035037A publication Critical patent/KR20070035037A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR20077000928A 2004-07-16 2005-07-05 정보 처리 시스템 및 정보 처리 방법과 컴퓨터 프로그램 Withdrawn KR20070035037A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JPJP-P-2004-00210761 2004-07-16
JP2004210761A JP2006031480A (ja) 2004-07-16 2004-07-16 情報処理システム及び情報処理方法、並びにコンピュータプログラム
PCT/JP2005/012422 WO2006008961A1 (ja) 2004-07-16 2005-07-05 情報処理システム及び情報処理方法、並びにコンピュータプログラム

Publications (1)

Publication Number Publication Date
KR20070035037A true KR20070035037A (ko) 2007-03-29

Family

ID=35785081

Family Applications (1)

Application Number Title Priority Date Filing Date
KR20077000928A Withdrawn KR20070035037A (ko) 2004-07-16 2005-07-05 정보 처리 시스템 및 정보 처리 방법과 컴퓨터 프로그램

Country Status (6)

Country Link
US (1) US20080253673A1 (https=)
EP (1) EP1775962A1 (https=)
JP (1) JP2006031480A (https=)
KR (1) KR20070035037A (https=)
CN (1) CN101036393A (https=)
WO (1) WO2006008961A1 (https=)

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KR101102190B1 (ko) * 2008-12-03 2012-01-02 엔비디아 코포레이션 압축 상태 비트 캐시 및 보조 기억 장치

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JP4802482B2 (ja) * 2004-11-10 2011-10-26 カシオ計算機株式会社 画像処理装置及び画像処理方法
US8599841B1 (en) 2006-03-28 2013-12-03 Nvidia Corporation Multi-format bitstream decoding engine
US8593469B2 (en) * 2006-03-29 2013-11-26 Nvidia Corporation Method and circuit for efficient caching of reference video data
US20090245580A1 (en) * 2006-07-21 2009-10-01 Darryl Greig Modifying parameters of an object detector based on detection information
JP4862566B2 (ja) 2006-09-04 2012-01-25 富士通株式会社 動画像処理装置及びプリフェッチ制御方法
JP4910576B2 (ja) * 2006-09-04 2012-04-04 富士通株式会社 動画像処理装置
JP4983160B2 (ja) * 2006-09-04 2012-07-25 富士通株式会社 動画像処理装置
JP4535047B2 (ja) 2006-09-06 2010-09-01 ソニー株式会社 画像データ処理方法、画像データ処理方法のプログラム、画像データ処理方法のプログラムを記録した記録媒体及び画像データ処理装置
CN100578452C (zh) * 2007-10-15 2010-01-06 晨星半导体股份有限公司 应用于嵌入式系统的数据处理方法
US20090225867A1 (en) * 2008-03-06 2009-09-10 Lee Kun-Bin Methods and apparatus for picture access
FR2930059B1 (fr) * 2008-04-09 2010-04-09 Ateme Sa Traitement d'une sequence video dans une memoire cache
US8577165B2 (en) * 2008-06-30 2013-11-05 Samsung Electronics Co., Ltd. Method and apparatus for bandwidth-reduced image encoding and decoding
US20090327609A1 (en) * 2008-06-30 2009-12-31 Bruce Fleming Performance based cache management
US9253496B2 (en) * 2008-12-12 2016-02-02 Qualcomm Incorporated Intelligent decoded picture buffering
JP5469433B2 (ja) * 2009-10-30 2014-04-16 株式会社キーエンス 画像処理装置及び画像処理方法
KR101279507B1 (ko) * 2009-12-15 2013-06-28 한국전자통신연구원 병렬 처리 기반 파이프라인 복호화 장치 및 방법
JP5020391B2 (ja) * 2010-02-22 2012-09-05 パナソニック株式会社 復号化装置及び復号化方法
JP5378298B2 (ja) * 2010-05-18 2013-12-25 日立コンシューマエレクトロニクス株式会社 機器間情報交換機能を有するストレージ
JP5278497B2 (ja) * 2011-06-02 2013-09-04 カシオ計算機株式会社 画像処理装置及び画像処理方法
CN102360273A (zh) * 2011-09-26 2012-02-22 北京邦诺存储科技有限公司 控制存储器与非易失性缓存装置协同存储的设备和方法
KR101611289B1 (ko) * 2011-12-16 2016-04-12 엘지전자 주식회사 전기자동차 및 그 제어방법
US20140184630A1 (en) * 2012-12-27 2014-07-03 Scott A. Krig Optimizing image memory access
US9667706B2 (en) 2013-08-16 2017-05-30 Pearson Education, Inc. Distributed processing systems
JP2015207123A (ja) * 2014-04-18 2015-11-19 富士通株式会社 ストレージ装置、ストレージ制御方法およびストレージ制御プログラム
US10148589B2 (en) * 2014-09-29 2018-12-04 Pearson Education, Inc. Resource allocation in distributed processing systems
US10051294B2 (en) * 2015-03-31 2018-08-14 Avago Technologies General Ip (Singapore) Pte. Ltd. Compressed video buffering
CN106157230B (zh) * 2016-05-25 2019-08-16 华中科技大学 海量脑组织三维图像数据快速调用方法
CN107562686B (zh) * 2017-08-18 2019-12-10 清华大学 信息处理方法和装置
TWI714003B (zh) * 2018-10-11 2020-12-21 力晶積成電子製造股份有限公司 可執行人工智慧運算的記憶體晶片及其操作方法
US11436046B2 (en) 2018-10-11 2022-09-06 Powerchip Semiconductor Manufacturing Corporation Electronic device with memory processor-based multiprocessing architecture and operation method thereof
JP7259537B2 (ja) * 2019-05-16 2023-04-18 オムロン株式会社 情報処理装置

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JP3123496B2 (ja) * 1998-01-28 2001-01-09 日本電気株式会社 動き補償処理方法及びシステム並びにその処理プログラムを記録した記録媒体
JP4427827B2 (ja) * 1998-07-15 2010-03-10 ソニー株式会社 データ処理方法、データ処理装置及び記録媒体
JP3322233B2 (ja) * 1999-03-19 2002-09-09 日本電気株式会社 動画像伸長方法及びそれを実行するプログラムを記録した記録媒体
US6809734B2 (en) * 2001-03-22 2004-10-26 Sony Computer Entertainment Inc. Resource dedication system and method for a computer architecture for broadband networks
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US7088872B1 (en) * 2002-02-14 2006-08-08 Cogent Systems, Inc. Method and apparatus for two dimensional image processing
US7304646B2 (en) * 2004-08-19 2007-12-04 Sony Computer Entertainment Inc. Image data structure for direct memory access
US7924914B2 (en) * 2005-09-20 2011-04-12 Intel Corporation Dynamically configuring a video decoder cache for motion compensation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101102190B1 (ko) * 2008-12-03 2012-01-02 엔비디아 코포레이션 압축 상태 비트 캐시 및 보조 기억 장치

Also Published As

Publication number Publication date
WO2006008961A1 (ja) 2006-01-26
CN101036393A (zh) 2007-09-12
JP2006031480A (ja) 2006-02-02
US20080253673A1 (en) 2008-10-16
EP1775962A1 (en) 2007-04-18

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20070115

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid