KR20070034673A - LCD and its driving method - Google Patents

Abstract

Disclosed are a liquid crystal display and a driving method thereof for improving image quality. The liquid crystal display device includes a liquid crystal display panel and a driver. The liquid crystal display panel includes a plurality of pixel portions, each pixel portion having a first switching element connected to the first gate line, a transmission portion having a first liquid crystal capacitor connected to the first switching element, and a second switching connected to the second gate line. And a reflector having a second liquid crystal capacitor connected to the element and the second switching element, and a split capacitor connected between the second switching element and the second liquid crystal capacitor. The driving unit applies a first common voltage to the first liquid crystal capacitor when the first switching element is turned on, and a second to the second liquid crystal capacitor when the first switching element is turned off and the second switching element is turned on. Apply a common voltage. Accordingly, by including the divided capacitors connected in series with the second liquid crystal capacitor, the image quality may be improved by substantially matching the V-T curve and the V-R curve.

Split Capacitor, Liquid Crystal Capacitor, Reflector, Transmissive, Common Voltage

Description

Liquid crystal display and driving method thereof {LIQUID CRYSTAL DISPLAY AND METHOD FOR DRIVING THE SAME}

1A is a graph showing voltage vs. transmittance in VA mode.

1B is a graph showing voltage versus reflectivity in VA mode.

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a detailed block diagram of the main driver shown in FIG. 2.

4 is a detailed block diagram illustrating the gate circuit of FIG. 2.

FIG. 5 is a detailed block diagram of the source driver illustrated in FIG. 3.

6 is a timing diagram illustrating a method of driving a liquid crystal display device by the source driver of FIG. 4.

7 is a graph illustrating a V-T curve and a V-R curve by simulation according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: liquid crystal display panel 200: drive device

210: main drive unit 211: control unit

215: voltage generator 217: source driver

230: gate circuit portion 300: flexible printed circuit board

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof for improving the image quality.

In the liquid crystal display panel, a liquid crystal layer is formed between the lower substrate and the upper substrate facing each other. The liquid crystal display panel displays an image by applying an electric field to the liquid crystal to change the molecular arrangement of the liquid crystal.

The liquid crystal display panel includes a reflective liquid crystal display panel for reflecting external light incident from the outside to display an image, a transmissive liquid crystal display panel for transmitting an internal light incident from the rear surface, and an external light according to the shape of a light source. Are classified into a reflection-transmissive liquid crystal display panel which displays an image by transmitting reflection and internal light.

The reflection-transmissive liquid crystal display panel has a voltage-to-transmission (V-T) curve in a transmissive mode and a voltage-to-reflectance (V-R) curve in a reflective mode.

FIG. 1A is a graph showing voltage vs. transmittance in VA mode, and FIG. 1B is a graph showing voltage vs. reflectance in VA mode.

1A and 1B, the black voltage VTb in the transmission mode and the black voltage VRb in the reflection mode are similar to each other at approximately 0V to 1.5V. On the other hand, the white voltage VTw in the transmission mode and the white voltage VRw in the reflection mode are different from each other. Specifically, the white voltage VTw in the transmission mode is about 4.5V, and the white voltage VRw in the reflection mode is about 2.5V, with a deviation of about 2V.

As described above, the reflection-transmissive liquid crystal display device has a problem in that image quality is deteriorated according to characteristics in which transmittance and reflectance of the V-T curve and the V-R curve do not coincide.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a liquid crystal display device for improving image quality.

Another object of the present invention is to provide a method of driving the liquid crystal display device.

The liquid crystal display device according to the embodiment for realizing the above object of the present invention includes a liquid crystal display panel and a driver. The liquid crystal display panel includes a plurality of pixel parts, each pixel part including a transmission part having a first switching element connected to a first gate line, a first liquid crystal capacitor connected to the first switching element, and a second connected to the second gate line. And a reflector having a second switching element and a second liquid crystal capacitor connected to the second switching element, and a split capacitor connected between the second switching element and the second liquid crystal capacitor. The driving unit applies a first common voltage to the first liquid crystal capacitor when the first switching element is turned on, and the first switching element is turned off and the second switching element is turned on when the first switching element is turned on. The second common voltage is applied to the liquid crystal capacitor.

According to another aspect of the present invention, there is provided a transmission part including a first switching element and a first liquid crystal capacitor connected to the first switching element, and a splitting capacitor connected to the second switching element and the second switching element. And a pixel portion including a reflecting portion having a second liquid crystal capacitor connected to the split capacitor, the driving method of the liquid crystal display device being turned on from the first switching element and transferred from the first switching element to the first liquid crystal capacitor. Charging a first pixel voltage corresponding to a data voltage and a first common voltage; turning off the first switching device and turning on the second switching device to turn on the second liquid crystal capacitor; Charging a second pixel voltage corresponding to the data voltage transferred from the second common voltage.

According to the liquid crystal display and the driving method thereof, a split capacitor is connected in series with the liquid crystal capacitor of the reflector to divide the charging voltage of the liquid crystal capacitor so that the image quality can be improved by substantially matching the VT curve and the VR curve. .

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display device includes a liquid crystal display panel 100, a driving device 200, and a flexible printed circuit board 300. The flexible printed circuit board (FPC) 300 electrically connects an external device (not shown) and the driving device 200.

The liquid crystal display panel 100 includes a lower substrate 110, an upper substrate 120, and a liquid crystal layer (not shown) interposed between the lower and upper substrates 110 and 120, and the display area DA. The peripheral area PA surrounds the display area DA. The liquid crystal layer is preferably a vertical alignment (VA) mode when the equipotential is formed on the lower substrate 110 and the upper substrate 120.

In the display area DA, m source wirings DL1,... DLm and 2n gate wirings GL1,..., GL2n intersecting the source wirings DL1,... DLm are formed. In the display area DA, m × n pixel parts P are defined by the source lines DL1,... DLm and the gate lines GL1 .. .. GL2n. Where n and m are natural numbers.

Each pixel portion P includes a transmissive portion Pt that transmits first light by one source wiring DL and two first and second gate lines GLt and GLr, and a reflective portion that reflects the first light. It is defined as (Pr). The cell gaps of the liquid crystal layers of the transmission part Pt and the reflection part Pr have the same single cell gap.

The transmission part Pt may include a first switching element TFTt connected to the source line DL and a first gate line GLt, a first liquid crystal capacitor CLCt and a first switching element connected to the first switching element TFTt. 1 includes a storage capacitor (CSTt).

The reflector Pr may include a second switching element TFTr connected to the source line DL and a second gate line GLt, a split capacitor CC connected to the second switching element TFTr, A second liquid crystal capacitor CLCr connected in series with the division capacitor CC and a second storage capacitor CSTr connected to the switching element TFTr are included. The common electrodes of each of the first and second liquid crystal capacitors CLCt and CLCr are integrally formed, and the common electrodes of each of the first and second storage capacitors CSTt and CSTr are connected in common.

Referring to a driving method of the pixel portion P, as the first gate line GLt is activated, the first switching element TFT1 is turned on and the data voltage VD transferred from the source line DL is transferred. The first liquid crystal capacitor CLCt is applied to a first electrode (eg, a transparent electrode). The common voltage VCOM is applied to the common electrode which is the second electrode of the first liquid crystal capacitor CLCt. Accordingly, the first liquid crystal capacitor CLCt of the transmission part Pt is charged with the first pixel voltage VPt corresponding to the data voltage VD and the common voltage VCOM.

Subsequently, in a state in which the first gate line GLt is inactivated and the first switching element TFTt is turned off, the second gate line GLr is activated to turn on the second switching element TFT2. Let's do it. As the second switching element TFTr is turned on, the data voltage VD transferred from the source wiring DL is applied to the first electrode (eg, a reflective electrode) of the second liquid crystal capacitor CLCr. The common voltage VCOM is applied to the common electrode which is the second electrode of the second liquid crystal capacitor CLCr.

Meanwhile, a partial voltage VD1 of the data voltage VD is charged in the division capacitor CC connected in series with the second liquid crystal capacitor CLCr, and thus, the second liquid crystal capacitor CLCr is substantially in the second liquid crystal capacitor CLCr. As the remaining data voltage VD2 except for the partial voltage VP1 is applied, the second pixel voltage VPr smaller than the first pixel voltage VPt is charged.

That is, by adjusting the capacitance of the divided capacitor CC, the difference between the white gray voltage VTw of the VT curve and the black gray voltage VTb and the white gray voltage VRw and the black gray voltage of the VR curve The difference VRw-VRb between (VRb) is made substantially the same.

The offset value between the adjusted V-T curve and the V-R curve compensates by changing the common voltage VCOM applied to the common electrodes of the first and second liquid crystal capacitors CLCt and CLCt.

The first and second common voltages VSTGt and VSTGr may be applied to the first and second common electrodes of the first and second storage capacitors CSTt and CSTr in the same manner as the first and second common voltages VCOMt and VCOMr. Are applied respectively. The common voltage VCOM of the liquid crystal capacitor and the common voltage VSTG of the storage capacitor are substantially the same.

That is, when the first switching element TFTt of the transmission part Pt is driven, a first common voltage VSTGt = VCOMt is applied to the first storage capacitor CSTt, and the second switching of the reflector Pr is performed. When the device TFTr is driven, a second common voltage VSTGr = VCOMr is applied to the second storage capacitor CSTr.

The driving device 200 includes a main driver 210 and a gate circuit 230.

The main driver 210 is a single chip mounted in the peripheral area PA, and drives signals to drive the pixel units P using control and data signals transmitted from the flexible printed circuit board 300. Output them.

The gate circuit 230 is integrated in the peripheral area PA or mounted in a separate chip form. The gate circuit 230 supplies gate signals G1t, G1r, Gnt, and Gnr to the gate lines GL1,..., GL2n based on a driving signal provided from the main driver 210. Output The first and second gate signals G1t and G1r applied to each pixel portion P are output during 1H (horizontal period).

3 is a detailed block diagram of the main driver shown in FIG. 2.

2 and 3, the main driver 210 includes a controller 211, a memory 213, a voltage generator 215, and a source driver 217.

The controller 211 receives a data signal 210a and a control signal 210b from the outside. The control signal 210b includes a horizontal synchronous signal, a vertical synchronous signal, a main clock signal, and a data enable signal.

The controller 211 writes and reads the data signal 210a into the memory 213 based on the control signal 210b. The control unit 211 outputs gate control signals 211a to the gate circuit unit 230. The gate control signals 211a include a vertical start signal STV, a first clock signal CK, a second clock signal CKB, and a gate voltage VSS.

The controller 211 outputs source control signals 211b to the source driver 217, and outputs a data signal 211d read from the memory 213 to the source driver 217. The source control signals 211b include a horizontal start signal, a load signal, and an inversion signal.

The controller 211 outputs a control signal 211c such as a main clock signal and an inverted signal to the voltage generator 215.

The voltage generator 215 generates driving voltages using an external power source 210c applied from the outside. The driving voltages may include gate voltages VSS and VDD 215a provided to the controller 211, reference gamma voltages VREF 215b provided to the source driver 217, and the upper substrate. Common voltages VCOMt and VCOMr applied to the common electrode of 120 and common voltages VSTGt and VSTGr 215c applied to the storage common electrode of the lower substrate 110 are included.

The voltage generator 215 applies a first common voltage VCOMt to the first liquid crystal capacitor in a first section of the 1H section where the first gate line GLt is activated, under the control of the controller 211. The second common voltage VCOMr is output to the second common electrode of the second liquid crystal capacitor CLCr during the second period in which the second gate line GLr is activated. .

The voltage generator 215 may also use the first and second common electrodes of the first and second storage capacitors CSTt and CSTr in the same manner as the first and second common voltages VCOMt and VCOMr. The second common voltages VSTGt and VSTGr are respectively applied.

The second common voltage VCOMr is a voltage for compensating an offset value between the data voltage in the transmission mode and the data voltage in the reflection mode, and is a value preset by an experiment. That is, the second common voltage VCOMr is a value obtained by comparing the dielectric constant of the liquid crystal layer according to the data voltage in the transmission mode and the dielectric constant of the liquid crystal layer according to the data voltage in the reflection mode.

The source driver 217 converts the data signal 211d read from the memory 213 into analog data voltages D1,..., Dm based on the gamma reference voltage VREF 215b. Outputs the source wirings DL1 and DLm formed on the lower substrate 110.

4 is a detailed block diagram illustrating the gate circuit of FIG. 2.

2 and 4, the gate circuit unit 230 includes one first shift register including 2n + 1 stages SRC1 to SRC2n + 1 connected to each other independently. The stages SRC1 to SRC2n + 1 include 2n driving stages SRC1 to SRC2n and one dummy stage SRC2n + 1.

Each stage SRC1 includes an input terminal IN, a clock terminal CK, a voltage terminal VSS, a control terminal CT, a first output terminal GOUT, and a second output terminal SOUT.

First and second clock signals CK and CKB are applied to the clock terminal CK. The first clock signal CK is applied to odd-numbered stages SRC1, SRC3, ..., SRC2n + 1, and the second clock signal CKB is even-numbered stages SRC2, SRC4, ... SRC2n).

The first output terminals GOUT of the odd-numbered stages SRC1, SRC3,..., SRC2n + 1 are gate signals G1t, G2t, .., Gnt synchronized to the first clock signal CK. The first output terminals GOUT of the even-numbered stages SRC2, SRC4,..., And SRC2n are gate signals G1r, G2r, .., Gnr synchronized to the second clock signal CKB. )

The first output terminal GOUT of the first stage SRC1 is connected to the first gate line GLt of the transmission part Pt to control the driving of the first switching element TFTt, and to the second stage SRC2. The first output terminal GOUT is connected to the second gate line GLr of the reflector Pr to control the driving of the second switching element TFTr.

Preferably, the first gate signal G1t, which is an output signal of the first stage SRC1, is output in the initial H / 2 section of the 1H section, and the second gate signal G1r, which is an output signal of the second stage SRC2. Is output in the later H / 2 interval or 1H interval. In this manner, the 2n stages SRC1 to SRC2n sequentially output the gate signals G1t, G1r, ..., Gnt, and Gnr.

On the other hand, the first output terminal GOUT of the dummy stage SRC2n + 1 is maintained in a floating state because there is no corresponding gate wiring.

The second output terminal SOUT of each odd-numbered stage SRC1 outputs the first clock signal CK as a stage driving signal, and the second output terminal SOUT of each even-numbered stage SRC2 is The second clock signal CKB is output as a stage driving signal.

The stage driving signal output from the second output terminal SOUT of the previous stage is applied to the input terminal IN of each odd-numbered stage SRC1, and the second output of the next stage is applied to the control terminal CT. The stage driving signal output from the terminal SOUT is applied.

Here, since there is no previous stage of the first stage SRC1, the vertical start signal STV is applied to the input terminal IN of the first stage SRC1. In addition, since the next stage of the dummy stage SRCn + 1 does not exist, the vertical start signal STV is applied to the control terminal CT of the dummy stage SRCn + 1.

On the other hand, each of the stages SRC1 to SRC2n + 1 further includes a voltage terminal to which a gate off voltage VSS is applied.

FIG. 5 is a detailed block diagram of the source driver illustrated in FIG. 3.

3 and 5, the source driver 270 may include a sampling latch 271, a level shifter 272, a holding latch 273, a mux 274, a DAC 275, and a D. The mux part 276 is included.

The sampling latch unit 271 includes a plurality of sampling latches SL and data signals R1, G1, B1,.., Rk corresponding to a 1H section provided from the control unit 211. , Gk, Bk) are sequentially latched.

The level shifter 272 includes a plurality of level shifters LS, and shifts the level of the data signals output from the shift register 271 to a predetermined level.

The holding latch unit 273 includes a plurality of holding latches (HL), sequentially latches data signals output from the level shifter unit 272, and is provided from the control unit 211. Load based on signal 211b.

The mux unit 274 groups the data signals output from the holding latch unit 273 into a plurality of groups and controls the output of the data signals included in each group.

Specifically, as illustrated, the data signals R1, G1, B1, .., Rk, Gk, and Bk output from the holding latch unit 373 are grouped into a red data group, a green data group, and a blue data group. Control the output of the red, green and blue data signals in each group.

First, the red data signals R1 and ..Rk are output to the DAC unit 275, and the next green data signals G1 and ..Gk are output to the DAC unit 275, followed by the blue data. Signals B1 and .. Bk are output to the DAC unit 275.

The DAC unit 275 first converts the red data signals R1,..., Rk into analog data voltages and outputs the same to the demux unit 376. The demux 276 outputs the input red data voltages to the source wirings DL1, DL4,..., DLm-2 connected to the first output terminals.

Next, the DAC unit 275 converts the green data signals G1,..., Gk into analog data voltages and outputs them to the demux unit 276. The demux unit 276 outputs the input green data voltages to the source lines DL2, DL6,..., DLm-1 connected to the second output terminals.

In the same manner, source wirings DL3, DL7,..., DLm connected to the third output terminals of the demux 376 through the DAC unit 375 through the blue data signal B1, .. Bk. Output to

As a result, the data voltages output to the source wirings DL1, DL2,... DLm correspond to the red data voltages corresponding to the output method of the source driver 270. 2), the next green data voltages are output to the corresponding source wirings DL2 and .DLm-1, and the blue data voltages are then output to the source wirings DL3 and .DLm.

FIG. 6 is a timing diagram for describing a driving method of the liquid crystal display shown in FIG. 2.

2 to 6, the source driver 270 converts the data signal of the horizontal line provided from the controller 211 into an analog data voltage during the 1H period, so that the source wirings DL1,. ) (DATA_O).

In detail, the source driver 270 outputs the data voltage 1L_O of the first horizontal line during the initial H / 2 period among the 1H sections, and the gate circuit 230 includes the first gate signal corresponding to the first horizontal line. (G1t) is output, and the voltage generator 215 outputs the first common voltage VCOMt to the common electrode of the upper substrate. The voltage generator 215 outputs the third common voltage VSTGt having the same potential as the first common voltage VCOMt to the storage common electrode of the lower substrate. In this case, the source driver 270 groups the data voltage 1L_O of the first horizontal line in the order of red data voltage, green data voltage and blue data voltage according to a 3 × 1 MUX method.

The first switching element TFTt of the transmission part Pt is turned on by the first gate signal G1t and transmits a data voltage transferred to the source wiring DL to the first liquid crystal capacitor CLCt. It transfers to the transparent electrode TE which is an electrode. The first common voltage VCOMt is transmitted to the common electrode, which is the second electrode of the first liquid crystal capacitor CLCt.

As a result, the pixel voltage VDP charged in the first liquid crystal capacitor CLCt of the transmission part Pt, that is, the first pixel voltage corresponding to the potential difference between the data voltage VD and the first common voltage VCOMt. (VPt) is charged.

Next, the source driver 270 maintains the data voltage 1L_O of the first horizontal line being output during the later H / 2 period of the 1H section, and the gate circuit 230 has a second corresponding to the first horizontal line. The gate signal G1r is output, and the voltage generator 215 outputs the second common voltage VCOMr to the common electrode of the upper substrate. The voltage generator 215 outputs the fourth common voltage VSTGr having the same potential as the second common voltage VCOMr to the storage common electrode of the lower substrate.

That is, the first switching device TFTt of the transmission part Pt is turned off and the second switching device TFTr of the reflection part Pr is turned on during the later H / 2 period.

As a result, the second switching element TFTr of the reflector Pr is turned on by the second gate signal G1r and the data voltage transferred to the source wiring DL is transferred to the second liquid crystal capacitor CLCr. It is delivered to a split capacitor (CC) connected in series. Partial data voltage VD1 of the data voltage is charged in the divided capacitor CC, and the remaining data voltage VD2 is charged in the second liquid crystal capacitor CLCr. Meanwhile, the second common voltage VCOMr is applied to the common electrode which is the second electrode of the second liquid crystal capacitor CLCr.

As a result, the pixel voltage VDP charged in the second liquid crystal capacitor CLCr of the reflector Pr corresponds to the second pixel voltage corresponding to the potential difference between the remaining data voltage VD2 and the second common voltage VCOMr. (VPr) is charged. In the second pixel voltage VPr, the first pixel voltage VPt is divided by the division capacitor CC to charge a voltage lower than the first pixel voltage VPt.

In addition, the first common voltage VCOMt applied to the first liquid crystal capacitor CLCt while the transmissive part Pt is driven and the second liquid crystal capacitor CLCr are applied to the second liquid crystal capacitor CLCr while the reflective part Pr is driven. The offset value between the VT curve and the VR curve adjusted by the division capacitor CC is compensated by the voltage difference ΔV between the second common voltage VCOMr.

As a result, the V-T curve and the V-R curve substantially coincide with the variation of the division capacitor CC and the common voltage VCOM.

7 is a graph illustrating a V-T curve and a V-R curve by simulation according to an embodiment of the present invention.

2 and 7, the white voltage VRw and the black voltage VRb of the VR curve are adjusted by adjusting the capacitance of the division capacitor CC connected in series with the second liquid crystal capacitor CLCr of the reflector Pr. The difference is adjusted so as to be substantially equal to the difference (VTw-VTb) of the difference (VRw-VRb) and the white voltage (VTw) of the VT curve and the black voltage (VTb).

In addition, the offset value between the VR curve and the VT curve adjusted so that the difference between the white voltage and the black voltage is substantially the same is applied to the first common voltage VCOMt and the reflecting part applied to the first liquid crystal capacitor CLCt of the transmission part Pt. The second common voltage VCOMr applied to the second liquid crystal capacitor CLCr of Pr is changed and compensated for.

Preferably, the second common voltage VCOMr is a value obtained by comparing the dielectric constant of the liquid crystal layer according to the data voltage in the reflective mode with the dielectric constant of the liquid crystal layer according to the data voltage in the transmissive mode. to be.

As described above, according to the present invention, by forming a divided capacitor connected in series with the second liquid crystal capacitor of the reflector to adjust the capacitance of the divided capacitor, the difference between the white voltage in the transmissive mode and the black voltage and the white voltage in the reflective mode The difference in the black voltage can be made substantially the same.

In addition, the offset values of the V-T curve and the V-R curve adjusted by the division capacitor may be compensated by adjusting the level of the common voltage of the liquid crystal capacitor.

Accordingly, the image quality of the reflection-transmissive liquid crystal display device can be improved by substantially matching the V-T curve and the V-R curve.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (17)

A plurality of pixel portions, each pixel portion having a first switching element connected to a first gate line, a transmission portion having a first liquid crystal capacitor connected to the first switching element, a second switching element connected to a second gate line, and A liquid crystal display panel including a reflection part having a second liquid crystal capacitor connected to a second switching element, and a split capacitor connected between the second switching element and the second liquid crystal capacitor; And A first common voltage is applied to the first liquid crystal capacitor when the first switching element is turned on, and the second liquid crystal capacitor when the first switching element is turned off and the second switching element is turned on And a driver for applying a second common voltage to the liquid crystal display. The liquid crystal display device of claim 1, wherein the first and second liquid crystal capacitors comprise a liquid crystal layer, And the liquid crystal layer is in a vertical alignment mode. The method of claim 1, wherein the transmitting part comprises a first storage capacitor, and the reflecting part comprises a second storage capacitor, The driving unit applies the first common voltage to the first storage capacitor when the first switching element is turned on, when the first switching element is turned off and the second switching element is turned on. And applying the second common voltage to the second storage capacitor. The display device of claim 1, wherein the first switching device comprises: a first gate electrode connected to the first gate wiring; a first source electrode connected to a source wiring; and a first electrode connected to a transparent electrode which is a first electrode of the first liquid crystal capacitor. And a drain electrode. The display device of claim 4, wherein the second switching device comprises a second gate electrode connected to the second gate line adjacent to the first gate line, a second source electrode connected to the source line, and a first electrode of the split capacitor. A drain electrode connected thereto; And a second electrode of the split capacitor is connected to a reflective electrode which is a first electrode of the second liquid crystal capacitor. The liquid crystal display of claim 5, wherein the first and second common electrodes of the first and second liquid crystal capacitors are electrically connected. The method of claim 5, wherein the driving unit A source driver which outputs a data voltage to the source wiring; A gate driver configured to output first and second gate signals for activating the first and second gate lines; And The first common voltage is applied to the first liquid crystal capacitor when the first gate wiring is activated, and the second common voltage is applied to the second liquid crystal when the first gate wiring is inactive and the second gate wiring is activated. And a voltage generator applied to the capacitor. The liquid crystal display of claim 7, wherein the first gate line is activated during an initial H / 2 period, and the second gate line is activated during a later H / 2 period. The liquid crystal display of claim 7, wherein the first gate line is activated during an initial H / 2 period, and the second gate line is activated during an 1H period. A transmissive portion having a first switching element and a first liquid crystal capacitor connected to the first switching element, a splitting portion connected to the second switching element and the second switching element and a reflecting portion having a second liquid crystal capacitor connected to the split capacitor. In a driving method of a liquid crystal display device including a pixel portion, Turning on the first switching device to charge the first liquid crystal capacitor with a first pixel voltage corresponding to a data voltage transferred from the first switching device and a first common voltage; And The first switching element is turned off and the second switching element is turned on to charge the second liquid crystal capacitor with a second pixel voltage corresponding to a data voltage transferred from the second switching element and a second common voltage. And driving the liquid crystal display device. The display device of claim 10, wherein the first switching device comprises: a first gate electrode connected to a first gate wiring; a first source electrode connected to a source wiring; and a first drain connected to a transparent electrode, which is a first electrode of the first liquid crystal capacitor. A method of driving a liquid crystal display device comprising an electrode. 12. The display device of claim 11, wherein the second switching element comprises a second gate electrode connected to the second gate line adjacent to the first gate line, a second source electrode connected to the source line, and a first electrode of the split capacitor. A drain electrode connected thereto; And a second electrode of the split capacitor is connected to a reflective electrode which is a first electrode of the second liquid crystal capacitor. The method of claim 12, wherein the charging of the first pixel voltage is performed. Applying the first common voltage to a first common electrode of the first liquid crystal capacitor; And Activating the first gate wiring to apply the data voltage applied to the source wiring to the transparent electrode of the first liquid crystal capacitor. The method of claim 12, wherein the charging of the second pixel voltage is performed. Deactivating the first gate wiring; Applying a second common voltage to a second electrode of the split capacitor and a second common electrode of the second liquid crystal capacitor; Activating the second gate wiring to apply a partial voltage of the data voltage applied to the source wiring to the first electrode of the division capacitor; And And applying a voltage other than the partial voltage among the data voltages to the reflective electrode of the second liquid crystal capacitor. The method of claim 12, wherein the first gate line is activated during an initial H / 2 period. The method of claim 12, wherein the second gate line is activated during an initial H / 2 period. The method of claim 12, wherein the second gate line is activated during a 1H period.

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