KR20070027941A - Liquid crystal display, apparatus and method for driving the same - Google Patents

Abstract

A liquid crystal display and an apparatus and a method for driving the same are provided to improve image quality by changing the voltage difference between first and second common voltages. A liquid crystal display panel(100) includes a plurality of pixels. Each of the pixels includes a transmission part(Pt) and a reflection part(Pr). The transmission part includes a first switching element(TFTt) connected to a first gate line and a first liquid crystal capacitor connected to the first switching element. The reflection part includes a second switching element(TFTr) connected to the second gate line and a second liquid crystal capacitor connected to the second switching element. A driving unit(200) applies a first common voltage to the first liquid crystal capacitor when the first switching element is turned on. The driving unit applies a second common voltage to the second liquid crystal capacitor when the first switching element is turned off and the second switching element is turned on.

Description

Liquid crystal display device and driving device and method thereof {LIQUID CRYSTAL DISPLAY, APPARATUS AND METHOD FOR DRIVING THE SAME}

1A is a graph showing voltage vs. transmittance in VA mode.

1B is a graph showing voltage versus reflectivity in VA mode.

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a plan view of the liquid crystal display panel illustrated in FIG. 2.

4 is a cross-sectional view taken along line II ′ of FIG. 3.

FIG. 5 is a detailed block diagram of the main driver of FIG. 2.

6 is a detailed block diagram illustrating the gate circuit of FIG. 2.

FIG. 7 is a block diagram according to an exemplary embodiment of the source driver illustrated in FIG. 5.

FIG. 8 is a timing diagram illustrating a method of driving a liquid crystal display device according to the source driver of FIG. 7.

9 is a block diagram according to another exemplary embodiment of the source driver illustrated in FIG. 5.

FIG. 10 is a timing diagram illustrating a method of driving a liquid crystal display device by the source driver of FIG. 9.

11A and 11B are graphs illustrating a V-T curve and a V-R curve in VA mode.

<Description of the symbols for the main parts of the drawings>

100: liquid crystal display panel 200: drive device

210: main drive unit 211: control unit

215: voltage generator 217: source driver

230: gate circuit portion 300: flexible printed circuit board

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, a drive device and a method thereof, and more particularly, to a liquid crystal display device for improving image quality, and a drive device and a method thereof.

In general, a liquid crystal layer is formed between a lower substrate and an upper substrate facing each other. The liquid crystal display panel displays an image by applying an electric field to the liquid crystal to change the molecular arrangement of the liquid crystal.

The liquid crystal display panel includes a reflective liquid crystal display panel for reflecting external light incident from the outside to display an image, a transmissive liquid crystal display panel for transmitting an internal light incident from the rear surface, and an external light according to the shape of a light source. Are classified into a reflection-transmissive liquid crystal display panel which displays an image by transmitting reflection and internal light.

The reflection-transmissive liquid crystal display panel has a voltage-to-transmission (V-T) curve in a transmissive mode and a voltage-to-reflectance (V-R) curve in a reflective mode.

FIG. 1A is a graph showing voltage vs. transmittance in VA mode, and FIG. 1B is a graph showing voltage vs. reflectance in VA mode.

1A and 1B, the transmission mode has the highest transmittance at approximately 4.5V or more. In other words, the white voltage Tw is approximately 4.5V in the transmission mode. On the other hand, the reflection mode has the highest transmittance at approximately 2.5V and transmittance is lowered again from 2.5V or more. Due to a mismatch between the V-T curve and the V-R curve, the reflection-transmissive liquid crystal display has a problem in that image quality is degraded.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a liquid crystal display device for improving image quality.

Another object of the present invention is to provide a driving device of the liquid crystal display device.

Another object of the present invention is to provide a method of driving the liquid crystal display.

The liquid crystal display device according to the embodiment for realizing the above object of the present invention includes a liquid crystal display panel and a driver. The liquid crystal display panel includes a plurality of pixel parts, each pixel part having a first switching element connected to a first gate line and a transmission part having a first liquid crystal capacitor connected to the first switching element and a second connected to a second gate line. And a reflecting unit having a switching element and a second liquid crystal capacitor connected to the second switching element. The driving unit applies a first common voltage to the first liquid crystal capacitor when the first switching element is turned on, and the first switching element is turned off and the second switching element is turned on when the first switching element is turned on. The second common voltage is applied to the liquid crystal capacitor.

A plurality of pixel parts according to an embodiment for realizing the above object of the present invention, each pixel portion having a first switching element connected to the first gate wiring and a first liquid crystal capacitor connected to the first switching element A driving apparatus of a liquid crystal display device having a reflection part having a second switching element connected to a transmissive part and a second gate wiring and a second liquid crystal capacitor connected to the second switching element includes a gate driver and a voltage generator. The gate driver outputs first and second gate signals for activating the first and second gate lines. The voltage generator applies the first common voltage to the first liquid crystal capacitor when the first gate line is activated, and applies the second common voltage to the second liquid crystal capacitor when the first gate line is inactive. do.

According to an embodiment of the present invention, a transmission part including a first switching element and a first liquid crystal capacitor connected to the first switching element, and a second liquid crystal connected to the second switching element and the second switching element. A driving method of a liquid crystal display device including a pixel part including a reflective part having a capacitor corresponds to a data voltage and a first common voltage transferred from the first switching element to the first liquid crystal capacitor by turning on the first switching element. Charging the first pixel voltage and turning off the first switching element and turning on the second switching element to have a second common voltage with the data voltage transferred from the second switching element to the second liquid crystal capacitor. Charging a second pixel voltage corresponding to the voltage.

According to such a liquid crystal display device and a driving device and method thereof, an image displayed on a pixel part by applying a first common voltage to a first liquid crystal capacitor of a transmission part and a second common voltage to a second liquid crystal capacitor of a reflector part. Can improve the picture quality.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

2 is a schematic plan view of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the liquid crystal display device includes a liquid crystal display panel 100, a driving device 200, and a flexible printed circuit board 300. The flexible printed circuit board (FPC) 300 electrically connects an external device (not shown) and the driving device 200.

The liquid crystal display panel 100 includes a lower substrate 110, an upper substrate 120, and a liquid crystal layer (not shown) interposed between the lower and upper substrates 110 and 120, and the display area DA. The peripheral area PA surrounds the display area DA.

In the display area DA, m source wirings DL1,... DLm and 2n gate wirings GL1,..., GL2n intersecting the source wirings DL1,... DLm are formed. In the display area DA, m × n pixel parts P are defined by the source lines DL1,... DLm and the gate lines GL1 .. .. GL2n. Where n and m are natural numbers.

Each pixel portion P includes a transmissive portion Pt that transmits first light by one source wiring DL and two first and second gate lines GLt and GLr, and a reflective portion that reflects the first light. It is defined as (Pr). The transmission part Pt may include a first switching element TFTt connected to the source wiring DL and a first gate line GLt, and a first liquid crystal capacitor CLCt connected to the first switching element TFTt. And a first storage capacitor CSTt.

The reflector Pr includes a second switching element TFTr connected to the source line DL and the second gate line GLt, a second liquid crystal capacitor CLCr connected to the second switching element TFTr, and The second storage capacitor CSTr is included.

The driving device 200 includes a main driver 210 and a gate circuit 230.

The main driver 210 is a single chip mounted in the peripheral area PA, and drives signals to drive the pixel units P using control and data signals transmitted from the flexible printed circuit board 300. Output them.

The gate circuit 230 is integrated in the peripheral area PA or mounted in a separate chip form. The gate circuit 230 supplies gate signals G1t, G1r, Gnt, and Gnr to the gate lines GL1,..., GL2n based on a driving signal provided from the main driver 210. Output The first and second gate signals G1t and G1r applied to each pixel portion P are output during 1H (horizontal period).

3 is a plan view of the liquid crystal display panel illustrated in FIG. 2.

4 is a cross-sectional view taken along line II ′ of FIG. 3.

2 to 4, the liquid crystal display panel includes a lower substrate 110, an upper substrate 120, and a liquid crystal layer 130.

The lower substrate 110 includes a first base substrate 101, and the first base substrate 101 includes m source wirings DL1, DLm and 2n gate wirings GL1,. M × n pixel portions P are defined by GL2n).

Each pixel part P includes a transmission part Pt that transmits the first light L1 incident under the first base substrate 101, and a second light incident on the first base substrate 101. It consists of a reflecting part Pr which reflects L2). A storage common line SCL is formed in the pixel portion P.

The transmission part Pt includes a first switching element TFTt and a transparent electrode TE. The first switching element TFTt may include a first gate electrode 131 connected to a first gate line GLt, a source electrode 133 connected to the source line DL, and a drain electrode connected to the transparent electrode TE. 134).

A gate insulating layer 102 is formed on the first gate line GLt and the first gate electrode 131, and between the first gate electrode 131 and the first source-drain electrodes 133 and 134. The active layer 132 is formed. Preferably, the active layer 132 includes amorphous silicon.

A protective insulating layer 103 and an organic insulating layer 104 on which the first contact hole 137 is formed are formed on the source wiring DL and the first source-drain electrodes 133 and 134. Of course, the organic insulating layer 104 may not be formed. The first drain electrode 134 and the transparent electrode TE are electrically connected through the first contact hole 137.

The reflector Pr includes a second switching element TFTr and a reflective electrode RE. The second switching element TFTr may include a second gate electrode 141 connected to a second gate line GLr, a source electrode 143 connected to the source line DL, and a drain electrode connected to the reflective electrode RE. 144).

A gate insulating layer 102 is formed on the second gate line GLr and the second gate electrode 141, and between the second gate electrode 141 and the second source-drain electrodes 143 and 144. The active layer 142 is formed. Preferably, the active layer 142 includes amorphous silicon.

A protective insulating layer 103 and an organic insulating layer 104 on which the second contact hole 147 is formed are formed on the source wiring DL and the second source-drain electrodes 143 and 144. Of course, the organic insulating layer 104 may not be formed. The second drain electrode 144 and the reflective electrode RE are electrically connected to each other through the second contact hole 147.

The storage common line SCL is formed of the same metal layer as the first and second gate lines GLt and GLr.

In the above description, the thin film transistor including the active layer formed of amorphous silicon is used as the first and second switching elements TFTt and TFTr. However, it will be apparent to those skilled in the art that the thin film transistor including the active layer formed of polycrystalline silicon may be formed. .

The upper substrate 120 includes a second base substrate 121, and the light blocking layer 122, the color filter layer 123, the overcoating layer 124, and the common electrode layer 125 are disposed on the second base substrate 121. Is formed.

The light blocking layer 122 blocks the first and second lights L1 and L2. In detail, the light blocking layer 122 is formed in a region corresponding to the source wirings DL, the first and second gate wirings GLt and GLr, and the first and second switching elements TFTt and TFTr. Is formed. Further, it is formed in a region corresponding to the boundary between the transmission portion Pt and the reflection portion Pr.

The color filter layer 123 is formed corresponding to the pixel portion P and includes red, green, and blue filter patterns. Although not shown, a light hole is formed in the color filter layer 123 corresponding to a predetermined region of the reflector Pr. The light hole compensates for the luminance difference between the transmitted light and the reflected light by transmitting the first light as it is.

The overcoat layer 124 is formed on the color filter layer 123 to protect the color filter layer 123 and to planarize the second base substrate 121.

The common electrode layer 125 is a common electrode facing the transparent electrode TE and the reflective electrode RE formed on the lower substrate 110. The first and second liquid crystal capacitors CLCt and CLCr of the pixel portion P are disposed. ).

 The liquid crystal layer 130 is a vertical alignment (VA) mode. When an equipotential is applied between the transparent electrode TE and the reflective electrode RE and the common electrode layer 125, the liquid crystal layer 130 is vertically aligned to display black gray.

5 is a detailed block diagram of the main driver 210 of FIG. 2.

2 and 5, the main driver 210 includes a controller 211, a memory 213, a voltage generator 215, and a source driver 217.

The controller 211 receives a data signal 210a and a control signal 210b from the outside. The control signal 210b includes a horizontal synchronous signal, a vertical synchronous signal, a main clock signal, and a data enable signal.

The controller 211 writes and reads the data signal 210a into the memory 213 based on the control signal 210b. The control unit 211 outputs gate control signals 211a to the gate circuit unit 230. The gate control signals 211a include a vertical start signal STV, a first clock signal CK, a second clock signal CKB, and a gate voltage VSS.

The controller 211 outputs source control signals 211b to the source driver 217, and outputs a data signal 211d read from the memory 213 to the source driver 217. The source control signals 211b include a horizontal start signal, a load signal, and an inversion signal.

The controller 211 outputs a control signal 211c such as a main clock signal and an inverted signal to the voltage generator 215.

The voltage generator 215 generates driving voltages using an external power source 210c applied from the outside. The driving voltages may include gate voltages VSS and VDD 215a provided to the controller 211, reference gamma voltages VREF 215b provided to the source driver 217, and the upper substrate. Common voltage (VCOM) 215c applied to the common electrode of 120 is included.

The voltage generator 215 applies a first common voltage VCOMt to the first liquid crystal capacitor in a first section of the 1H section where the first gate line GLt is activated, under the control of the controller 211. The second common voltage VCOMr is output to the second common electrode of the second liquid crystal capacitor CLCr during the second period in which the second gate line GLr is activated. .

The voltage difference between the first common voltage VCOMt and the second common voltage VCOMr is substantially equal to the voltage difference between the peak voltage Tw of the V-T curve and the peak voltage Rw of the V-R curve. For example, referring to FIGS. 1A and 1B, the voltage difference between the first and second common voltages VCOMt and VCOMr is a voltage difference between 4.5V of the peak voltage Tw of the VT curve and 2.5V of the peak voltage Rw of the VR curve. Has a voltage difference of 2V.

 The source driver 217 converts the data signal 211d read from the memory 213 into analog data voltages D1,..., Dm based on the gamma reference voltage VREF 215b. Outputs the source wirings DL1 and DLm formed on the lower substrate 110.

6 is a detailed block diagram illustrating the gate circuit of FIG. 2.

2 and 6, the gate circuit unit 230 includes one shift register including 2n + 1 stages SRC1 to SRC2n + 1 connected to each other independently. The stages SRC1 to SRC2n + 1 include 2n driving stages SRC1 to SRC2n and one dummy stage SRC2n + 1.

Each stage SRC1 includes an input terminal IN, a clock terminal CK, a voltage terminal VSS, a control terminal CT, a first output terminal GOUT, and a second output terminal SOUT.

First and second clock signals CK and CKB are applied to the clock terminal CK. The first clock signal CK is applied to odd-numbered stages SRC1, SRC3, ..., SRC2n + 1, and the second clock signal CKB is even-numbered stages SRC2, SRC4, ... SRC2n).

The first output terminals GOUT of the odd-numbered stages SRC1, SRC3,..., SRC2n + 1 are gate signals G1t, G2t, .., Gnt synchronized to the first clock signal CK. The first output terminals GOUT of the even-numbered stages SRC2, SRC4,..., And SRC2n are gate signals G1r, G2r, .., Gnr synchronized to the second clock signal CKB. )

The first output terminal GOUT of the first stage SRC1 is connected to the first gate line GLt of the transmission part Pt to control the driving of the first switching element TFTt, and to the second stage SRC2. The first output terminal GOUT is connected to the second gate line GLr of the reflector Pr to control the driving of the second switching element TFTr.

Preferably, the first gate signal G1t, which is an output signal of the first stage SRC1, is output in the initial H / 2 section of the 1H section, and the second gate signal G1r, which is an output signal of the second stage SRC2. Is output in the later H / 2 interval or 1H interval. In this manner, the 2n stages SRC1 to SRC2n sequentially output the gate signals G1t, G1r, ..., Gnt, and Gnr.

On the other hand, the first output terminal GOUT of the dummy stage SRC2n + 1 is maintained in a floating state because there is no corresponding gate wiring.

The second output terminal SOUT of each odd-numbered stage SRC1 outputs the first clock signal CK as a stage driving signal, and the second output terminal SOUT of each even-numbered stage SRC2 is The second clock signal CKB is output as a stage driving signal.

The stage driving signal output from the second output terminal SOUT of the previous stage is applied to the input terminal IN of each odd-numbered stage SRC1, and the second output of the next stage is applied to the control terminal CT. The stage driving signal output from the terminal SOUT is applied.

Here, since there is no previous stage of the first stage SRC1, the vertical start signal STV is applied to the input terminal IN of the first stage SRC1. In addition, since the next stage of the dummy stage SRCn + 1 does not exist, the vertical start signal STV is applied to the control terminal CT of the dummy stage SRCn + 1.

On the other hand, each of the stages SRC1 to SRC2n + 1 further includes a voltage terminal to which a gate off voltage VSS is applied.

FIG. 7 is a block diagram according to an exemplary embodiment of the source driver illustrated in FIG. 5.

5 and 7, the source driver 270 includes a sampling latch part 271, a level shifter part 272, a holding latch part 273, a DAC part 274, and an output buffer part 275. do.

The sampling latch unit 271 includes a plurality of sampling latches SL and data signals R1, G1, B1,.., Rk corresponding to a 1H section provided from the control unit 211. , Gk, Bk) sequentially latch.

The level shifter 272 includes a plurality of level shifters LS, and shifts the level of the data signals output from the shift register 271 to a predetermined level.

The holding latch unit 273 includes a plurality of holding latches (HL), sequentially latches data signals output from the level shifter unit 272, and is provided from the control unit 211. Load based on signal 211b.

The DAC unit 274 includes a plurality of digital-to-analog converters (DACs), and the data signals loaded from the holding latch unit 272 are analogized using the reference gamma voltages VREF. The data voltage is converted into data and output.

The output buffer unit 275 includes a plurality of amplifiers A, and amplifies the data voltages output from the DAC unit 274 to a predetermined level so that the source lines DL1, DL2, DL3,. , DLm-2, DLm-1, DLm).

FIG. 8 is a timing diagram illustrating a method of driving a liquid crystal display device according to the source driver of FIG. 7.

1, 5 to 8, the source driver 270 converts a horizontal line data signal provided from the controller 211 into an analog data voltage during a 1H period, and converts the source lines DL1,. .., DLm) to output (DATA_O).

In detail, the source driver 270 outputs the data voltage 1L_O of the first horizontal line during the initial H / 2 period among the 1H sections, and the gate circuit 230 includes the first gate signal corresponding to the first horizontal line. (G1t) is output, and the voltage generator 215 outputs the first common voltage VCOMt to the common electrode of the upper substrate.

As a result, the first switching element TFTt of the transmission part Pt is turned on by the first gate signal G1t and receives a voltage corresponding to the data voltage transferred to the source wiring DL. It applies to the transparent electrode TE which is a 1st electrode of (CLCt). The first common voltage VCOMt is applied to the common electrode, which is the second electrode of the first liquid crystal capacitor CLCt.

As a result, the first liquid crystal capacitor CLCt is charged with a first pixel voltage VPt corresponding to a potential difference between the transparent electrode TE and the common electrode.

Next, the source driver 270 continues to output the data voltage 1L_O of the first horizontal line being output during the later H / 2 period of the 1H section, and the gate circuit 230 may control the first horizontal line. The second gate signal G1r is output, and the voltage generator 215 outputs the second common voltage VCOM2 to the common electrode of the upper substrate.

That is, the first switching device TFTt of the transmission part Pt is turned off and the second switching device TFTr of the reflection part Pr is turned on during the later H / 2 period.

As a result, the second switching element TFTr of the reflector Pr is turned on by the second gate signal G1r and receives a voltage corresponding to the data voltage transmitted to the source wiring DL. It applies to the reflective electrode RE which is the 1st electrode of capacitor CLCr. The second common voltage VCOMr is applied to the common electrode, which is the second electrode of the second liquid crystal capacitor CLCr.

As a result, the second liquid crystal capacitor CLCr is charged with the second pixel voltage VPr corresponding to the potential difference between the reflective electrode RE and the common electrode.

As illustrated, the first pixel voltage VPt charged in the first liquid crystal capacitor CLCt and the second pixel voltage VPr charged in the second liquid crystal capacitor CLCr are different from each other. The first common voltage VCOMt and the second common voltage VCOMr are substantially different from the voltage difference between the peak voltage Tw of the VT curve and the peak voltage Rw of the VR curve when referring to FIGS. 1A and 1B. Have the same voltage difference.

For example, when the peak voltage Tw of the VT curve is 4.5V and the peak voltage Rw of the VR curve is 2.5V, the voltage difference between the first and second common voltages VCOMt and VCOMr is Δ. V) is 2V. In detail, when the liquid crystal layer is in VA mode, an absolute value of the first common voltage VCOMt applied to the first liquid crystal capacitor CLCt of the transmission part Pt is equal to the second liquid crystal capacitor CLCr of the reflection part Pr. ) Is greater than the absolute value of the second common voltage VCOMr applied by the voltage difference ΔV.

In the above description, the transmission part Pt is driven by turning on the first switching device TFTt connected to the first gate line GL1t during the initial H / 2 period, and the first switching device TFTt during the later H / 2 period. ) Is turned off and the second switching element TFTr connected to the second gate line GL1r is turned on to drive the reflector Pr.

However, like the second gate signals G1r and G2r shown in dashed lines, the first and second switching elements TFTt and TFTr are simultaneously turned on during the initial H / 2 period to transmit the Pt and the reflector. After driving Pr, only the reflector Pr may be driven by turning off the first switching element TFTr during the later H / 2 period.

9 is a block diagram according to another exemplary embodiment of the source driver illustrated in FIG. 5.

5 and 9, the source driver 370 may include a sampling latch unit 371, a level shifter unit 372, a holding latch unit 373, a mux unit 374, a DAC unit 375, and a demux. A portion 376 is included. Since the sampling latch unit 371, the level shifter unit 372, and the holding latch unit 373 are the same as those described with reference to FIG. 7, a detailed description thereof will be omitted.

The mux unit 374 groups the data signals output from the holding latch unit 373 into a plurality of groups, and controls the output of the data signals included in each group.

Specifically, as illustrated, the data signals R1, G1, B1, .., Rk, Gk, and Bk output from the holding latch unit 373 are grouped into a red data group, a green data group, and a blue data group. Control the output of the red, green and blue data signals in each group.

First, red data signals R1 and... Rk are output to the DAC unit 375, and next green data signals G1 and .. Gk are output to the DAC unit 375. Signals B1 and .. Bk are output to the DAC unit 375. Accordingly, the DAC unit 375 is reduced by 1/3 compared with FIG. 7.

The DAC unit 375 first converts the red data signals R1,..., Rk into analog data voltages and outputs the same to the demux unit 376. The demux 376 outputs the input red data voltages to the source lines DL1, DL4,..., DLm-2 connected to the first output terminals.

Next, the DAC unit 375 converts the green data signals G1, ..., Gk into analog data voltages and outputs them to the demux unit 376. The demux 376 outputs the input green data voltages to the source lines DL2, DL6,..., DLm-1 connected to the second output terminals.

In the same manner, the source wirings DL3, DL7,..., DLm connected to the third output terminals of the demux 376 through the DAC unit 375 as the blue data signals B1 and .. Bk. Output to.

As a result, the data voltages output to the source wires DL1, DL2,... DLm correspond to the red data voltages corresponding to the output method of the source driver 370. 2), the next green data voltages are output to the corresponding source wirings DL2 and .DLm-1, and the blue data voltages are then output to the source wirings DL3 and .DLm.

FIG. 10 is a timing diagram illustrating a method of driving a liquid crystal display device by the source driver of FIG. 9.

1, 5 to 10, the source driver 370 converts the data signal of the horizontal line provided from the controller 211 into an analog data voltage during the 1H period, so that the source lines DL1, .. , DLm) (DATA_O).

In detail, the source driver 370 outputs the data voltage 1L_O of the first horizontal line during the initial H / 2 period among the 1H sections, and the gate circuit 230 includes the first gate signal corresponding to the first horizontal line. (G1t) is output, and the voltage generator 215 outputs the first common voltage VCOMt to the common electrode of the upper substrate. In this case, the source driver 370 outputs the data voltage 1L_O of the first horizontal line by grouping the red data voltage, the green data voltage, and the blue data voltage in the order of 3 × 1 MUX.

The first switching element TFTt of the transmission part Pt is turned on by the first gate signal G1t and receives a voltage corresponding to the data voltage transmitted to the source wiring DL. The first liquid crystal capacitor CLCt Transfer to a transparent electrode (TE), which is a first electrode. The first common voltage VCOMt is transmitted to the common electrode, which is the second electrode of the first liquid crystal capacitor CLCt.

As a result, the first liquid crystal capacitor CLCt is charged with a first pixel voltage VPt corresponding to a potential difference between the transparent electrode TE and the common electrode.

Next, the source driver 270 maintains the data voltage 1L_O of the first horizontal line being output during the later H / 2 period of the 1H section, and the gate circuit 230 has a second corresponding to the first horizontal line. The gate signal G1r is output, and the voltage generator 215 outputs the second common voltage VCOMr to the common electrode of the upper substrate.

That is, during the later H / 2 period, the first switching element TFTt of the transmission part Pt is turned off and the second switching element TFTr of the reflection part Pr is turned on.

As a result, the second switching element TFTr of the reflector Pr is turned on by the second gate signal G1r and receives a voltage corresponding to the data voltage transmitted to the source wiring DL. The first electrode of the capacitor CLCr is transferred to the reflective electrode RE. The second common voltage VCOMr is transmitted to the common electrode, which is the second electrode of the second liquid crystal capacitor CLCr.

As a result, the second liquid crystal capacitor CLCr is charged with the second pixel voltage VPr corresponding to the potential difference between the reflective electrode RE and the common electrode.

As illustrated, the first pixel voltage VPt charged in the first liquid crystal capacitor CLCt and the second pixel voltage VPr charged in the second liquid crystal capacitor CLCr are different from each other. The first common voltage VCOMt and the second common voltage VCOMr have a voltage difference between the peak voltage Tw of the VT curve and the peak voltage Rw of the VR curve shown in FIGS. 1A and 1B. Have substantially the same voltage difference.

For example, when the peak voltage Tw of the VT curve is 4.5V and the peak voltage Rw of the VR curve is 2.5V, the voltage difference between the first and second common voltages VCOMt and VCOMr is Δ. V) is 2V. When the liquid crystal layer is in the VA mode, an absolute value of the first common voltage VCOMt applied to the first liquid crystal capacitor CLCt of the transmission part Pt is applied to the second liquid crystal capacitor CLCr of the reflection part Pr. It is larger than the absolute value of the applied second common voltage VCOMr.

In the above description, the transmission part Pt is driven by turning on the first switching device TFTt connected to the first gate line GL1t during the initial H / 2 period, and the first switching device TFTt during the later H / 2 period. ) Is turned off and the second switching element TFTr connected to the second gate line GL1r is turned on to drive the reflector Pr.

However, like the second gate signals G1r and G2r shown in dashed lines, the first and second switching elements TFTt and TFTr are simultaneously turned on during the initial H / 2 period to transmit the Pt and the reflector. After driving (Pr), during the later H / 2 period, only the second switching element TFTr may be turned off and only the second switching element TFTr may be turned on to drive only the reflector Pr.

11A and 11B are graphs illustrating a V-T curve and a V-R curve in VA mode.

11A is a graph illustrating a V-T curve and a V-R curve in a conventional VA mode.

Referring to FIG. 11A, the V-T curve of the conventional VA mode gradually increases transmittance at approximately 1.5 V or more, and maintains the maximum transmittance at approximately 4.5 V or more. On the other hand, the existing V-R curve gradually increases the reflectance within the range of approximately 1.5V to 2.5V, and gradually decreases the reflectance at a voltage greater than approximately 2.5V.

Accordingly, the gamma curve combining the existing V-T and V-R curves gradually increases the transmittance before about 2.5V by the V-R curve and decreases the transmittance again from about 2.5V. Therefore, the desired white gradation image cannot be obtained.

11B is a graph illustrating a V-T curve and a V-R curve in a VA mode according to an embodiment of the present invention.

Referring to FIG. 11B, the V-T curve according to the embodiment gradually increases the transmittance from about 1.5V and maintains the maximum transmittance above about 4.5V. On the other hand, the improved V-R curve according to the embodiment gradually increases the reflectance from about 2V, so that the reflectance maintains the highest value at about 3.5V or more.

Accordingly, the gamma curve combining the V-T and V-R curves according to the embodiment gradually increases the transmittance from about 2V or more, and maintains the highest transmittance at about 4V or more. Therefore, an image of desired white gradation can be obtained.

As described above, according to the present invention, the voltage difference between the first common voltage applied to the first liquid crystal capacitor of the transmissive part and the second common voltage applied to the second liquid crystal capacitor of the reflector is determined by the peak voltage of the VT curve and the VR curve. The image quality can be improved by changing the voltage difference between the peak voltages.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (20)

A plurality of pixel portions, each pixel portion having a first switching element connected to a first gate line, a transmission portion having a first liquid crystal capacitor connected to the first switching element, a second switching element connected to a second gate line, and the second switching element; A liquid crystal display panel including a reflector having a second liquid crystal capacitor connected to a second switching element; And A first common voltage is applied to the first liquid crystal capacitor when the first switching element is turned on, and the second liquid crystal capacitor when the first switching element is turned off and the second switching element is turned on And a driver for applying a second common voltage to the liquid crystal display. The liquid crystal display of claim 1, wherein the first and second liquid crystal capacitors include a liquid crystal layer. Wherein the voltage difference between the first common voltage and the second common voltage is substantially equal to the voltage difference between the peak voltage of the voltage versus transmittance curve of the liquid crystal layer and the peak voltage of the voltage versus reflectance curve. The liquid crystal display device according to claim 2, wherein the liquid crystal layer is in a vertical alignment mode. The display device of claim 1, wherein the first switching device comprises: a first gate electrode connected to the first gate wiring; a first source electrode connected to a source wiring; and a first electrode connected to a transparent electrode which is a first electrode of the first liquid crystal capacitor. And a drain electrode. The display device of claim 4, wherein the second switching device comprises: a second gate electrode connected to the second gate wiring adjacent to the first gate wiring; a second source electrode connected to the source wiring; and a first of the second liquid crystal capacitor. And a second drain electrode connected to the reflective electrode as the electrode. The liquid crystal display of claim 5, wherein the first and second common electrodes of the first and second liquid crystal capacitors are electrically connected. The method of claim 5, wherein the driving unit A source driver outputting a data voltage to the source wiring; A gate driver configured to output first and second gate signals for activating the first and second gate lines; And A voltage generator configured to apply the first common voltage to the first liquid crystal capacitor when the first gate line is activated, and apply the second common voltage to the second liquid crystal capacitor when the first gate line is inactive. Liquid crystal display comprising a. The liquid crystal display of claim 7, wherein the first gate line is activated during an initial H / 2 period, and the second gate line is activated during a later H / 2 period. The liquid crystal display of claim 7, wherein the first gate line is activated during an initial H / 2 period, and the second gate line is activated during an 1H period. A plurality of pixel portions, each pixel portion having a first switching element connected to a first gate line, a transmission portion having a first liquid crystal capacitor connected to the first switching element, a second switching element connected to a second gate line, and the second switching element; In a driving device of a liquid crystal display device having a reflector having a second liquid crystal capacitor connected to a second switching element, A gate driver configured to output first and second gate signals for activating the first and second gate lines; And A voltage generator configured to apply the first common voltage to the first liquid crystal capacitor when the first gate line is activated, and apply the second common voltage to the second liquid crystal capacitor when the first gate line is inactive. And a drive device for the liquid crystal display device. The liquid crystal display of claim 1, wherein the first and second liquid crystal capacitors include a liquid crystal layer. Wherein the voltage difference between the first common voltage and the second common voltage is substantially the same as the voltage difference between the peak voltage of the voltage versus transmittance curve of the liquid crystal layer and the peak voltage of the voltage versus reflectance curve. . And a pixel portion including a transmissive portion having a first switching element and a first liquid crystal capacitor connected to the first switching element, and a reflecting portion having a second switching element and a second liquid crystal capacitor connected to the second switching element. In the driving method, Turning on the first switching element to charge the first liquid crystal capacitor with a first pixel voltage corresponding to a data voltage transferred from the first switching element and a first common voltage; And The first switching element is turned off and the second switching element is turned on to charge the second liquid crystal capacitor with a second pixel voltage corresponding to a data voltage transferred from the second switching element and a second common voltage. And driving the liquid crystal display device. The liquid crystal display of claim 12, wherein the first and second liquid crystal capacitors include a liquid crystal layer. The voltage difference between the first common voltage and the second common voltage is substantially the same as the voltage difference between the peak voltage of the voltage vs. the transmittance curve of the liquid crystal layer and the peak voltage of the voltage vs. the reflectance curve. . The liquid crystal display of claim 12, wherein the first switching element comprises: a first gate electrode connected to a first gate wiring; a first source electrode connected to a source wiring; and a first drain connected to a transparent electrode, which is a first electrode of the first liquid crystal capacitor. A method of driving a liquid crystal display device comprising an electrode. The display device of claim 14, wherein the second switching device comprises: a second gate electrode connected to the second gate wiring adjacent to the first gate wiring; a second source electrode connected to the source wiring; and a first of the second liquid crystal capacitor. And a second drain electrode connected to the reflective electrode, which is an electrode. The method of claim 15, wherein the charging of the first pixel voltage is performed. Activating the first gate wiring to apply a voltage corresponding to the data voltage applied to the source wiring to the transparent electrode of the first liquid crystal capacitor; and And applying the first common voltage to the first common electrode of the first liquid crystal capacitor. The method of claim 15, wherein the charging of the second pixel voltage is performed. Deactivating the first gate wiring; Activating the second gate wiring to apply a voltage corresponding to the data voltage applied to the source wiring to the reflective electrode of the second liquid crystal capacitor; and And applying the second common voltage to the first common electrode of the second liquid crystal capacitor. The method of claim 15, wherein the first gate line is activated during an initial H / 2 period. The method of claim 15, wherein the second gate line is activated during an initial H / 2 period. The method of claim 15, wherein the second gate line is activated during a 1H period.

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