KR20070034200A - Laminated package having adhesive layer and method for manufacturing same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated package having an adhesive layer and a method of manufacturing the same. A fan-out board on chip (BOC) package is a process of laminating and mounting a laminated package on a substrate. Thermal stresses in the bonds cause bending and solder joint failures.

The present invention provides a laminated package having a bonding layer interposed by thermocompression on the lower surface of the wiring board of both the semiconductor chip of the lower package and the resin sealing portion of the upper package, in order to solve the above problems. According to the present invention, since the thermocompressor adjusts the horizontality of the lower and upper packages in the process of thermally compressing the adhesive layer between the upper and upper packages, it is possible to suppress the occurrence of warpage due to the thermal stress acting during the lamination process. Solder joint failure can be prevented. In addition, even if warpage is generated in the lower and upper packages, the warpage may be corrected in the process of thermocompression bonding the adhesive layer. When the laminated package having the adhesive layer is solder-bonded to the mother substrate or the module substrate, the thermal stress acting is absorbed by the adhesive layer, so that warpage of the laminated package and poor solder joint can be suppressed.

BOC, Bending, Solder Bonding, Solder Open, Lamination

Description

Stack package having an adhesive layer and a method of manufacturing the same

1 is a cross-sectional view illustrating a laminated package in which board-on-chip packages according to the prior art are stacked.

FIG. 2 is a side view schematically illustrating a state in which warpage and solder bonding defects are generated in the multilayer package mounted on the module substrate of FIG. 1.

3 is an exploded perspective view showing a laminated package having an adhesive layer according to the first embodiment of the present invention.

4 is a cross-sectional view of FIG. 3.

FIG. 5 is a cross-sectional view illustrating adhesive layers used in the stacking package of FIG. 3.

6 to 8 are cross-sectional views illustrating each step according to the method of manufacturing the laminated package of FIG. 3.

9 is a cross-sectional view showing a laminated package having an adhesive layer having a filler according to a second embodiment of the present invention.

Description of the main parts of the drawing

110: BOC package 120: wiring board

121: upper surface 123: lower surface

125: window 130: semiconductor chip

131: center pad 140: bonding wire

150: resin sealing portion 151: first sealing portion

160: solder ball 170: adhesive layer

171: first adhesive layer 173: second adhesive layer

175: filler 191, 193: thermocompressor

200, 300: laminated package

The present invention relates to a laminated package and a method for manufacturing the same, and more particularly, to a laminated package having an adhesive layer in which a board on chip (BOC) package is laminated in three dimensions and a method for manufacturing the same.

With the trend toward thinner and shorter electronic devices, high-density and high-mounted packages are becoming important factors, and in the case of computers, large amounts of random access memory (RAM) and flash memory are increasing with increasing storage capacity. Like the Flash Memory, the size of the chip grows naturally, but the package is being studied to be smaller in accordance with the above requirements.

Here, various methods that have been proposed to reduce the size of a package include, for example, a multilayer package in which a plurality of semiconductor packages are stacked, a semiconductor module in which a plurality of semiconductor packages or a multilayer package is mounted on at least one surface of a wiring board, and the like. There is this.

A stacked package according to the prior art using a board on chip (BOC) package as a unit package is shown in FIG. 1. Referring to FIG. 1, the stack package 100 according to the related art has a structure in which two BOC packages 10 are stacked in three dimensions. At this time, the BOC package 10a positioned at the lower side is referred to as the lower package, and the BOC package 10b positioned at the upper side is referred to as the upper package.

The BOC package 10 has a fan-out in which the semiconductor chip 30 is mounted on the upper surface 21 of the wiring board and the solder balls 60 are formed on the edge of the lower surface 23 of the wiring board. Type of semiconductor package.

The stacking of the BOC package 10 is performed by a solder bonding process using the solder balls 60. That is, after the flux is applied to the solder ball 60 of the upper package, the solder ball 60 of the upper package is mounted on the wiring board 20 of the lower package, and then the solder ball 60 of the upper package is mounted. Melt is bonded to the wiring board 20 of the lower package.

In order to minimize the thickness of the stacked package 100, the BOC packages 10 may be stacked such that the resin encapsulation unit 50 of the upper package may be positioned close to the semiconductor chip 30 of the lower package.

In the stacked package 100, the BOC package 10 is laminated by a solder bonding process. The BOC packages 10 are stacked sequentially from the bottom up. The solder balls 60 of the upper package are bonded to the wiring board 20 of the lower package by melting the solder balls 60 while the BOC packages 10 are vertically aligned. This process is repeatedly performed to manufacture a laminated package 100.

By the way, in the manufacturing process of the conventional laminated package 100, in order to melt the solder ball 60 during the lamination process of the BOC package 10, heat of 200 ° C. or more is applied every time the lamination of the BOC package 10 is performed. All. As a result, thermal stress is applied to the component parts of the multilayer package 100, and thus many component parts are damaged.

For example, problems such as falling solder balls or shorting between neighboring solder balls occur. This problem is more severe as the number of unit packages stacked. This is especially true when the unit package is stacked in four or more layers.

Defects such as ball lifting due to warpage of the wiring board also occur. Since the components of the multilayer package, that is, the wiring board, the molding resin, and the semiconductor chip, have different thermal expansion coefficients, the wiring board may be bent due to thermal stress applied when the high temperature process such as the solder bonding process is performed several times. . Therefore, at both ends of the wiring board where the warpage phenomenon occurs relatively, the solder balls are excited, resulting in a poor connection with the lower wiring board.

Meanwhile, the laminate package, which is determined to be good in the conventional laminate package manufacturing step, is used by being mounted on a mother substrate by itself, or as shown in FIG. 2, by mounting on the module substrate 81 to form a part of the semiconductor module 80. Can be used as At this time, the stack packages 100 are mounted on one surface of the module substrate 81 by solder bonding.

As the semiconductor module 80 is also pointed out in the above-described laminated package 100, since the laminated package 100 is mounted on the module substrate 81 by a solder bonding method, the semiconductor package 80 has a problem due to thermal stress. . That is, at both ends of the multilayer package 100 in which the warpage phenomenon occurs relatively, the solder balls 60 are excited and a defect that cannot be solder-bonded to the lower module substrate 81 occurs.

Therefore, an object of the present invention is to be able to suppress the defect caused by the thermal stress acting in the process of laminating the BOC package.

Another object of the present invention is to be able to suppress the defects caused by the thermal stress acting in the process of mounting the laminated package on the mother substrate or module substrate.

In order to achieve the above object, the present invention provides a multilayer package in which a semiconductor chip is mounted on an upper surface of a wiring board, and unit packages in which solder balls are formed on a lower surface of the wiring board outside the semiconductor chip are stacked in three dimensions by solder balls. An adhesive layer is disposed between a semiconductor chip of a lower package and a wiring board of an upper package.

In this case, the BOC package may be used as the unit package, and the adhesive layer is interposed between the semiconductor chip of the lower package and the lower surface of the wiring board on both sides of the resin seal of the upper package.

In the laminated package according to the present invention, the adhesive layer comprises a first adhesive layer adhered to the lower surface of the wiring board, a first adhesive layer positioned below the first adhesive layer and adhered to the upper surface of the semiconductor chip and having adhesiveness at the melting temperature of the solder ball 2 adhesive layers. In this case, the second adhesive layer may include fillers having a size capable of maintaining a gap between the semiconductor chip and the resin encapsulation portion positioned up and down with respect to the adhesive layer.

The present invention provides a method for producing a laminated package having an adhesive layer. That is, (a) preparing a unit package in which a semiconductor chip is mounted on an upper surface of a wiring board and solder balls are formed on a lower surface of the wiring board outside the semiconductor chip; (b) adhering an adhesive layer to the lower surface of the wiring boards of the unit packages to be stacked on the lowermost package among the unit packages; (c) mounting the unit packages in which the adhesive layer is formed on the lowermost package in three dimensions; (d) thermally compressing the unit packages to solder-bond the unit packages through solder balls and adhering the lower surface of the adhesive layer to the back surface of the semiconductor chip.

In the method of manufacturing a laminated package according to the present invention, in step (b), the adhesive layer is bonded to the lower surface of the wiring board by a thermocompression bonding method.

In the method of manufacturing a laminated package according to the present invention, the adhesive layer is bonded to the lower surface of the wiring board and adhered to the first adhesive layer having adhesiveness in the step (b) proceeding at 200 ° C. or lower, and the upper surface of the semiconductor chip. It includes a second adhesive layer having an adhesive in step (d) to proceed at the melting temperature of the solder ball.

In the method of manufacturing a laminated package according to the present invention, the second adhesive layer may include fillers of a size capable of maintaining a gap between the semiconductor chip and the resin encapsulation portion positioned up and down with respect to the adhesive layer.

In the method of manufacturing a laminated package according to the present invention, step (d) is performed in a state in which heat and a constant pressure of 200 ° C to 260 ° C are applied to the adhesive layer in an air chamber of 180 ° C to 260 ° C.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

First embodiment

3 is an exploded perspective view showing the laminated package 200 having the adhesive layer 170c according to the first embodiment of the present invention. 4 is a cross-sectional view of FIG. 3.

3 and 4, the stack package 200 according to the first embodiment has a structure in which two BOC packages 110 are stacked in three dimensions through the adhesive layer 170c.

The BOC package 110 has a fan-out in which the semiconductor chip 130 is mounted on the upper surface 121 of the wiring board 120 and the solder balls 160 are formed on the edge of the lower surface 123 of the wiring board. -out) type semiconductor package. That is, the BOC package 110 may include the semiconductor chip 130 on the upper surface 121 of the wiring board so that the center pad 131 of the semiconductor chip is exposed on the window 125 formed at the center portion of the wiring board 120. The active surface has a bonded structure. The center pad 131 and the wiring board 120 are connected to each other by a bonding wire 140 through the window 125 of the wiring board. The center pad 131 and the bonding wire 140 exposed to the window 125 are protected by a resin encapsulation unit 150 formed of a soft silicone-based molding resin on the lower surface 123 of the wiring board. The solder balls 160 for external connection are formed on the lower surface 123 of the wiring board outside the resin encapsulation part 150.

In this case, the semiconductor chip 130 adhered to the upper surface 121 of the wiring board is exposed to the outside, and the solder ball 160 may be laminated on the mother substrate, the module substrate, or another BOC package. It is formed higher than).

In particular, the adhesive layer 170c is interposed by thermocompression bonding between the semiconductor chip 130 of the lower package and the wiring board 120 of the upper package. Preferably, the semiconductor chip 130 of the lower package and the resin encapsulation portion of the upper package ( It is interposed on the lower surface of both wiring boards 120.

The adhesive layer 170c according to the first embodiment is disposed on the first adhesive layer 171 adhered to the bottom surface 123 of the wiring board, and is disposed below the first adhesive layer 171 and adhered to the back surface of the semiconductor chip 130. The second adhesive layer 173 is included. In this case, an adhesive having an adhesive property at 200 ° C. or less may be used as the first adhesive layer 171, and an adhesive may be used at 200 ° C. to 260 ° C., which is a melting temperature of the solder ball 160, as the second adhesive layer 173. Adhesives can be used. As a material of the first and second adhesive layers 171 and 173, an adhesive tape or a liquid adhesive may be used.

As the adhesive layer, adhesive layers 170a, 170b, 170c, 170d, as shown in FIG. 5, may be used. That is, the second adhesive layer 173 including the fillers 175 as illustrated in FIG. 5D, including the adhesive layer 170c according to the first exemplary embodiment as illustrated in FIG. 5C. An adhesive layer 170d may be used. Alternatively, an adhesive layer 170a composed of one adhesive as shown in FIG. 5A is used, or an adhesive layer including fillers 175 in the adhesive 173 as shown in FIG. 5B. 170b may be used. In this case, the filler 175 may preferably use fillers having a size capable of maintaining a gap between the resin encapsulation portion and the semiconductor chip, which are positioned up and down with respect to the adhesive layers 170b and 170d. It is preferable to use the material of a 2nd contact bonding layer as an adhesive agent of the contact bonding layers 170a and 170b of FIG. 5 (a) and (b).

The adhesive layer 170c may be solder-bonded according to the stacking of the BOC package 110, and maintain the gap at which the semiconductor chip 130 of the lower package does not exert mechanical stress on the resin encapsulation 150 of the upper package. It is preferable to form to the thickness which is.

Therefore, since the adhesive layer 170c is bonded to the lower surface of the semiconductor chip 130 of the lower package and the lower surface of the wiring board 120 on both sides of the resin encapsulation part 150 of the upper package, the lower and upper packages ( It is possible to suppress occurrence of warpage of 110a and 110b. Moreover, it can suppress that a solder joint defect arises by this.

When the laminated package 200 is solder bonded to the mother substrate or the module substrate, the thermal stress acting is absorbed by the adhesive layer 170c, thereby ensuring the solder joint reliability of the laminated package 200.

Meanwhile, the first embodiment discloses an example in which two BOC packages 110 are stacked, but is not limited thereto. Three or more BOC packages 110 may be interposed between the BOC packages 110 through an adhesive layer 170c. ) Can be laminated, of course.

A method of manufacturing the laminated package according to the first embodiment will be described with reference to FIGS. 6 to 8 as follows. The same reference numerals denote the same components throughout the drawings.

First, starting from the step of preparing the lower package, the upper package and the adhesive layer to proceed the lamination process.

Next, as shown in Figure 6, the step of adhering the adhesive layer 170c to the lower surface of the upper package (110b). The adhesive layer 170c is bonded to the bottom surface 123 of the wiring boards on both sides of the resin encapsulation part 150 by thermocompression bonding with the thermocompressor 191. In the thermocompression bonding process, the adhesive layer 170c is adhered to the lower surface 123 of the wiring board by applying a predetermined pressure at 200 ° C. or less at which melting of the solder ball 160 does not occur. At this time, the adhesive layer 170c is bonded to the region between the solder ball 160 and the resin encapsulation part 150.

In addition, since the horizontalness of the upper package 110b is adjusted in the process of thermocompressing the upper package 110b with the thermocompressor 191 to bond the adhesive layer 170c, if the bending occurs in the upper package 110b, the adhesive layer In the process of bonding the (170c) can be expected to effect the correction of the warpage.

Next, as shown in FIG. 7, the upper package 110b is aligned and mounted on the upper portion of the lower package 110a. That is, after the flux 161 is applied to the upper surface 121 of the lower substrate to which the solder balls 160 of the upper package are to be bonded, the upper package 110b is aligned and mounted on the upper portion of the lower package 110a.

In this case, the flux 161 may be applied to the solder balls 160 of the upper package and then aligned and mounted on the upper portion of the lower package 110a.

Next, as shown in FIG. 8, the step of stacking the BOC package 110 by thermocompression is performed. That is, the semi-finished product having the upper package 110b mounted on the lower package 110a is loaded into the air chamber. Then, the inside of the air chamber is heated above the melting temperature of the solder ball 160 to heat the solder ball 160 in a deformable state, and then the lower and upper packages 110a and 110b are heated using a thermocompressor 193 heated to a predetermined temperature. ) Is thermally compressed and solder bonded to each other through the solder ball 160, and the lower surface of the adhesive layer 170c is attached to the back surface of the semiconductor chip 130 of the lower package.

At this time, the inside of the air chamber is heated to 180 ° C to 260 ° C, the thermocompressor 193 is a thermocompression process is performed in a state heated to 200 ° C to 260 ° C. That is, the thermocompression process is performed in a temperature range in which the solder bonding process and the adhesive layer bonding process may be simultaneously performed by one thermocompression process.

In order to bond the adhesive layer 170c, the lower and upper packages 110a and 110b are laminated in the process of thermocompression bonding the lower and upper packages 110a and 110b with the thermocompressor 193, so that the lamination is performed. In this process, the bending caused by the thermal stress can be suppressed to prevent the occurrence of solder joint defects. In addition, if warpage occurs in the lower and upper packages 110 and 110b, the warpage may be corrected in the process of thermocompressing the adhesive layer 170c.

In addition, since the adhesive layer 170c is bonded to the lower surface of the semiconductor chip 130 of the lower package and the lower surface of the wiring board 120 on both sides of the resin encapsulation part 150 of the upper package, the lower and upper packages ( It is possible to suppress occurrence of warpage of 110a and 110b. Moreover, it can suppress that a solder joint defect arises by this.

Finally, by unloading the semi-finished product after the thermocompression process is completed in the air chamber, the laminated package 200 as shown in FIG. 4 may be obtained.

Second embodiment

In the first exemplary embodiment of the present invention, an example in which the adhesive layer 170c shown in FIG. 5B is used as the adhesive layer is disclosed, but as shown in FIGS. 5B and 9, the filler 175 The laminated package 300 may be implemented through the adhesive layer 170b having the. Since the laminated package 300 according to the second embodiment has the same structure as the first embodiment except that the adhesive layer 170b having the filler 175 is interposed, the adhesive package 170b will be described.

The adhesive layer 170b has a structure in which the fillers 175 are included in the adhesive 173, and the filler 175 has the semiconductor chip 130 and the resin encapsulation part 150 positioned up and down with respect to the adhesive layer 173. It is preferable to use a filler 175 of a size that can maintain the spacing between. Therefore, due to the fillers 175 included in the adhesive layer 170b, mechanical interference between the semiconductor chip 130 and the resin encapsulation 150 may be suppressed in the process of stacking the BOC package 110. have.

In addition, the fillers 175 may more stably serve to compensate for the warpage of the BOC package 110 in the process of adhering the adhesive layer 170b to the upper package 110b or in the process of stacking the BOC packages 110. To be able.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. Meanwhile, although the BOC package is described as an example in the embodiment of the present invention, the present invention is not limited thereto, and a fan-out ball grid array package may be used as the unit package.

Therefore, according to the present invention, since the adhesive layer is interposed by thermocompression on the lower surface of the semiconductor chip of the lower package and the wiring boards on both sides of the resin encapsulation part of the upper package, the adhesive layer is subjected to the thermal stress acting in the solder bonding process performed with the thermal compression. It is possible to suppress occurrence of warping of the lower and upper packages. Moreover, it can suppress that a solder joint defect arises by this. That is, since the thermocompressor adjusts the horizontality of the lower and upper packages in the process of thermocompressing the adhesive layer between the upper and upper packages, the warpage may be corrected in the process of adhering the adhesive layer even if the lower and upper packages are warped.

In addition, since the adhesive layer absorbs the thermal stress applied when soldering the laminated package to the mother substrate or the module substrate, the solder joint reliability of the laminated package can be secured.

Claims (9)

In a laminated package in which a semiconductor chip is mounted on an upper surface of a wiring board, and unit packages in which solder balls are formed on a lower surface of the wiring board outside the semiconductor chip are stacked three-dimensionally through the solder ball. An adhesive layer interposed between the semiconductor chip of the lower package and the wiring board of the upper package. The method of claim 1, wherein the unit package, A wiring board having a window formed in the center portion thereof; A semiconductor chip bonded to an upper surface of the wiring board such that center pads are exposed to the window; A bonding wire electrically connecting the center pad and the wiring board through the window; A resin encapsulation portion for sealing a center portion of a lower surface of the wiring board around the window to protect the center pads and a bonding wire exposed to the window; A plurality of solder balls formed on a lower surface of the wiring board outside the semiconductor chip; Including; And the adhesive layer is interposed between the semiconductor chip of the lower package and the lower surface of the wiring board on both sides of the resin encapsulation part of the upper package. The method according to claim 1 or 2, wherein the adhesive layer, A first adhesive layer adhered to a lower surface of the wiring board; And a second adhesive layer disposed below the first adhesive layer and adhered to an upper surface of the semiconductor chip, wherein the second adhesive layer has adhesiveness at a melting temperature of the solder balls. The stack package according to claim 3, wherein the second adhesive layer includes fillers having a size capable of maintaining a gap between the semiconductor chip and the resin encapsulation portion positioned up and down about the adhesive layer. (a) preparing a unit package in which a semiconductor chip is mounted on an upper surface of a wiring board and solder balls are formed on a lower surface of the wiring board outside the semiconductor chip; (b) adhering an adhesive layer to lower surfaces of the wiring boards of the unit packages to be stacked on the lowermost package among the unit packages; (c) mounting unit packages in which the adhesive layer is formed on the lowermost package in three dimensions; (d) thermally compressing the unit packages to solder-bond the unit packages through the solder balls and attaching the lower surface of the adhesive layer to the back surface of the semiconductor chip; Method of preparation. The method of claim 5, wherein the adhesive layer is bonded to the lower surface of the wiring board by a thermocompression bonding method in the step (b). The method of claim 6, wherein the adhesive layer, A first adhesive layer adhered to a lower surface of the wiring board and having adhesiveness in the step (b) which proceeds at 200 ° C. or less; And a second adhesive layer adhered to an upper surface of the semiconductor chip, the adhesive layer having adhesiveness in the step (d) performed at the melting temperature of the solder ball. 2. The multilayer package of claim 7, wherein the second adhesive layer includes fillers having a size that can maintain a gap between the semiconductor chip and the resin encapsulation portion positioned up and down about the adhesive layer. Manufacturing method. The method of claim 5, wherein the step (d) is performed in a state in which heat and a constant pressure of 200 ° C. to 260 ° C. are applied to the adhesive layer in an air chamber at 180 ° C. to 260 ° C. 10. The manufacturing method of the laminated package which has an adhesive layer to make.

Images