KR20070030519A - Semiconductor package with fixing means of bonding wires - Google Patents

Semiconductor package with fixing means of bonding wires Download PDF

Info

Publication number
KR20070030519A
KR20070030519A KR1020050085244A KR20050085244A KR20070030519A KR 20070030519 A KR20070030519 A KR 20070030519A KR 1020050085244 A KR1020050085244 A KR 1020050085244A KR 20050085244 A KR20050085244 A KR 20050085244A KR 20070030519 A KR20070030519 A KR 20070030519A
Authority
KR
South Korea
Prior art keywords
bonding wire
fixing means
bonding
wire fixing
substrate
Prior art date
Application number
KR1020050085244A
Other languages
Korean (ko)
Inventor
김현중
김광은
김태형
이영근
한선길
윤석목
나선정
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020050085244A priority Critical patent/KR20070030519A/en
Publication of KR20070030519A publication Critical patent/KR20070030519A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48996—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/48998—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 본딩 와이어 고정 수단을 갖는 반도체 패키지에 관한 것으로, 본딩 와이어가 다른 본딩 와이어와 접촉되어 단락이 발생되는 것을 방지하기 위한 것이다. 본 발명은 기판에 실장되는 반도체 칩과, 기판과 반도체 칩을 전기적으로 연결하기 위한 본딩 와이어, 본딩 와이어를 고정하기 위한 본딩 와이어 고정 수단을 포함하여 구성된다. 여기서, 본딩 와이어 고정 수단은 본딩 와이어를 수직으로 가로지르며 본딩 와이어의 상부면에 접착되고, 점착성을 갖는 절연성 수지로 이루어지며, 원통의 막대 형상이나 직사각으로 길게 형성된 띠 형상으로 형성되기 때문에, 본딩 와이어와 접착되어 본딩 와이어의 움직임을 억제할 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package having a bonding wire fixing means, which is intended to prevent a short circuit from being caused by contact of the bonding wire with another bonding wire. The present invention comprises a semiconductor chip mounted on a substrate, a bonding wire for electrically connecting the substrate and the semiconductor chip, and bonding wire fixing means for fixing the bonding wire. Here, the bonding wire fixing means is bonded to the upper surface of the bonding wire vertically across the bonding wire, is made of an insulating resin having an adhesive, and is formed in a cylindrical rod shape or a strip formed in a rectangular shape, the bonding wire It can bond with and can suppress the movement of a bonding wire.

따라서, 본딩 와이어의 단락으로 인한 불량을 줄일 수 있어 수율이 높아지는 효과가 있다.Therefore, the defect due to the short circuit of the bonding wire can be reduced and the yield is increased.

본딩 와이어, 단락, 절연 수지, 와이어 볼, 칩 적층형 패키지 Bonding Wire, Short Circuit, Insulation Resin, Wire Ball, Chip Stacked Package

Description

본딩 와이어 고정 수단을 갖는 반도체 패키지{SEMICONDUCTOR PACKAGE WITH FIXING MEANS OF BONDING WIRES}Semiconductor package with bonding wire fixing means {SEMICONDUCTOR PACKAGE WITH FIXING MEANS OF BONDING WIRES}

도 1a는 종래 기술에 따른 일반적인 칩 적층형 패키지를 나타내는 개략적인 단면도.1A is a schematic cross-sectional view illustrating a conventional chip stack package according to the prior art.

도 1b는 도 1a의 일부를 확대하여 나타내는 단면도.FIG. 1B is an enlarged cross-sectional view of a portion of FIG. 1A. FIG.

도 2a는 본 발명의 실시예에 따른 칩 적층형 패키지를 개략적으로 나타내는 단면도.2A is a schematic cross-sectional view of a chip stacked package according to an embodiment of the present invention.

도 2b는 도 2a의 칩 적층형 패키지를 개략적으로 나타내는 평면도.FIG. 2B is a plan view schematically illustrating the chip stacked package of FIG. 2A; FIG.

도 3a는 본 발명의 다른 실시예에 따른 칩 적층형 패키지를 나타내는 개략적인 단면도.Figure 3a is a schematic cross-sectional view showing a chip stack package according to another embodiment of the present invention.

도 3b는 3a의 칩 적층형 패키지를 개략적으로 나타내는 평면도.3B is a plan view schematically illustrating the chip stacked package of 3A.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

10, 110 : 반도체 칩 14, 114 : 본딩 패드(bonding pad) 10, 110: semiconductor chip 14, 114: bonding pad

20, 120 : 기판 21, 121 : 기판 패드20, 120: substrate 21, 121: substrate pad

30, 130 : 접착제 40, 140 : 본딩 와이어(bonding wire)30, 130: adhesive 40, 140: bonding wire

50, 150 : 범프(bump) 60, 160 : 와이어 볼(wire ball)50, 150 bump 60, 160 wire ball

80 : 와이어 코팅 물질(wire coating material)80: wire coating material

90, 190 : 몰딩 수지 100, 200, 300 : 칩 적층형 패키지 90, 190: molding resin 100, 200, 300: chip lamination package

110 내지 113 : 제 1 내지 제 3 반도체 칩 110 to 113: first to third semiconductor chips

141 내지 143 : 제 1 내지 제 3 본딩 와이어141 to 143: first to third bonding wires

180, 280 : 본딩 와이어 고정 수단180, 280: bonding wire fixing means

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 본딩 와이어가 다른 본딩 와이어와 접촉되어 단락이 발생되는 것을 억제할 수 있는 본딩 와이어 고정 수단을 갖는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having bonding wire fixing means capable of suppressing occurrence of a short circuit due to contact of the bonding wire with another bonding wire.

최근 반도체 산업의 발전과 사용자의 요구에 따라 전자 기기는 지속적으로 소형화 및 경량화되고 있으며, 이에 따라 전자기기에 탑재되는 반도체 소자들도 소형화, 경량화, 및 고집적화되고 있다. Recently, according to the development of the semiconductor industry and the needs of users, electronic devices are continuously miniaturized and lightened, and accordingly, semiconductor devices mounted on electronic devices are also miniaturized, lightened, and highly integrated.

이와 같은 흐름을 타고 개발된 패키지의 일례로 복수의 반도체 칩을 수직으로 적층하여 하나의 개별 패키지로 구현한 칩 적층형 패키지(chip stack type package)를 들 수 있다. 칩 적층형 패키지는 단일 칩 패키지를 여러 개 적층한 패키지 적층형 구조보다 크기, 무게 및 실장면적에서 소형화와 경량화에 유리하며, 동일한 크기의 개별 패키지에 비하여 용량이 증가되어 고집적화에 유리하다. An example of a package developed through such a flow includes a chip stack type package in which a plurality of semiconductor chips are vertically stacked and implemented as one individual package. The chip stack package is advantageous in miniaturization and light weight in size, weight, and mounting area, compared to a package stack structure in which a single chip package is stacked several times, and has an increased capacity compared to individual packages of the same size, which is advantageous for high integration.

그런데, 이러한 칩 적층형 패키지는 다수 개의 반도체 칩이 적층되기 때문에 최상부에 위치한 반도체 칩과 기판을 연결하는 본딩 와이어의 길이가 지나치게 길 어지게 된다. 이로 인하여 반도체 칩들을 성형수지로 봉지하는 몰딩 공정이 진행될 때, 본딩 와이어가 아래로 처지거나(wire sagging), 본딩 와이어가 측면으로 넘어지는(wire sweeping) 경우가 발생된다.However, in the chip stack package, since a plurality of semiconductor chips are stacked, the length of the bonding wire connecting the semiconductor chip and the substrate positioned at the top thereof becomes too long. As a result, when a molding process of encapsulating semiconductor chips with a molding resin is performed, a bonding wire may be sag down, or the bonding wire may be swept to the side.

이 경우, 본딩 와이어와 칩 사이 또는 이웃하는 본딩 와이어들 사이에 단락이 발생될 수 있기 때문에, 이러한 문제점을 해결하기 위해서 본딩 와이어와 와이어 볼(wire ball), 즉 본딩 와이어가 반도체 칩과 기판에 접속되는 부분에 와이어 코팅 물질(wire coating material)을 주입하는 방법이 이용되고 있다.In this case, since a short circuit may occur between the bonding wire and the chip or between neighboring bonding wires, in order to solve this problem, the bonding wire and the wire ball, that is, the bonding wire are connected to the semiconductor chip and the substrate. A method of injecting a wire coating material into the portion to be used is used.

그렇지만, 이와 같은 와이어 코팅 물질을 이용하는 방법을 이용하더라도, 본딩 와이어의 와이어 볼 들뜸(wire ball lift) 현상이나, 와이어 볼과 와이어의 연결부분에 미세 크랙이 발생되는 등의 문제가 발생되고 있다. 이하, 도면을 참조하여 이에 관하여 보다 상세하게 설명한다.However, even when using such a method of using a wire coating material, problems such as wire ball lift phenomenon of the bonding wire or fine cracks are generated in the connection portion between the wire ball and the wire. Hereinafter, this will be described in more detail with reference to the drawings.

도 1a는 종래 기술에 따른 일반적인 칩 적층형 패키지를 나타내는 개략적인 단면도이고, 도 1b는 도 1a의 일부를 확대하여 나타내는 단면도로서, 와이어 볼 들뜸 현상을 보여준다.FIG. 1A is a schematic cross-sectional view illustrating a conventional chip stacked package according to the related art, and FIG. 1B is an enlarged cross-sectional view of a portion of FIG. 1A, illustrating a wire ball lifting phenomenon.

먼저 도 1a를 참조하면, 칩 적층형 패키지(200)는 기판(20), 다수개의 반도체 칩(10), 본딩 와이어(40), 와이어 코팅 물질(80), 및 몰딩 수지(90)를 포함하여 구성된다.Referring first to FIG. 1A, the chip stacked package 200 includes a substrate 20, a plurality of semiconductor chips 10, a bonding wire 40, a wire coating material 80, and a molding resin 90. do.

다수개의 반도체 칩(10)들은 기판(20) 상에 접착제(30)를 이용하여 적층되어 있다.The plurality of semiconductor chips 10 are stacked on the substrate 20 using the adhesive 30.

본딩 와이어(40)는 일단이 반도체 칩(10)의 본딩 패드(14)와 연결되고, 타단 이 기판(20)의 기판 패드(21)에 접속되어 반도체 칩(10)과 기판(20)을 전기적으로 연결한다. One end of the bonding wire 40 is connected to the bonding pad 14 of the semiconductor chip 10, and the other end thereof is connected to the substrate pad 21 of the substrate 20 to electrically connect the semiconductor chip 10 and the substrate 20. Connect with

와이어 코팅 물질(80)은 도시되지 않은 디스펜서를 통해 주입되며, 주입 후 경화 과정을 통해 경화되어 본딩 와이어(40)가 아래로 처지거나 옆으로 쓰러지지 않도록 고정시킨다.The wire coating material 80 is injected through a dispenser, not shown, and is cured through the curing process after the injection to fix the bonding wire 40 so that it does not sag down or fall sideways.

몰딩 수지(90)로 반도체 칩(10) 및 기판(20)의 상부면을 밀봉하여 외부 환경으로부터 반도체 칩(10)을 보호한다. The upper surface of the semiconductor chip 10 and the substrate 20 is sealed with the molding resin 90 to protect the semiconductor chip 10 from an external environment.

그런데 이와 같은 종래의 칩 적층형 패키지(100)의 경우, 와이어 코팅 물질(80)의 주입 시 와이어 코팅 물질(80)의 점성과 본딩 와이어(40) 사이의 표면 장력으로 인해 범프(50) 및 와이어 볼(60)을 완전히 덮지 못하고 본딩 와이어(40)와 몰딩 수지(90)가 형성하는 면을 따라 와이어 코팅 물질(80)의 경계면이 형성된다. However, in the conventional chip stack package 100, the bump 50 and the wire ball may be formed due to the viscosity of the wire coating material 80 and the surface tension between the bonding wires 40 when the wire coating material 80 is injected. The interface of the wire coating material 80 is formed along the surface formed by the bonding wire 40 and the molding resin 90 without completely covering 60.

이러한 경우, 본딩 와이어(40), 와이어 코팅 물질(80), 및 몰딩 수지(90)의 열 팽창 계수가 각각 다르기 때문에, 이후 계속 진행되는 패키지 공정 과정에서 이들 상호간의 전단 응력(shear stress)으로 인해, 와이어 볼 들뜸(wire ball lift) 현상(70)이나 와이어 볼과 와이어의 연결부분에 미세 크랙이 발생된다. 그리고 이로 인하여 반도체 칩(10)과 기판(20) 사이의 전기적 접속 불량이 발생되어 신뢰성이 낮아지는 문제가 발생된다.In this case, since the thermal expansion coefficients of the bonding wire 40, the wire coating material 80, and the molding resin 90 are different, the shear stresses between them may be caused by subsequent package processes. , Wire ball lift phenomenon (70) or a fine crack is generated in the connection portion of the wire ball and the wire. As a result, a poor electrical connection between the semiconductor chip 10 and the substrate 20 occurs, resulting in a problem of low reliability.

따라서 본 발명의 목적은 전술된 바와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 와이어 코팅 물질을 사용하지 않고 본딩 와이어가 다른 본딩 와이어 와 접촉되어 단락이 발생되는 것을 방지할 수 있는 본딩 와이어 고정 수단을 갖는 반도체 패키지를 제공하는 데에 있다. Accordingly, an object of the present invention is to solve the problems of the prior art as described above, and to provide a bonding wire fixing means capable of preventing the bonding wire from contacting other bonding wires and causing a short circuit without using a wire coating material. It is providing the semiconductor package which has.

상기 목적을 달성하기 위한 본 발명의 본딩 와이어 고정 수단을 갖는 반도체 패키지는 일면에 기판 패드가 형성되어 있는 기판, 기판에 실장되고, 일면에 본딩 패드가 형성되어 있는 적어도 하나 이상의 반도체 칩, 본딩 패드와 기판 패드를 전기적으로 연결하는 다수의 본딩 와이어, 및 본딩 와이어를 수직으로 가로지르며 본딩 와이어의 상부면에 접착되는 절연성의 본딩 와이어 고정 수단을 포함하여 형성되는 것이 특징이다. 이 경우, 본딩 와이어 고정 수단을 수지(樹脂)로 이루어질 수 있다. The semiconductor package having the bonding wire fixing means of the present invention for achieving the above object is at least one semiconductor chip, the bonding pad is mounted on the substrate, the substrate is formed on one surface, the bonding pad is formed on one surface and And a plurality of bonding wires electrically connecting the substrate pads, and insulating bonding wire fixing means vertically across the bonding wires and bonded to an upper surface of the bonding wires. In this case, the bonding wire fixing means may be made of resin.

또한, 본 발명에 있어서, 본딩 와이어 고정 수단은 원통의 막대 형상 또는 직사각으로 길게 형성된 띠 형상 중 어느 하나인 것이 바람직하며, 적어도 하나 이상의 반도체 칩 중 최상부에 적층되는 반도체 칩과 연결되는 본딩 와이어에 접착되는 것이 바람직하다. 이때, 본딩 와이어 고정 수단은 다수개가 적어도 하나 이상의 반도체 칩과 연결되는 모든 본딩 와이어에 각각 접착되거나, 선택적으로 접착되는 것 중 어느 하나일 수 있다. In addition, in the present invention, the bonding wire fixing means is preferably any one of a cylindrical rod shape or a strip shape formed in a rectangular shape, and is bonded to a bonding wire connected to a semiconductor chip stacked on top of at least one semiconductor chip. It is desirable to be. In this case, the bonding wire fixing means may be any one of a plurality of bonding to each bonding wire connected to at least one or more semiconductor chips, or selectively bonded.

더하여 본 발명에 있어서, 본딩 와이어 고정 수단은 표면에 점착성을 갖는 물질이 도포되어 있는 것이 바람직하며, 또한 열에 의해 본딩 와이어와 접착될 수 있다. In addition, in the present invention, the bonding wire fixing means is preferably coated with a material having a tacky property on the surface thereof, and can be bonded to the bonding wire by heat.

이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설 명하도록 한다. 첨부 도면에 있어서 일부 구성요소는 도면의 명확한 이해를 돕기 위해 다소 과장되거나 개략적으로 도시되거나 또는 생략되었으며, 각 구성요소의 실제 크기가 전적으로 반영된 것은 아니다. 또한, 도면을 통틀어 동일한 구성요소 또는 대응하는 구성요소는 동일한 참조 번호를 사용하였다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, some of the components are somewhat exaggerated, schematically illustrated or omitted to facilitate a clear understanding of the drawings, and the actual size of each component is not entirely reflected. In addition, the same components or corresponding components throughout the drawings used the same reference numerals.

도 2a는 본 발명의 실시예에 따른 칩 적층형 패키지를 개략적으로 나타내는 단면도이고, 도 2b는 도 2a의 칩 적층형 패키지를 개략적으로 나타내는 평면도이다.2A is a cross-sectional view schematically illustrating a chip stacked package according to an exemplary embodiment of the present invention, and FIG. 2B is a plan view schematically illustrating the chip stacked package of FIG. 2A.

도 2a 및 도 2b를 참조하면, 본 발명의 칩 적층형 패키지(200)는, 제 1 내지 제 3 반도체 칩(110; 111, 112, 113), 기판(120), 제 1 내지 제 3 본딩 와이어(140; 141, 142, 143), 몰딩 수지(190), 및 본딩 와이어 고정 수단(180)을 포함하여 구성된다.2A and 2B, the chip stack package 200 according to the present invention may include a first to third semiconductor chip 110 (111; 112, 113), a substrate 120, and a first to third bonding wire ( 140; 141, 142, 143, molding resin 190, and bonding wire fixing means 180.

기판(120)의 일면에 실장되는 반도체 칩(110)들은 상면의 가장자리에 다수의 본딩 패드(114)들이 형성되어 있으며, 이를 통해 본딩 와이어(140)와 연결된다. 본 실시예에서는 제 1 내지 제 3 반도체 칩(111, 112, 113)이 차례로 수직으로 적층되어 있는 칩 적층형 패키지(200)를 예시하였지만, 이외에도 한 개 또는 두 개의 반도체 칩(110)으로 형성되거나 네 개 이상의 반도체 칩(110)들이 적층될 수도 있다. 이때, 제 1 내지 제 3 반도체 칩(111, 112, 113)들은 그 사이에 개재되는 접착제(130)에 의해 서로 접착된다. The semiconductor chips 110 mounted on one surface of the substrate 120 have a plurality of bonding pads 114 formed at edges of the upper surface thereof, and are connected to the bonding wires 140 through the plurality of bonding pads 114. In the present exemplary embodiment, the chip stacked package 200 in which the first to third semiconductor chips 111, 112, and 113 are sequentially stacked vertically is illustrated, but in addition, one or two semiconductor chips 110 may be formed. More than one semiconductor chip 110 may be stacked. In this case, the first to third semiconductor chips 111, 112, and 113 are adhered to each other by the adhesive 130 interposed therebetween.

기판(120)은 인쇄회로기판(PCB), 리드 프레임 또는 유연성(flexible) 기판일 수 있으며, 반도체 칩(110)들이 실장되는 면에 본딩 와이어(140)가 연결되기 위한 기판 패드(121)가 형성되어 있다. The substrate 120 may be a printed circuit board (PCB), a lead frame, or a flexible substrate, and a substrate pad 121 for connecting the bonding wire 140 to a surface on which the semiconductor chips 110 are mounted is formed. It is.

제 1 내지 제 3 본딩 와이어(141, 142, 143)는 제 1 내지 제 3 반도체 칩(111, 112, 113)과 대응되도록 일단이 본딩 패드(114)에 연결되고, 타단이 기판 패드(121)에 연결된다. 본 실시예에서는 반도체 칩(110)의 본딩 패드(114)에 범프(150)를 형성한 뒤, 기판(120)의 기판 패드(121)에 와이어 볼(160)을 본딩한 후 본딩 와이어(140)를 범프(150)와 연결하는 범프 리버스 본딩(bump reverse bonding)방식을 통해 본딩된 본딩 와이어(140)를 예시하였지만, 이와 더불어 일반적인 와이어 본딩 방식에도 본 발명을 적용할 수 있다.One end of the first to third bonding wires 141, 142, and 143 is connected to the bonding pad 114 so as to correspond to the first to third semiconductor chips 111, 112, and 113, and the other end thereof is the substrate pad 121. Is connected to. In the present exemplary embodiment, after the bumps 150 are formed on the bonding pads 114 of the semiconductor chip 110, the wire balls 160 are bonded to the substrate pads 121 of the substrate 120, and then the bonding wires 140 are bonded. Although the bonding wire 140 is bonded through a bump reverse bonding method for connecting the bump 150 to the bump 150, the present invention may also be applied to a general wire bonding method.

몰딩 수지(190)는 기판(120)의 상부에 위치하고 있는 반도체 칩(110)들과 본딩 와이어(140)를 감싸도록 형성되어 외부 환경으로부터 이를 보호한다. The molding resin 190 is formed to surround the semiconductor chip 110 and the bonding wire 140 positioned on the substrate 120 to protect it from the external environment.

본딩 와이어 고정 수단(180)은 본딩 와이어(140)의 상부에서 본딩 와이어(140)를 수직으로 가로지르며 접착된다. 본딩 와이어 고정 수단(180)은 절연성을 갖는 수지(樹脂)이며, 실과 같은 와이어 형상으로 형성된다. Bonding wire fixing means 180 is bonded across the bonding wire 140 vertically on top of the bonding wire 140. The bonding wire fixing means 180 is an insulating resin, and is formed in a wire shape like a thread.

또한, 본딩 와이어 고정 수단(180)은 본딩 와이어(140)에 접착되기 위하여 그 표면에 접착 테이프와 같이 점착성을 갖는 물질이 도포되어 있다. 이에 따라 본딩 와이어(140)들이 흔들리는 것을 방지하고 고정시킬 수 있다. In addition, in order to bond the bonding wire fixing unit 180 to the bonding wire 140, a material having adhesiveness, such as an adhesive tape, is coated on the surface thereof. Accordingly, the bonding wires 140 may be prevented from being shaken and fixed.

여기서, 본딩 와이어 고정 수단(180)과 본딩 와이어(140)와의 접착력을 강화시키기 위해 본딩 와이어 고정 수단(180)에 열을 가하는 방법이 이용될 수 있다. 수지로 형성되는 본딩 와이어 고정 수단(180)에 열이 가해지면, 본딩 와이어 고정 수단(180)은 가해진 열에 의해 표면이 용융되고, 본딩 와이어 고정 수단(180)에 접 촉되어 있던 본딩 와이어(140)는 용융된 본딩 와이어 고정 수단(180)의 표면에 묻히게 된다. 이러한 상태에서 본딩 와이어 고정 수단(180)을 경화시키면, 본딩 와이어(140)의 접착 부분은 본딩 와이어 고정수단에 묻힌 상태로 경화되며 고정된다. Here, a method of applying heat to the bonding wire fixing means 180 may be used to enhance the adhesive force between the bonding wire fixing means 180 and the bonding wire 140. When heat is applied to the bonding wire fixing means 180 formed of resin, the bonding wire fixing means 180 is melted by the applied heat, and the bonding wire fixing means 180 is in contact with the bonding wire fixing means 180. Is buried on the surface of the molten bonding wire fixing means 180. When the bonding wire fixing means 180 is cured in this state, the adhesive portion of the bonding wire 140 is hardened and fixed while being buried in the bonding wire fixing means.

이러한 본딩 와이어 고정 수단(180)은 본딩 와이어(140)가 인접한 다른 본딩 와이어(140)와 접촉하는 것을 방지할 수 있다. 예를 들면, 도 2에서 본딩 와이어 고정 수단(180)은 적층되어 있는 다수개의 반도체 칩(110)들 중 최상부의 제 3 반도체 칩(113)과 연결되는 제 3 본딩 와이어(143)에 접착되어 있다. 제 3 본딩 와이어(143)의 경우, 본딩 패드(114)와 기판 패드(121) 사이의 거리기 길기 때문에 제 3 본딩 와이어(143)의 길이도 길게 형성된다. The bonding wire fixing means 180 may prevent the bonding wire 140 from contacting another adjacent bonding wire 140. For example, in FIG. 2, the bonding wire fixing unit 180 is bonded to the third bonding wire 143 which is connected to the third semiconductor chip 113 on the top of the plurality of stacked semiconductor chips 110. . In the case of the third bonding wire 143, since the distance between the bonding pad 114 and the substrate pad 121 is long, the length of the third bonding wire 143 is also long.

이 경우, 이후에 진행되는 몰딩 주입 공정에서 몰딩의 주입 압력에 의해 제 3 본딩 와이어(143)가 측면으로 쓰러지면서 인접한 제 3 본딩 와이어(143)와 접촉하기 쉽다. 그러나, 본 발명에 따른 본딩 와이어 고정 수단(180)은 제 3 본딩 와이어(140)에 접착되어 제 3 본딩 와이어(143)를 고정시키기 때문에 제 3 본딩 와이어(143)가 측면으로 쓰러지는 것을 억제할 수 있게 된다. In this case, in the subsequent molding injection process, the third bonding wire 143 collapses to the side by the injection pressure of the molding, and is easily in contact with the adjacent third bonding wire 143. However, since the bonding wire fixing unit 180 according to the present invention is bonded to the third bonding wire 140 to fix the third bonding wire 143, the third bonding wire 143 may be prevented from falling down to the side. Will be.

또한, 본딩 와이어 고정 수단(180)은 본딩 와이어(140)가 아래로 처지면서 하부에 형성된 본딩 와이어(140)와 접촉하는 것도 방지할 수 있다. 즉, 제 2 본딩 와이어(142)의 상부에 본딩 와이어 고정 수단(180)을 접착시키는 경우(도 2a의 점선), 제 3 본딩 와이어(143)가 아래로 처지더라도, 그 사이에 개재되어 있는 본딩 와이어 고정 수단(180)이 제 2 본딩 와이어(142)와 제 3 본딩 와이어(143)의 접촉을 방지하게 되며, 이에 따라 본딩 와이어(140)간의 단락을 막을 수 있다. In addition, the bonding wire fixing unit 180 may prevent the bonding wire 140 from coming into contact with the bonding wire 140 formed at the lower portion thereof. That is, when the bonding wire fixing means 180 is adhered to the upper portion of the second bonding wire 142 (dashed line in FIG. 2A), even if the third bonding wire 143 sags downward, bonding interposed therebetween. The wire fixing unit 180 may prevent the second bonding wire 142 and the third bonding wire 143 from contacting each other, thereby preventing a short circuit between the bonding wires 140.

이때, 제 3 본딩 와이어(143)를 본딩 와이어 고정 수단(180)의 상부면에 접착시켜, 제 3 본딩 와이어(143)와 제 2 본딩 와이어(140)을 동시에 고정시키는 것도 가능하다. In this case, the third bonding wire 143 may be attached to the upper surface of the bonding wire fixing unit 180 to simultaneously fix the third bonding wire 143 and the second bonding wire 140.

이와 같은 본 발명의 본딩 와이어 고정 수단(180)은 제 1 내지 제 3 본딩 와이어(141, 142, 143) 중 어느 하나의 본딩 와이어(140)에 접착 될 수 있으며, 필요에 따라 다수개가 제 1 내지 제 3 본딩 와이어(141, 142, 143)에 각각 설치되는 것도 가능하다. As described above, the bonding wire fixing unit 180 may be bonded to any one of the first to third bonding wires 141, 142, and 143, and a plurality of the first to third bonding wires 141, 142, and 143 may be attached to the bonding wire 140. It is also possible to be provided in each of the 3rd bonding wires 141, 142, 143.

이러한 본 발명의 본딩 와이어 고정 수단(180)은 본딩 와이어 코팅 물질(도 1a의 80)을 이용하지 않고 본딩 와이어(140)들 간의 접촉을 방지할 수 있기 때문에, 와이어 볼 들뜸 현상이나 미세 크랙이 발생되는 것도 방지할 수 있다.Since the bonding wire fixing unit 180 of the present invention can prevent contact between the bonding wires 140 without using the bonding wire coating material (80 of FIG. 1A), wire ball lifting or fine cracking occurs. It can also be prevented.

도 3a는 본 발명의 다른 실시예에 따른 칩 적층형 패키지를 나타내는 개략적인 단면도이고, 도 3b는 3a의 칩 적층형 패키지를 개략적으로 나타내는 평면도이다. 3A is a schematic cross-sectional view illustrating a chip stacked package according to another exemplary embodiment of the present invention, and FIG. 3B is a plan view schematically illustrating the chip stacked package of 3A.

본 실시예에 따른 본딩 와이어 고정 수단(280)을 갖는 반도체 패키지(300)는 전술된 실시예과 유사하게 구성되며, 본딩 와이어 고정 수단(280)의 형상에서 차이를 갖는다. The semiconductor package 300 having the bonding wire fixing means 280 according to the present embodiment is configured similarly to the above-described embodiment, and has a difference in the shape of the bonding wire fixing means 280.

본 실시예의 본딩 와이어 고정 수단(280)은 테이프와 같은 띠 형상으로 형성되어 제 3 본딩 와이어(143)의 상면에 접착된다. 이 경우, 제 3 본딩 와이어(143)와 본딩 와이어 고정 수단(280)이 접촉하는 부분이 많기 때문에 접착력이 더욱 강화되는 이점이 있다. 또한, 제 2 본딩 와이어(142)의 상부에 본딩 와이어 고정 수 단(280)이 개재되는 경우(도 3a의 점선), 전술된 실시예에서의 본딩 와이어 고정 수단(도 2a의 180)보다 넓은 면적으로 제 2 본딩 와이어(142)를 보호하므로, 상부의 제 3 본딩 와이어(143)가 아래로 처지더라도 이로 인하여 단락이 발생되는 것을 보다 효과적으로 억제할 수 있다.The bonding wire fixing means 280 of the present embodiment is formed in a band shape such as a tape and bonded to the upper surface of the third bonding wire 143. In this case, since there are many parts in which the third bonding wire 143 and the bonding wire fixing means 280 contact, there is an advantage that the adhesive force is further enhanced. Further, when the bonding wire fixing end 280 is interposed on the second bonding wire 142 (dotted line in FIG. 3A), the area larger than the bonding wire fixing means (180 in FIG. 2A) in the above-described embodiment. Since the second bonding wire 142 is protected, even if the upper third bonding wire 143 sags downward, it is possible to more effectively suppress the occurrence of a short circuit.

한편, 본 발명에 따른 본딩 와이어 고정 수단을 갖는 반도체 패키지는 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 다양한 변형이 가능하다. 예를 들어 실시예에서는 칩 적층형 패키지에 본딩 와이어 고정 수단을 이용하였지만, 이에 한정되는 것은 아니며 단일 칩 패키지나 적층 패키지 등 와이어 본딩을 이용하여 제조되는 반도체 패키지에 다양하게 적용될 수 있다. On the other hand, the semiconductor package having a bonding wire fixing means according to the present invention is not limited to the embodiment, various modifications are possible by those skilled in the art within the technical idea of the present invention. For example, although the bonding wire fixing means is used in the chip stack package, the present invention is not limited thereto and may be variously applied to a semiconductor package manufactured using wire bonding such as a single chip package or a stack package.

또한, 본 실시예에서는 원통의 막대 형상 또는 직사각으로 길게 형성된 띠 형상의 본딩 와이어 고정 수단을 이용하였지만, 본딩 와이어를 수직으로 가로지르며 본딩 와이어와 접착될 수 있는 형태라면 다양한 응용이 가능하다.In addition, in the present embodiment, a cylindrical rod-shaped or a strip-shaped bonding wire fixing means formed in a rectangular shape is used, but various applications are possible as long as it can cross the bonding wire vertically and be bonded to the bonding wire.

이상에서 살펴본 바와 같이, 본 발명에 따른 특징으로 본딩 와이어 고정 수단을 갖는 반도체 패키지는 반도체 칩과 기판을 연결하는 본딩 와이어의 상부에 본딩 와이어를 수직으로 가로지르며 본딩 와이어 고정 수단이 접착된다. As described above, in the semiconductor package having the bonding wire fixing means as a feature according to the present invention, the bonding wire fixing means is attached to the upper portion of the bonding wire connecting the semiconductor chip and the substrate vertically.

이에, 본딩 와이어에 와이어 코팅 물질을 사용하지 않으면서 본딩 와이어가 다른 본딩 와이어와 접촉되어 단락이 발생되는 것을 억제할 수 있으므로, 불량을 줄일 수 있어 수율이 높아지는 효과가 있다.Accordingly, since the bonding wire is in contact with other bonding wires and a short circuit may be suppressed without using the wire coating material in the bonding wires, defects may be reduced and the yield may be increased.

Claims (7)

일면에 기판 패드가 형성되어 있는 기판;A substrate having a substrate pad formed on one surface thereof; 상기 기판에 실장되고, 일면에 본딩 패드가 형성되어 있는 적어도 하나 이상의 반도체 칩;At least one semiconductor chip mounted on the substrate and having a bonding pad formed on one surface thereof; 상기 본딩 패드와 상기 기판 패드를 전기적으로 연결하는 다수의 본딩 와이어; 및 A plurality of bonding wires electrically connecting the bonding pads and the substrate pads; And 상기 본딩 와이어를 수직으로 가로지르며 상기 본딩 와이어의 상부면에 접착되는 절연성의 본딩 와이어 고정 수단;을 포함하여 구성되는 것을 특징으로 본딩 와이어 고정 수단을 갖는 반도체 패키지.And an insulating bonding wire fixing means that traverses the bonding wire vertically and is bonded to an upper surface of the bonding wire. 제 1 항에 있어서, 상기 본딩 와이어 고정 수단은 수지(樹脂)로 이루어지는 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지.The semiconductor package with bonding wire fixing means according to claim 1, wherein the bonding wire fixing means is made of resin. 제 1 항에 있어서, 상기 본딩 와이어 고정 수단은 원통의 막대 형상 또는 직사각으로 길게 형성된 띠 형상 중 어느 하나인 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지. The semiconductor package with bonding wire fixing means according to claim 1, wherein the bonding wire fixing means is any one of a cylindrical rod shape or a strip shape formed to extend in a rectangular shape. 제 1 항에 있어서, 상기 본딩 와이어 고정 수단은 적어도 하나 이상의 상기 반도체 칩 중 최상부에 적층되는 반도체 칩과 연결되는 상기 본딩 와이어에 접착되 는 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지.2. The semiconductor package according to claim 1, wherein the bonding wire fixing means is attached to the bonding wire connected to a semiconductor chip stacked on top of at least one of the semiconductor chips. 제 1 항에 있어서, 상기 본딩 와이어 고정 수단은 다수개가 적어도 하나 이상의 상기 반도체 칩과 연결되는 모든 상기 본딩 와이어에 각각 접착되거나, 선택적으로 접착되는 것 중 어느 하나인 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지.2. The bonding wire fixing means of claim 1, wherein the bonding wire fixing means is any one of a plurality of bonding wires attached to each of the bonding wires connected to at least one of the semiconductor chips, or selectively bonded to each other. Having a semiconductor package. 제 1 항 내지 제 5 항 중 어느 한 항에 있어서, 상기 본딩 와이어 고정 수단은 표면에 점착성을 갖는 물질이 도포되어 있는 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지.6. The semiconductor package according to any one of claims 1 to 5, wherein the bonding wire fixing means is coated with a material having a tacky property on its surface. 제 1 항 내지 제 5 항 중 어느 한 항에 있어서, 상기 본딩 와이어 고정 수단은 열에 의해 상기 본딩 와이어와 접착되는 것을 특징으로 하는 본딩 와이어 고정 수단을 갖는 반도체 패키지.6. The semiconductor package according to any one of claims 1 to 5, wherein the bonding wire fixing means is bonded to the bonding wire by heat.
KR1020050085244A 2005-09-13 2005-09-13 Semiconductor package with fixing means of bonding wires KR20070030519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020050085244A KR20070030519A (en) 2005-09-13 2005-09-13 Semiconductor package with fixing means of bonding wires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020050085244A KR20070030519A (en) 2005-09-13 2005-09-13 Semiconductor package with fixing means of bonding wires

Publications (1)

Publication Number Publication Date
KR20070030519A true KR20070030519A (en) 2007-03-16

Family

ID=43655133

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050085244A KR20070030519A (en) 2005-09-13 2005-09-13 Semiconductor package with fixing means of bonding wires

Country Status (1)

Country Link
KR (1) KR20070030519A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989939B2 (en) 2008-09-04 2011-08-02 Samsung Electronics Co., Ltd. Semiconductor package which includes an insulating layer located between package substrates which may prevent an electrical short caused by a bonding wire
CN104051400A (en) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 Brace for bond wire
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7989939B2 (en) 2008-09-04 2011-08-02 Samsung Electronics Co., Ltd. Semiconductor package which includes an insulating layer located between package substrates which may prevent an electrical short caused by a bonding wire
CN104051400A (en) * 2013-03-12 2014-09-17 飞思卡尔半导体公司 Brace for bond wire
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
US11257780B2 (en) 2015-11-02 2022-02-22 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires

Similar Documents

Publication Publication Date Title
US7148560B2 (en) IC chip package structure and underfill process
JP4998268B2 (en) Semiconductor device and manufacturing method thereof
US7129572B2 (en) Submember mounted on a chip of electrical device for electrical connection
US8355262B2 (en) Electronic component built-in substrate and method of manufacturing electronic component built-in substrate
US20070020811A1 (en) Method and apparatus for attaching microelectronic substrates and support members
JP4899406B2 (en) Flip chip type semiconductor device
JP5104734B2 (en) Highly reliable semiconductor device production method and system
JP2009212315A (en) Semiconductor device and manufacturing method thereof
KR100825784B1 (en) Semiconductor package suppressing a warpage and wire open defects and manufacturing method thereof
JP2010010301A (en) Semiconductor device and method of manufacturing the same
US20080237855A1 (en) Ball grid array package and its substrate
US6261869B1 (en) Hybrid BGA and QFP chip package assembly and process for same
KR100748558B1 (en) Chip size package and method of fabricating the same
US20070246814A1 (en) Ball Grid array package structure
KR20070030519A (en) Semiconductor package with fixing means of bonding wires
JP2008251929A (en) Multilayer type semiconductor device
TWI582905B (en) Chip package structure and manufacturing method thereof
KR100541397B1 (en) BGA package with insulated dummy solder ball
US20030211653A1 (en) Apparatus for providing mechanical support to a column grid array package
JP2005243975A (en) Semiconductor device
US7968993B2 (en) Stacked semiconductor device and semiconductor memory device
US20070235872A1 (en) Semiconductor package structure
KR19990066529A (en) Chip size package and its manufacturing method
KR100248202B1 (en) Chip scale package and method foe forming the same
KR20100020771A (en) Method for fabricating semiconductor package

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid