KR20070030454A - Method for manufacturing a semiconductor device - Google Patents

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can prevent the floating phenomenon of the metal wiring by suppressing the explosion reaction between the diffusion barrier and the metal wiring such as tungsten, regardless of the thickness of the diffusion barrier, in the present invention Depositing an interlayer insulating film on the substrate; forming a pattern hole to expose a portion of the substrate by etching a portion of the interlayer insulating film; and depositing a metal film along a step of an upper portion of the interlayer insulating film including the pattern hole. Forming a metal silicide film on the surface of the substrate at the bottom of the pattern hole by performing a thermal process; and implanting nitrogen into a portion of the metal silicide film by a predetermined depth through a nitrogen ion implantation process to form a diffusion barrier film. And depositing a metal wiring on the diffusion barrier to fill the pattern hole. It provides a semiconductor device manufacturing process comprising the system.

Metal wiring, diffusion barrier, nitrogen ion implantation, metal silicide, TiSiN.

Description

Semiconductor device manufacturing method {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

1 is a cross-sectional view illustrating a metal wiring forming method of a semiconductor device according to the prior art.

2 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

110: substrate

112: interlayer insulating film

114: trench

116: Via Hole

118: Ti film

122: TiSi film

124: nitrogen ion implantation process

125: TiN film

126 TiSiN film

128: diffusion barrier

130: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a diffusion barrier and a method for forming a metal wiring of a NAND FLASH memory device having a line width of 70 nm.

In general, in order to manufacture a semiconductor integrated circuit, film formation, pattern etching, and the like are repeatedly performed on a substrate to form a plurality of desired semiconductor elements.

However, at the time of forming the wirings connecting the elements, there is a problem in that the Si of the substrate or the Si-containing layer which is the underlying layer causes mutual diffusion with the wiring forming material. Therefore, conventionally, a barrier metal is interposed between the wiring and the underlying layer to prevent such diffusion between Si and the wiring forming material. In this case, the barrier metal should be made of a material having excellent corrosion resistance as water having low electrical resistance.

Currently, nitrides of high melting point metal materials such as Ti, W, and Mo tend to be used as barrier metal materials for any one of copper (Cu), aluminum (Al), and tungsten (W), which are widely used as wiring materials. . Among them, Ti / TiN having good electrical and corrosion resistance is frequently used. In general, Ti functions as an adhesive layer to improve step coverage characteristics with the underlying layer.

On the other hand, in recent years, the line width of wirings has also narrowed in response to the demand for high integration and high miniaturization of semiconductor elements. Accordingly, the aspect ratio of the contact hole or the via hole formed in the wiring formation region is increased, and the embedding characteristic of the wiring material embedded in the contact hole is deteriorated due to the increase in the aspect ratio. As a result, conventional chemical vapor deposition (hereinafter, referred to as CVD) is used to improve the embedding properties of the wiring material. In particular, in terms of manufacturing cost and mass productivity, W is deposited by CVD to form wiring.

1 is a cross-sectional view illustrating a metal wiring forming method of a semiconductor device according to the prior art.

Referring to FIG. 1, an interlayer insulating film 12 (ILD) covering a semiconductor structure layer is deposited on a substrate 10 on which a semiconductor structure layer (not shown) such as a transistor is formed. Then, the interlayer insulating layer 12 is etched through a dual damascene process to form a pattern hole (not shown) having a damascene structure exposing a portion of the substrate 10.

Subsequently, the TiN film 14 is deposited along the stepped portion of the interlayer insulating film 12 including the pattern holes using the CVD method. Then, the W film 16 is deposited on the TiN film 14 so that the pattern holes are filled.

In this case, during the W deposition using the CVD method, the contact resistance is controlled by forming nucleation according to an explosive reduction reaction using a mixed gas of SiH ₄ / WF ₆ . Here, this reduction reaction is sensitive to the thickness of the diffusion barrier. That is, when the thickness of the diffusion barrier film made of TiN is thin because it is sensitive to the step coverage of the bottom of the pattern hole, Ti and fluorine (F) easily react at the weak part of the bottom of the pattern hole. ), The contact resistance increases rapidly.

In addition, when such an explosion reaction (see 'A' region) occurs, a sense amplifier having a step difference due to the characteristics of CVD TiN having low stress and / or uniformity applied to the deposition of W or In the SWD (Side Word Line) area, the lifting of the metal wires (see section 'B') occurs without overcoming the step. This lifting phenomenon (see 'B' region) causes particles (particles) to cause a decrease in the yield (yeild) of the device.

Therefore, the present invention has been proposed to solve the above problems, and manufacturing a semiconductor device capable of preventing the floating phenomenon of the metal wiring by suppressing the explosion reaction between the diffusion barrier and the metal wiring such as tungsten irrespective of the thickness of the diffusion barrier. The purpose is to provide a method.

According to an aspect of the present invention, there is provided a method of fabricating an interlayer insulating film on a substrate, forming a pattern hole to expose a portion of the substrate by etching a portion of the interlayer insulating film; Depositing a metal film along a step of an upper portion of the interlayer insulating film including the pattern hole, performing a thermal process to form a metal silicide film on the substrate surface of the bottom of the pattern hole, and performing a nitrogen ion implantation process. A method of manufacturing a semiconductor device includes forming a diffusion barrier layer by injecting nitrogen into a portion of a silicide layer by a predetermined depth, and depositing a metal wire on the diffusion barrier layer to fill the pattern hole.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

2 to 5 are process cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

First, as shown in FIG. 2, an interlayer insulating film 112 is deposited on a substrate 110 on which a predetermined semiconductor structure layer is formed. Here, the semiconductor structure layer includes a plurality of active elements such as transistors. In addition, the interlayer insulating film 112 is formed of an oxide film-based material. For example, the interlayer insulating layer 112 may include an HDP (High Density Plasma) oxide film, a Boron Phosphorus Silicate Glass (BPSG) film, a Phosphorus Silicate Glass (PSG) film, a Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS) film, and a Plasma Enhanced Chemical Vapor (PECVD) film. A single layer film or a laminate of these layers is laminated using any one of a deposition film, a USG (Un-doped Silicate Glass) film, a Fluorinated Silicate Glass (FSG) film, a Carbon Doped Oxide (CDO) film, and an Organic Silicate Glass (OSG) film. Form into a film.

Subsequently, the interlayer insulating layer 112 is etched through a dual damascene process to form a pattern hole (not shown) exposing a portion of the substrate 110. For example, first, a portion of the interlayer insulating layer 112 is etched to a predetermined depth to form a trench 114 by an etching process using a first mask pattern (not shown) formed through a first photomask process. Then, after performing a strip process to remove the first mask pattern, the interlayer exposed to the bottom of the trench 114 through an etching process using a second mask pattern (not shown) formed through the second photomask process. A portion of the insulating layer 112 is etched to form a via hole 116 exposing a portion of the substrate 110. Thereafter, a strip process is performed to remove the second mask pattern.

Subsequently, the Ti film 118 is deposited as an adhesive layer to improve the step coverage characteristic with the substrate 110 at the bottom of the via hole 116 along the step of the upper part of the entire structure including the via hole 116. Here, the Ti film 118 may be replaced with Ta, but since the effects obtained by them are the same, only the Ti film 118 will be described below. At this time, the Ti film 118 is deposited to a thickness of 100 to 150 kHz using PVD (Physical Vapor Deposition) or CVD method. Preferably, the deposition is carried out using a PVD method. This is because the PVD method prevents damage to the substrate 110 at the bottom of the via hole 116 as compared to the CVD method.

In this case, when the Ti film 118 is deposited by about 150 GPa, the Ti film 118 is deposited to a thickness of about 75 GPa on the substrate 110 exposed through the bottom of the via hole 116. This is because the line width of the via hole 116 is narrowed due to the high integration of the semiconductor device, so that the deposition characteristics of the Ti film 118 are reduced in the via hole 116 having a high aspect ratio.

Next, as shown in FIG. 3, the thermal process 120 is performed in-situ to form a metal silicide film such as the TiSi film 122. At this time, the TiSi film 122 is formed by reaction of Si drawn from the substrate 110 with Ti. Usually, the TiSi film 122 is thicker than the thickness of the Ti film 118 first deposited on the substrate 110 at the bottom of the via hole 116. For example, the thickness of the TiSi film 122 is about 50% increased from the thickness of the first Ti film 118 deposited. This is an increased thickness in the Ti film 118 downward direction.

Here, the thermal process 120 is carried out for 40 to 60 seconds at a process temperature of 750 to 800 ℃ using RTP (Rapid Thermal Rrocess) equipment. Preferably, it is 60 seconds. As such, by forming the TiSi film 122, it is possible to further improve the adhesive force with the metal wiring 130 (see FIG. 5) to be formed through the subsequent process.

Next, as shown in FIG. 4, nitrogen (N ₂ ) ion implantation step 124 is performed in situ to inject nitrogen into the TiSi film 122 and the Ti film 118. As a result, part of the exposed Ti film 118 and part of the TiSi film 122 are converted into the TiSiN film 126. Accordingly, the Ti film / TiN film 118/125 is laminated on the surface of the interlayer insulating film 112, and the TiSi film / TiSiN film 122 is formed on the substrate 110 at the bottom of the via hole 116 (see FIG. 2). / 126) can be formed a diffusion barrier film 128. Specifically, the TiSiN film 126 is formed by injecting nitrogen to a predetermined depth from the top of the TiSi film 122, and the TiN film 125 is formed by injecting nitrogen to a certain depth from the top of the Ti film 118. .

That is, in the preferred embodiment of the present invention, the TiSiN film 126 is formed by performing the nitrogen ion implantation process 124 in situ with the deposition chamber of the Ti film 118, so that a separate CVD chamber for depositing TiSiN is formed. It is not necessary. As a result, the TiSiN film 126 does not increase in thickness in the upper direction of the Ti film 118, thereby reducing the contact resistance. In addition, by forming the TiN film 125 and the TiSiN film 126 through the nitrogen ion implantation process 124, the TiN film 125 and the TiSiN film 126 having a uniform thickness can be formed. Therefore, it is possible to secure a high uniformity of the TiN film 125 to suppress the floating phenomenon of the metal wiring 130 (see FIG. 5) to be formed through the subsequent process.

In addition, by forming the TiN film 125 and the TiSiN film 126 through the nitrogen ion implantation process 124, a plasma processing process for removing impurities may be unnecessary, thereby simplifying the manufacturing process.

At this time, it is important that the nitrogen ion implantation process 124 is performed twice with different ion implantation energies so that the thickness of the TiSiN film 126 is first on the substrate 110 at the bottom of the via hole 116 (see FIG. 2). It is to be 1/3 of the thickness of the deposited Ti film 118. In other words, when the Ti film 118 is deposited to a thickness of 75 GPa, the TiSiN film 126 has a thickness of 25 GPa. Therefore, it is possible to suppress the occurrence of an explosion phenomenon between the diffusion barrier 128 and the metal wiring 130 even at a thin thickness.

Preferably, the nitrogen ion implantation process 124 increases the ion implantation energy in the secondary nitrogen ion implantation process than in the primary nitrogen ion implantation process. For example, in the first nitrogen ion implantation process, nitrogen of 1.2E12 dose is implanted with ion implantation energy of 20 KeV so that nitrogen is implanted on the surface of the TiSi film 122. Then, in the secondary nitrogen ion implantation process, nitrogen of 1.2E12 dose is implanted with ion implantation energy of 30 KeV so that nitrogen is implanted from the top of the TiSi film 122 to a predetermined depth. In addition, the thickness of the TiSiN film 126 may be adjusted by adjusting the required time of the nitrogen ion implantation process 124.

Subsequently, as shown in FIG. 5, the metal wiring 130 is deposited to fill the via hole 116 (see FIG. 2) and the trench 114 (FIG. 2) on the diffusion barrier layer 128. For example, any one of W, Cu and Al is deposited by CVD. Preferably, W is deposited to a thickness of 4500-5000 kPa.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, by depositing a metal film such as Ti on the substrate and then performing a thermal process and a nitrogen ion implantation process to form a diffusion barrier film made of TiSiN, the film quality of the diffusion barrier film becomes dense. In addition, by forming TiSiN through a nitrogen ion implantation process, TiSiN is formed without increasing the thickness in the upper direction of Ti which is initially deposited. Therefore, even at a thin thickness, it is possible to prevent the explosion reaction between the diffusion barrier and the metal wiring deposited on the diffusion barrier.

In addition, according to the present invention, a diffusion preventing film made of TiN having a uniform thickness can be formed on the surface of the interlayer insulating film through a nitrogen ion implantation process to suppress the floating phenomenon of the metal wiring. Therefore, particle generation can be prevented to improve the yield of the semiconductor device.

In addition, according to the present invention, not only a separate plasma treatment process for removing impurities may be omitted by forming a diffusion barrier formed of dense TiSiN, but all the processes for forming the diffusion barrier formed of TiSiN may be performed in the same chamber. This can be done in situ. Therefore, the manufacturing process of the semiconductor device can be simplified.

Claims (17)

Depositing an interlayer insulating film on the substrate; Etching a portion of the interlayer insulating layer to form a pattern hole exposing a portion of the substrate; Depositing a metal film along a step of an upper portion of the interlayer insulating film including the pattern hole; Performing a thermal process to form a metal silicide film on the substrate surface of the bottom of the pattern hole; Forming a diffusion barrier by injecting nitrogen into a portion of the metal silicide layer by a predetermined depth through a nitrogen ion implantation process; And Depositing a metal wiring on the diffusion barrier to fill the pattern hole Semiconductor device manufacturing method comprising a. The method of claim 1, And depositing the metal film, forming the metal silicide film, and forming the diffusion barrier layer in situ in the same chamber. The method of claim 1, The metal film is a semiconductor device manufacturing method formed of Ti or Ta. The method of claim 3, wherein The forming of the diffusion barrier layer is a method of manufacturing a semiconductor device to inject the nitrogen from the top of the metal silicide film to a predetermined depth. The method of claim 4, wherein The diffusion barrier is a semiconductor device manufacturing method of forming a stacked structure of TiSi / TiSiN or TaSi / TaSiN. The method of claim 5, The TiSiN and TaSiN is a semiconductor device manufacturing method for forming a thickness of 1/3 of the initial thickness of the metal film. The method of claim 3, wherein The forming of the diffusion barrier layer is a method of manufacturing a semiconductor device in which the nitrogen is injected into a portion of the metal silicide film through the nitrogen ion implantation process and the nitrogen is also injected into a portion of the metal film. The method of claim 7, wherein The forming of the diffusion barrier layer is a method of manufacturing a semiconductor device to inject the nitrogen from the top of the metal film to a predetermined depth. The method of claim 8, The diffusion barrier is a semiconductor device manufacturing method of forming a stacked structure of Ti / TiN or Ta / TaN. The method according to any one of claims 1 to 9, The nitrogen ion implantation process is a semiconductor device manufacturing method is carried out two times by varying the ion implantation energy, respectively. The method of claim 10, The nitrogen ion implantation process is a semiconductor device manufacturing method for applying the ion implantation energy of 20KeV during the primary ion implantation to inject the nitrogen to the surface of the metal silicide film. The method of claim 11, The nitrogen ion implantation process is a semiconductor device manufacturing method for applying a higher ion implantation energy than the primary ion implantation in the secondary ion implantation to inject the nitrogen to a certain depth from the top of the metal silicide film. The method of claim 12, The ion implantation energy is 30KeV during the secondary ion implantation method. The method according to any one of claims 1 to 9, The depositing of the metal film is a semiconductor device manufacturing method using a PVD method. The method according to any one of claims 1 to 9, The thermal process is a semiconductor device manufacturing method performed for 40 to 60 seconds at a temperature of 750 to 800 ℃ using RTP equipment. The method according to any one of claims 1 to 9, The metal wiring is formed of any one of W, Cu and Al. The method according to any one of claims 1 to 9, Forming the pattern hole is a semiconductor device manufacturing method using a dual damascene process.

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