KR20070024782A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
KR20070024782A
KR20070024782A KR1020050080288A KR20050080288A KR20070024782A KR 20070024782 A KR20070024782 A KR 20070024782A KR 1020050080288 A KR1020050080288 A KR 1020050080288A KR 20050080288 A KR20050080288 A KR 20050080288A KR 20070024782 A KR20070024782 A KR 20070024782A
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South Korea
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precharge
power
write
bit line
signal
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KR1020050080288A
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Korean (ko)
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김종환
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주식회사 하이닉스반도체
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Priority to KR1020050080288A priority Critical patent/KR20070024782A/en
Publication of KR20070024782A publication Critical patent/KR20070024782A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

A semiconductor memory device is provided to improve reliability of the device by preventing a data fail due to the continuous write driving by supplying an external voltage to a supply port of an internal voltage during a precharge driving operation of a bit line pair. A latch part(200) latches data. A write control part(100) controls the driving of the latch part in response to first and second column selection signals. A write driving part(300) drives positive and negative data of the latch part to a bit line pair. A precharge part(400) precharges the bit line pair to an internal voltage level in response to a precharge control signal. A voltage driver(PM1) supplies an external voltage to a supply port of the internal voltage. A sub-precharge voltage control part(500) turns on the voltage driver for a predetermined time in a precharge operation.

Description

반도체메모리소자{SEMICONDUCTOR MEMORY DEVICE}Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

도 1은 종래기술에 따른 반도체메모리소자의 블록 구성도.1 is a block diagram of a semiconductor memory device according to the prior art.

도 2는 본 발명에 따른 반도체메모리소자의 블록 구성도.2 is a block diagram of a semiconductor memory device according to the present invention;

도 3은 도 2의 반도체메모리소자의 시뮬레이션 파형도.3 is a simulation waveform diagram of the semiconductor memory device of FIG.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

100 : 쓰기 제어부100: write control unit

200 : 래치부200: latch portion

300 : 쓰기 드라이빙부300: write driving unit

400 : 프리차지부400: precharge part

500 : 보조-프리차지 전원 제어부500: auxiliary precharge power control unit

PM1 : 전원 드라이버PM1: Power Driver

본 발명은 반도체 설계 기술에 관한 것으로, 특히 쓰기 동작 시 데이터를 페일을 방지하기 위한 반도체메모리소자에 관한 것이다.The present invention relates to a semiconductor design technology, and more particularly to a semiconductor memory device for preventing data from failing during a write operation.

일반적인 DRAM의 메모리 액세스 과정을 간략히 살펴보도록 하도록 한다.Let's take a brief look at the DRAM memory access process.

먼저, 액티브 커맨드와 로우 어드레스가 인가되면, 이에 응답하여 활성화된 워드라인에 연결된 메모리셀의 데이터가 비트라인 쌍에 미세전압 차로서 인가되고, 이는 비트라인 감지증폭기(Bit Line Sense Amplifier)에 의해 감지되어 논리 판별이 가능한 레벨로 증폭된다. 이어 읽기 또는 쓰기커맨드와 함께 컬럼 어드레스가 인가되면, 컬럼 어드레스에 따른 컬럼선택신호에 의해 선택된 비트라인에 대응하는 비트라인 감지증폭기의 증폭된 메모리 셀의 데이터가 출력되거나, 인가된 외부 데이터가 컬럼선택신호에 의해 선택된 비트라인 쌍에 쓰여진다. 이후 프리차지 커맨드에 의해 비트라인 쌍이 프리차지되어, 다음 액티브 커맨드의 인가를 위해 초기화된다.First, when an active command and a row address are applied, data of a memory cell connected to an activated word line in response thereto is applied as a minute voltage difference to a pair of bit lines, which is sensed by a bit line sense amplifier. And amplified to a level where logic can be discriminated. Subsequently, when a column address is applied together with a read or write command, data of the amplified memory cell of the bit line sense amplifier corresponding to the bit line selected by the column selection signal according to the column address is outputted, or the external data applied is the column selection. It is written to the bit line pair selected by the signal. The bit line pair is then precharged by the precharge command and initialized for application of the next active command.

한편, 다음에서는 전술한 프리차지 과정을 위한 회로 구성 및 동작을 보다 구체적으로 살펴보도록 한다.Meanwhile, the circuit configuration and operation for the precharge process described above will be described in more detail.

도 1은 종래기술에 따른 반도체메모리소자의 블록 구성도이다.1 is a block diagram of a semiconductor memory device according to the prior art.

도 1을 참조하면, 종래기술에 따른 반도체메모리소자는 데이터를 래치하기 위한 래치부(20)와, 컬럼 선택신호 YIOW 및 AYIOS에 응답하여 래치부(20)의 구동을 제어하기 위한 쓰기 제어부(10)와, 래치부(20)의 정 및 부 데이터를 비트라인 쌍(MIOT, MIOB)에 드라이빙하기 위한 쓰기 드라이빙부(30)와, 프리차지 제어신호(MIPC)에 응답하여 비트라인 쌍(MIOT, MIOB)을 프리차지 시키기 위한 프리차지부 (40)를 구비한다.Referring to FIG. 1, a semiconductor memory device according to the related art includes a latch unit 20 for latching data and a write control unit 10 for controlling driving of the latch unit 20 in response to column selection signals YIOW and AYIOS. ), The write driving unit 30 for driving the positive and negative data of the latch unit 20 to the bit line pairs MIOT and MIOB, and the bit line pair MIOT, in response to the precharge control signal MIPC. And a precharge portion 40 for precharging the MIOB.

다음에서는 종래기술에 따른 반도체메모리소자가 비트라인 쌍(MIOT, MIOB)에 데이터를 쓰는 과정 및 프리차지되는 과정을 간략히 살펴보도록 한다.Next, a process of writing data to a bit line pair MIOT and MIOB and precharging the semiconductor memory device according to the related art will be briefly described.

쓰기 제어부(10)는 컬럼 선택신호 YIOW 및 AYIOS가 활성화에 응답하여 출력신호를 활성화시키면, 래치부(20)는 쓰기 제어부(10)의 출력신호에 응답하여 데이터(DIN)를 래치하여 이를 정 및 부 데이터로 출력한다. 이어, 쓰기 드라이빙부(30)는 래치부(20)의 정 및 부 데이터를 각 정 비트라인(MIOT) 및 부 비트라인(MIOB)에 드라이빙한다. 이후, 프리차지신호(MIPC)가 논리레벨 'H'로 활성화되면 프리차지부(40)가 응답하여 내부전원 VCORE의 레벨로 정 및 부 비트라인(MIOT, MIOB)을 프리차지시키므로서, 다음 커맨드의 입력을 준비한다.When the write control unit 10 activates the output signal in response to the activation of the column selection signals YIOW and AYIOS, the latch unit 20 latches the data DIN in response to the output signal of the write control unit 10 to set it. Output as negative data. Subsequently, the write driving unit 30 drives the positive and negative data of the latch unit 20 to the positive bit line MIOT and the sub bit line MIOB. Subsequently, when the precharge signal MIPC is activated to a logic level 'H', the precharge unit 40 responds to precharge the positive and negative bit lines MIOT and MIOB to the level of the internal power supply VCORE, and then the next command. Prepare for input.

한편, 쓰기동작 이후에 비트라인 쌍(MIOT, MIOB)을 내부전원 VCORE의 레벨로 프리차지하게 되면 내부전원 VCORE의 전류소모가 발생한다. 특히, 쓰기동작이 연속적으로 이뤄지는 경우에 전류소모에 의한 내부전원 VCORE의 레벨 하강이 심화되어, 논리레벨 'H'의 데이터가 레벨 하강되어 메모리셀에 저장된다. 이와같이, 레벨 하강된 데이터는 논리레벨의 판단이 어려우므로 데이터의 페일이 발생한다. 더욱이, 반도체메모리소자의 밴드폭이 X16인 경우에는 이러한 문제점이 더욱 빈번히 발생 된다.On the other hand, if the bit line pair MIOT, MIOB is precharged to the level of the internal power supply VCORE after the write operation, current consumption of the internal power supply VCORE occurs. In particular, when the write operation is performed continuously, the level drop of the internal power supply VCORE due to the current consumption is intensified, and the data of the logic level 'H' is dropped and stored in the memory cell. As described above, since the level data is difficult to determine the logic level, data failure occurs. Moreover, this problem occurs more frequently when the bandwidth of the semiconductor memory device is X16.

본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 제안된 것으 로, 쓰기동작의 수행으로 내부전원이 하강되어 발생하는 데이터 페일 현상을 방지할 수 있는 반도체메모리소자를 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a semiconductor memory device capable of preventing a data fail phenomenon caused by the internal power supply being lowered by performing a write operation.

상기의 기술적 과제를 달성하기 위한 본 발명의 일측면에 따른 반도체메모리소자는 데이터를 래치하기 위한 래치부; 제1 및 제2 컬럼 선택신호에 응답하여 상기 래치부의 구동을 제어하기 위한 쓰기 제어부; 상기 래치부의 정 및 부 데이터를 비트라인 쌍에 드라이빙하기 위한 쓰기 드라이빙부; 프리차지 제어신호에 응답하여 상기 비트라인 쌍을 내부전원 레벨로 프리차지 시키기 위한 프리차지부; 상기 내부전원의 공급단에 외부전원을 공급하기 위한 전원 드라이버; 및 프리차지 시 소정시간 동안 상기 전원 드라이버를 턴온시키기 위한 보조-프리차지 전원 제어부를 구비한다.According to an aspect of the present invention, a semiconductor memory device includes: a latch unit for latching data; A write controller for controlling driving of the latch unit in response to first and second column selection signals; A write driver for driving positive and negative data of the latch unit on a bit line pair; A precharge unit for precharging the pair of bit lines to an internal power level in response to a precharge control signal; A power driver for supplying external power to the supply terminal of the internal power; And an auxiliary precharge power control unit for turning on the power driver for a predetermined time during precharging.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도 2는 본 발명에 따른 반도체메모리소자의 블록 구성도이다.2 is a block diagram of a semiconductor memory device according to the present invention.

도 2를 참조하면, 본 발명에 따른 반도체메모리소자는 데이터(DIN)를 래치하기 위한 래치부(200)와, 컬럼 선택신호 YIOW 및 AYIOS에 응답하여 래치부(200)의 구동을 제어하기 위한 쓰기 제어부(100)와, 래치부(200)의 정 및 부 데이터를 비트 라인 쌍(MIOT, MIOB)에 드라이빙하기 위한 쓰기 드라이빙부(300)와, 프리차지 제어신호(MIPC)에 응답하여 비트라인 쌍(MIOT, MIOB)을 프리차지 시키기 위한 프리차지부(400)와, 내부전원 VCORE의 공급단에 외부전원(VDD)을 공급하기 위한 전원 드라이버(PM1)와, 프리차지 시 소정시간 동안 전원 드라이버(PM1)를 턴온시키기 위한 보조-프리차지 전원 제어부(500)를 구비한다.Referring to FIG. 2, a semiconductor memory device according to the present invention includes a latch unit 200 for latching data DIN and a write unit for controlling driving of the latch unit 200 in response to column selection signals YIOW and AYIOS. The control unit 100, the write driving unit 300 for driving the positive and negative data of the latch unit 200 to the bit line pairs MIOT and MIOB, and the bit line pairs in response to the precharge control signal MIPC. A precharge unit 400 for precharging the MIOT and MIOB, a power driver PM1 for supplying the external power supply VDD to the supply terminal of the internal power supply VCORE, and a power driver for a predetermined time during the precharge. Auxiliary precharge power control unit 500 for turning on PM1) is provided.

그리고 보조-프리차지 전원 제어부(500)는 전원 감지신호(VDET)와 쓰기구동신호(WTS)와 밴드폭신호(X16)를 입력으로 갖는 낸드게이트(ND1)와, 프리차지 제어신호(MIPC)를 소정시간 지연시키기 위한 지연부(520)와, 지연부(520)의 출력신호를 반전시키기 위한 인버터(I1)와, 인버터(I1)의 출력신호와 프리차지 제어신호(MIPC)를 입력으로 갖는 낸드게이트(ND2)와, 낸드게이트 ND1 및 ND2의 출력신호를 입력으로 갖는 노어게이트(NR1)와, 노어게이트(NR1)의 출력신호를 반전시켜 출력하기 위한 인버터(I2)를 구비한다.In addition, the auxiliary precharge power control unit 500 supplies the NAND gate ND1 having the power detection signal VDET, the write drive signal WTS, and the bandwidth signal X16 as an input, and the precharge control signal MIPC. NAND having as inputs a delay unit 520 for delaying a predetermined time, an inverter I1 for inverting the output signal of the delay unit 520, an output signal of the inverter I1 and a precharge control signal MIPC A gate ND2, a NOR gate NR1 having input signals of the NAND gates ND1 and ND2 as inputs, and an inverter I2 for inverting and outputting an output signal of the NOR gate NR1 are provided.

참고적으로, 전원 감지신호(VDET)는 내부전원 VCORE의 레벨 하강이 발생하지 않는 조건 하에서의 외부전원(VDD)의 레벨을 나타내며, 쓰기 구동신호(WTS)는 쓰기구동 시 발생하며 밴드폭신호(X16)는 소자의 밴드폭이 X16인 경우에 활성화된다.For reference, the power detection signal VDET indicates the level of the external power supply VDD under the condition that the level drop of the internal power supply VCORE does not occur, and the write driving signal WTS is generated during the write drive and the bandwidth signal X16 is generated. Is activated when the device's bandwidth is X16.

다음에서 비트라인 프리차지 동작을 간략히 살펴보도록 한다.The following describes the bit line precharge operation briefly.

먼저, 전원 감지신호(VDET), 쓰기 구동신호(WTS) 및 밴드폭신호(X16)가 활성화되면 보조-프리차지 전원 제어부(500)는 출력신호를 논리레벨 'L'로 활성화시킨다. 이어, 전원 드라이버(PM1)는 보조-프리차지 전원 제어부(500)의 출력신호에 응답하여 내부전원 VCORE의 공급단에 외부전원(VDD)을 공급한다.First, when the power detection signal VDET, the write driving signal WTS, and the bandwidth signal X16 are activated, the auxiliary precharge power control unit 500 activates the output signal to a logic level 'L'. Subsequently, the power driver PM1 supplies the external power VDD to the supply terminal of the internal power VCORE in response to the output signal of the auxiliary precharge power control unit 500.

도 3은 도 2의 반도체메모리소자의 시뮬레이션 파형도로서, 특히 쓰기 구동이 연속적으로 이뤄지는 경우이다.FIG. 3 is a simulation waveform diagram of the semiconductor memory device of FIG. 2, in particular, in which write driving is performed continuously.

이와같이, 본 발명에 따른 반도체메모리소자는 도 1에 도시된 종래기술에 비해 보조-프리차지 전원 제어부 및 전원 드라이버를 더 구비하여, 비트라인 프리차지 구동 시 소정시간 동안 내부전원 VCORE의 공급단에 외부전원을 공급하므로서, 연속되는 쓰기 동작의 수행으로 인해 내부전원의 레벨이 하강되는 현상을 방지한다.As described above, the semiconductor memory device according to the present invention further includes an auxiliary precharge power control unit and a power driver as compared to the related art illustrated in FIG. 1, and is external to the supply terminal of the internal power supply VCORE for a predetermined time during the bit line precharge driving. By supplying the power, the level of the internal power supply is prevented from being lowered due to the successive write operations.

이상에서 설명한 본 발명은 전술한 실시 예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속한 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 비트라인 쌍의 프리차지 구동 시 내부전원의 공급단에 외부전원을 소정시간 공급하므로서, 연속된 쓰기 구동으로 인한 데이터 페일 현상을 방지하여 소자의 신뢰도를 향상시킨다.The present invention described above supplies external power to the supply terminal of the internal power for a predetermined time during the precharge driving of the bit line pair, thereby preventing data failure due to continuous write driving, thereby improving reliability of the device.

Claims (2)

데이터를 래치하기 위한 래치부;A latch unit for latching data; 제1 및 제2 컬럼 선택신호에 응답하여 상기 래치부의 구동을 제어하기 위한 쓰기 제어부;A write controller for controlling driving of the latch unit in response to first and second column selection signals; 상기 래치부의 정 및 부 데이터를 비트라인 쌍에 드라이빙하기 위한 쓰기 드라이빙부;A write driver for driving positive and negative data of the latch unit on a bit line pair; 프리차지 제어신호에 응답하여 상기 비트라인 쌍을 내부전원 레벨로 프리차지 시키기 위한 프리차지부;A precharge unit for precharging the pair of bit lines to an internal power level in response to a precharge control signal; 상기 내부전원의 공급단에 외부전원을 공급하기 위한 전원 드라이버; 및A power driver for supplying external power to the supply terminal of the internal power; And 프리차지 시 소정시간 동안 상기 전원 드라이버를 턴온시키기 위한 보조-프리차지 전원 제어부Auxiliary precharge power controller for turning on the power driver for a predetermined time during precharging 를 구비하는 반도체메모리소자.A semiconductor memory device having a. 제1항에 있어서,The method of claim 1, 상기 보조-프리차지 전원 제어부는,The auxiliary precharge power control unit, 전원 감지신호와 쓰기구동신호와 밴드폭신호를 입력으로 갖는 제1 낸드게이트와,A first NAND gate having a power detection signal, a write drive signal, and a bandwidth signal as inputs; 상기 프리차지 제어신호를 소정시간 지연시키기 위한 지연부와,A delay unit for delaying the precharge control signal for a predetermined time; 상기 지연부의 출력신호를 반전시키기 위한 제1 인버터와,A first inverter for inverting the output signal of the delay unit; 상기 제1 인버터의 출력신호와 상기 프리차지 제어신호를 입력으로 갖는 제2 낸드게이트와,A second NAND gate having an output signal of the first inverter and the precharge control signal as inputs; 상기 제1 및 제2 낸드게이트의 출력신호를 입력으로 갖는 노어게이트와,A NOR gate having the input signals of the first and second NAND gates as inputs; 상기 노어게이트의 출력신호를 반전시켜 출력하기 위한 제2 인버터를 구비하는 것을 특징으로 하는 반도체메모리소자.And a second inverter for inverting and outputting the output signal of the NOR gate.
KR1020050080288A 2005-08-30 2005-08-30 Semiconductor memory device KR20070024782A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892728B1 (en) * 2007-12-27 2009-04-10 주식회사 하이닉스반도체 Circuit and method for controlling main amplifier semiconductor memory apparatus
US8644094B2 (en) 2011-05-23 2014-02-04 Samsung Electronics Co., Ltd. Semiconductor memory devices including precharge using isolated voltages

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100892728B1 (en) * 2007-12-27 2009-04-10 주식회사 하이닉스반도체 Circuit and method for controlling main amplifier semiconductor memory apparatus
US8644094B2 (en) 2011-05-23 2014-02-04 Samsung Electronics Co., Ltd. Semiconductor memory devices including precharge using isolated voltages

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