KR100668732B1 - Circuit for preventing sensing noise of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data sensing circuit of a semiconductor memory capable of preventing a malfunction of a local sensing amplifier during a parallel test. The present invention provides a sense amplifier enable control signal SAEBi by a first delay time tD1. A second delay unit delaying and outputting the first delay unit outputting the delay and the output signal of the first delay unit tD1 by a second delay time tD2; the output signal of the second delay unit and the parallel test control signal TPARA A second logic operation unit configured to output an output signal of the first delay unit inverted and an inverted parallel test control signal TPARA, and an output signal and a sense of the first and second logic operation units; A third logic operation unit configured to calculate and output an amplifier enable control signal SAEBi, and a fourth logic operation unit configured to compute and output an output signal of the sense amplifier enable control signal SAEBi and the third logic operation unit; A CSP driver for outputting an overdriving signal CSP to the sense amplifier block by the output signal SAP1B of the fourth logical operation unit NR4 and the output signal SAP2 of the delayed third logical operation unit NR4; And a CSN driver for outputting an under-driving signal CSN to the sense amplifier block by an enable signal SAN.

Local I / O, parallel test, sensing noise

Description

Circuit for preventing sensing noise of semiconductor device

1 is a block diagram of a data sensing circuit of a conventional semiconductor memory

2 is an operational waveform diagram in parallel test in the prior art.

3 is a block diagram of a data sensing circuit of a semiconductor memory according to the present invention.

Figure 4a is a normal operating waveform diagram of the data sensing circuit according to the present invention

4b is an operational waveform diagram during parallel testing of a data sensing circuit according to the present invention;

Explanation of symbols for the main parts of the drawings

31.X-Decoder 32.Wordline Driver

33a. First delay section 33b. Second delay unit

34.CSP driver 35.CSN driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data sensing of semiconductor memories, and more particularly, to a data sensing circuit of a semiconductor memory capable of preventing a malfunction of a local sensing amplifier during a parallel test.                         

BACKGROUND OF THE INVENTION A semiconductor memory device is used as a component having a function of storing digital information, reading information when necessary, and transmitting the information to an external device.

As the storage capacity of semiconductor memory devices increases, the effort and cost of testing the operating states of the memory cells of the semiconductor memory devices also begin to increase.

Thus, a method of testing memory cells at a lower cost has been studied, and as a result, a technique for testing many memory cells has been developed. That is the parallel bit test method.

In the parallel bit test method, it is possible to achieve miniaturization and low power consumption of a semiconductor memory device by using a circuit with low power consumption.

Hereinafter, a parallel test of a semiconductor memory device of the prior art will be described with reference to the accompanying drawings.

1 is a configuration diagram of a data sensing circuit of a semiconductor memory of the prior art, and FIG. 2 is an operational waveform diagram of a parallel test of the prior art.

First, a unit cell is composed of a cell transistor having a gate connected to a word line and one electrode connected to a bit line BLT or a bit line BLB, and a capacitor connected to the other electrode and the ground terminal of the cell transistor, respectively. A memory cell region including a plurality of these unit cells, and sense amplifier blocks connected to the bit lines BLT and / or bit lines BLB of the memory cell regions, and decoding the row input address AXi. An X-decoder 1, a word line driver 2 enabling specific word lines WL0, WL1, ... WLi by the decoded address signal, and a sense amplifier enable control signal SAEBi. A delay block (tD) 3 for delaying?, A first NOR gate 4a for NOR operation on the output signal of the delay block (tD) 3 and a sense amplifier enable control signal SAEBi, and the first 1 Output signal and sense amplifier of NOR gate 4a First inverter 5a for inverting the second NOR gate 4b for calculating the enable control signal SAEBi and for outputting the first enable signal SAP1B by inverting the output signal of the second NOR gate 4b. Second and third inverters 5b and 5c for delaying the output signal of the first NOR gate 4a and outputting the second enable signal SAP2, and the first and second enable signals SAP1B ( The CSP driver 6 outputs the overdriving signal CSP by SAP2, and the CSN driver 7 outputs the underdriving signal CSN by the third enable signal SAN.

In the conventional data sensing circuit configured as described above, specific word lines WL0, WL1,..., And WLi are enabled by external address coding, and cell data is applied to the bit line BLT BLB.

In addition, the sense amplifier enable control signal SAEBi enables the overdriving signal CSP and the underdriving signal CSN which are the sense amplifier driving signals, and the sense amplifier operates to sense the data of the bit line and select a column. When the signal ys is turned on, data is transferred to the local I / O bus.

In memory device testing, parallel test techniques are used to reduce test time.

This parallel test is determined by accessing several memory cells at the same time. Compared to the normal test, the parallel test has a large loading in the sensing operation, which degrades the characteristics of the sensing noise.

FIG. 2 is a flow diagram illustrating a data sensing signal flow of a memory cell according to the related art, and is represented by a first enable signal SAP1B having a delay time Dt pulse width in order to improve a sensing speed during an initial operation of a sense amplifier. The sense amplifier is controlled, which uses a signal buffered with external Vdd (3.3V).

In addition, after the data is sufficiently sensed, the sensing level is determined by the internal voltage 1.8V by the second enable signal SAP2.

At the end of the first enable signal SAP1B section using the external voltage signal to improve the initial sensing speed, the column select signal ys is turned on and data is transmitted to the local I / O bus. .

However, the data sensing circuit of the semiconductor memory of the prior art has the following problems.

In the data sensing circuit of the related art, when the column selection signal ys is turned on in the parallel test mode and data is transferred to the local I / O bus, the excessive first enable signal SAP1B section is maintained to sense the noise. Occurs excessively.

That is, the data sensing circuit of the prior art does not have the immunity to excessive noise sources generated in the parallel test operation because the sensing amplifier control signals in the normal operation and the parallel test operation are the same in the sensing operation.

This is caused by using a high level buffered external voltage to speed up the initial sensing operation. This causes a malfunction of the data sensing operation and greatly reduces the reliability of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the data sensing circuit of the prior art, and an object of the present invention is to provide a data sensing circuit of a semiconductor memory capable of preventing a malfunction of a local sensing amplifier during a parallel test. have.

A data sensing circuit of a semiconductor memory according to the present invention for achieving the above object is a semiconductor memory device including sense amplifier blocks are connected to the bit line (BLT), / bit line (BLB) of the memory cell region, The first delay unit outputs the sense amplifier enable control signal SAEBi by the first delay time tD1 and delays the output signal of the first delay unit tD1 by the second delay time tD2. A second logic unit configured to calculate and output an output signal of the second delay unit and a parallel test control signal TPARA, and an output signal of the first delay unit inverted and an inverted parallel test control signal TPARA A second logic operation unit configured to output an operation; a third logic operation unit configured to output an output signal of the first and second logic operation units and a sense amplifier enable control signal SAEBi and a sense amplifier enable control signal SAE Bi) and a fourth logic operation unit for calculating and outputting an output signal of the third logic operation unit; an output signal SAP1B of the inverted fourth logic operation unit NR4 and an output signal SAP2 of the delayed third logic operation unit NR4. A CSP driver for outputting an overdriving signal (CSP) to the sense amplifier block by using a CSP driver; and a CSN driver for outputting an underdriving signal (CSN) to the sense amplifier block by a third enable signal (SAN). It is characterized by.

Hereinafter, a data sensing circuit of a semiconductor memory according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a data sensing circuit of a semiconductor memory according to the present invention.

4A is a diagram illustrating normal operation waveforms of the data sensing circuit according to the present invention, and FIG. 4B is a diagram illustrating operation waveforms during parallel testing of the data sensing circuit according to the present invention.

The present invention is to prevent the deterioration of the characteristics of the noise generated during the parallel test by configuring the control path for the normal operation and the parallel test operation differently.

First, a unit cell is composed of a cell transistor having a gate connected to a word line and one electrode connected to a bit line BLT or a bit line BLB, and a capacitor connected to the other electrode and the ground terminal of the cell transistor, respectively. And a memory cell region including a plurality of unit cells, sense amplifier blocks connected to the bit lines BLT and / or bit lines BLB of the memory cell regions, and sensed by the column select signal YS. An X-decoder 31 including switching elements for outputting data to a local input / output bus (LIOB) LIO, and decoding a row input address AXi, and a specific word line WL0, WL1 by a decoded address signal. Word line driver 32 to enable WLi, first delay units tD1 and 33a for delaying the sense amplifier enable control signal SAEBi, and first delay units tD1. Delaying the output signal of 33a A first logic operation unit NR1 for performing an NOR operation on a second delay unit tD2 33b, an output signal of the second delay unit tD2 33b, and a parallel test control signal TPARA, and the first delay Output signals of the first and second inverters INV3 and INV4 for inverting the output signal of the negative tD1 33a and the parallel test control signal TPARA, respectively, and the output signals of the first and second inverters INV3 and INV4. A second logical operation unit NR2 for NOR operation, and a third logical operation unit NR3 for NOR operation on the output signal of the first and second logical operation units NR1 and NR2 and the sense amplifier enable control signal SAEBi. And a fourth logic operation unit NR4 for NOR operation of the sense amplifier enable control signal SAEBi and an output signal of the third logic operation unit NR3, and an output signal of the fourth logic operation unit NR4 by inverting. A third inverter INV5 for outputting the one enable signal SAP1B and a fourth for outputting the second enable signal SAP2 by delaying an output signal of the third logic operation unit NR3. 5 CSP driver 34 for outputting overdriving signal CSP by inverter INV6 (INV7), first and second enable signals SAP1B and SAP2, and third enable signal SAN. And a CSN driver 35 for outputting the underdriving signal CSN.

In the data sensing circuit according to the present invention configured as described above, specific word lines WL0, WL1,..., And WLi are enabled by external address coding, and cell data is applied to the bit line BLT BLB.

In addition, the sense amplifier enable control signal SAEBi enables the overdriving signal CSP and the underdriving signal CSN which are the sense amplifier driving signals, and the sense amplifier operates to sense the data of the bit line and select a column. When the signal ys is turned on, data is transferred to the local I / O bus.

In the normal operation of the sense amplifier enable control signal SAEBi, since the parallel test control signal TPARA becomes low as shown in FIG. 4A, the first and second delay units tD1 (tD2) 33a and 33b are low. The first enable signal SAP1B having a pulse width of tD = t (D1 + D2) is generated to improve the speed for the initial sensing operation during normal operation.

In the parallel test mode, as shown in FIG. 4B, the parallel test control signal TPARA becomes high so that the sense amplifier enable control signal SAEBi passes only the delay path of tD1 and has a first enable signal having a pulse width of tD1. (SAP1B) occurs.

Therefore, the first enable signal SAP1B signal having a pulse width equal to tD1 (tD1 <tD) controls the sensing operation for a short period during the parallel test operation, thereby reducing noise in the sensing operation.

The data sensing circuit of the semiconductor memory according to the present invention has the following effects.

In normal operation, use the section using high external voltage to improve the speed and in the parallel test operation, adjust the section using high voltage to prevent the malfunction of data sensing. Solve the noise problem.

This can optimize all operation in normal operation mode and parallel test mode, increasing the reliability of the device.

Claims (3)

A semiconductor memory device comprising sense amplifier blocks connected to and configured to correspond to bit lines BLT and / or bit lines BLB in a memory cell region. A first delay unit for delaying and outputting the sense amplifier enable control signal SAEBi by a first delay time tD1 and a second delay unit for outputting the output signal of the first delay unit tD1 for a second delay time tD2 2 delay section; A second logic for calculating and outputting an output signal of the second delay unit and the parallel test control signal TPARA and a second logic for calculating and outputting an inverted output signal of the first delay unit and an inverted parallel test control signal TPARA A calculator; Computing and outputting a third logic operation unit and a sense amplifier enable control signal SAEBi and an output signal of the third logic operation unit and the output signal and the sense amplifier enable control signal SAEBi A fourth logic operation unit; A CSP driver configured to output an overdriving signal CSP to the sense amplifier block by the output signal SAP1B of the inverted fourth logic operation unit NR4 and the output signal SAP2 of the delayed third logic operation unit NR4; And a CSN driver for outputting an under-driving signal (CSN) to the sense amplifier block by a third enable signal (SAN). 2. The sense amplifier enable control signal SAEBi according to claim 1, wherein the sense amplifier enable control signal SAEBi passes through the first and second delay parts tD1 and tD2 with the parallel test control signal TPARA low. A data sensing circuit of a semiconductor memory, characterized in that the output signal of the inverted fourth logic calculating section (NR4) used as the signal (SAP1B) has a pulse width of tD = t (D1 + D2). 2. The inverting circuit of claim 1, wherein the parallel test control signal TPARA becomes high in the parallel test mode so that the sense amplifier enable control signal SAEBi passes through only the delay path of tD1 and is used as the first enable signal SAP1B. And the output signal of the fourth logic calculating section (NR4) has a pulse width of tD1.

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