KR20070021372A - Circuit and method for controlling Sense amplifier of semiconductor memory device - Google Patents

Abstract

According to an aspect of the present invention, there is provided an electronic device including: a sense amplifier driving controller configured to generate sense amplifier control signals using external active command signals and test mode signals; A pulse generator for receiving one of the sense amplifier control signals and generating a pulse signal; And a sense amplifier driver which generates an overdriving signal and a first sense amplifier driving signal by combining one of the pulse signal and one of the control signals, and generates a second sense amplifier driving signal by buffering the other of the control signals. Disclosed is a sense amplifier control circuit comprising a.

Sense amplifier, test mode, overdriving,

Description

Circuit and method for controlling a sense amplifier of a semiconductor memory device {Circuit and method for controlling Sense amplifier of semiconductor memory device}

1 is a circuit diagram illustrating a general sense amplifier.

FIG. 2 is a circuit diagram illustrating a circuit for controlling the sense amplifier of FIG. 1.

3A to 3C are timing diagrams illustrating waveforms of the signals of FIG. 2.

4 is a circuit diagram showing a sense amplifier control circuit according to a first embodiment of the present invention.

5A through 5C are timing diagrams illustrating waveforms of the signals of FIG. 4.

6 is a circuit diagram illustrating a sense amplifier control circuit according to a second embodiment of the present invention.

7A to 7C are timing diagrams illustrating waveforms of the signals of FIG. 6.

8 is a circuit diagram illustrating the level shifter of FIGS. 4 and 6.

<Description of Symbols for Main Parts of Drawings>

10, 110: sense amplifier control unit

20, 120: pulse generator

30, 130: sense amplifier drive unit

The present invention relates to a circuit and a method for controlling a sense amplifier of a semiconductor memory device, and more particularly, to a circuit and a method for controlling a sense amplifier suitable for an overdriving method.

1 illustrates a sense amplifier generally used, and FIG. 2 is a sense amplifier control circuit for controlling driving of the sense amplifier of FIG. 1.

Referring to FIG. 2, the sense amplifier control circuit includes a sense amplifier driving controller 10, a pulse generator 20, and a sense amplifier driver 30. The sense amplifier driving controller 10 receives the sense amplifier activation signal SA_ACTBP and the sense amplifier inactivation signal SA_PCGP and generates a sense amplifier PMOS control signal SAPD and a sense amplifier NMOS control signal SAND. The pulse generator 20 delays the sense amplifier PMOS control signal SAPD to generate a predetermined pulse. The sense amplifier driver 30 receives the sense amplifier PMOS control signal SAPD and the sense amplifier NMOS control signal SAND and receives the overdriving signal SAP1, the sense amplifier PMOS driving signal SAP2, and the sense amplifier N. The Morse driving signal SAN1 is generated. Here, the over driving signal SAP1 initially overlies the first power supply line RTO for supplying power to the PMOSs MP3 and MP4 of the sense amplifier SA shown in FIG. 1 to the power supply voltage VDD. This signal is for driving, and the sense amplifier PMOS driving signal SAP2 is a signal for driving the first power supply line RTO with the core voltage VCORE after the sense amplifier overdriving, and sense amplifier NMOS driving. The signal SAN1 is a signal for supplying a ground voltage VSS to a second power supply line SB for supplying power to the NMOSs MN2 and MN3 of the sense amplifier SA of FIG. 1.

FIG. 3A illustrates a normal operation of the sense amplifier control circuit of FIG. 2, and FIG. 3B illustrates a case in which a test mode signal TRTO (test mode for delaying the sensing enable time of the RTO compared to the normal operation) is enabled. FIG. 3C illustrates a case in which the test mode signal TSB (test mode for delaying the sensing enable time of the SB compared to normal operation) is enabled.

The conventional sense amplifier control circuit inverts and logically multiplies the sense amplifier PMOS control signal SAPD and the sense amplifier NMOS control signal SAND in generating the sense amplifier PMOS driving signal SAP2.

However, in the normal operation (FIG. 3A) and when the test mode signal TSB is enabled (FIG. 3C), the sense amplifier control circuit operates well without any problem as shown in FIGS. 3A and 3C. However, when the test mode signal TRTO is enabled, the sense amplifier PMOS driving signal SAP2 shown in FIG. 3B (circled portion) is the sense amplifier PMOS driving signal SAP2 shown in FIGS. 3A and 3C. There is a problem in the operation of the sense amplifier control circuit because it does not have the same waveform as.

The technical problem to be achieved by the present invention is to allow the sense amplifier control circuit to operate well without any problem in the test mode for delaying the sensing enable time of the power supply line connected to the PMOS of the sense amplifier as compared to the normal operation.

According to a first aspect of the present invention, there is provided a sense amplifier control circuit including: a sense amplifier driving controller configured to generate sense amplifier control signals using external active command signals and test mode signals; A pulse generator for receiving one of the sense amplifier control signals and generating a pulse signal; And a sense amplifier driver which generates an overdriving signal and a first sense amplifier driving signal by combining one of the pulse signal and one of the control signals, and generates a second sense amplifier driving signal by buffering the other of the control signals. It includes.

According to another aspect of the present invention, there is provided a method of controlling a sense amplifier of a semiconductor memory device, the method comprising: generating sense amplifier control signals using external active command signals and test mode signals; Generating a pulse signal by receiving one of the sense amplifier control signals; Combining the pulse signal and one of the control signals to generate an overdriving signal and a first sense amplifier driving signal; Buffering another one of the control signals to generate a second sense amplifier driving signal; And controlling driving of the sense amplifier in response to the overdriving signal and the first and second sense amplifier driving signals.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only the embodiments to complete the disclosure of the present invention and complete the scope of the invention to those skilled in the art. It is provided to inform you. Like reference numerals in the drawings denote like elements.

4 shows a sense amplifier control circuit according to a first embodiment of the present invention. In the figure, SA_ACTBP is a sense amplifier activation signal that activates the sense amplifier through an internal delay upon receiving an external active command, and SA_PCGP is a sense amplifier deactivation signal that deactivates the sense amplifier through an internal delay upon receiving an external precharge command.

Referring to FIG. 4, the sense amplifier control circuit includes a sense amplifier driving controller 110, a pulse generator 120, and a sense amplifier driver 130. The sense amplifier driving control unit 110 receives the sense amplifier activation signal SA_ACTBP and the sense amplifier inactivation signal SA_PCGP and generates a sense amplifier PMOS control signal SAPD and a sense amplifier NMOS control signal SAND. The pulse generator 120 receives the sense amplifier PMOS control signal SAPD and generates a pulse signal. The sense amplifier driver 130 generates the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 by using the output signal of the pulse generator 120 and the sense amplifier PMOS control signal SAPD, and sense The sense amplifier NMOS driving signal SAN1 is generated using the amplifier NMOS control signal SAND.

In FIG. 4, the sense amplifier driving control unit 110 includes the latch unit 111, the inverters IV111-IV115, the delay units 112-115, the transfer gates TG111-TG114, and NAND gates ND111 and ND112. It includes. The latch unit 111 latches and outputs the sense amplifier activation signal SA_ACTBP and the sense amplifier inactivation signal SA_PCGP, and the inverter IV111 inverts the output signal of the latch unit 111 to output the sense amplifier activation / deactivation signal ( Output SAE). The delay unit 112 outputs the sense amplifier PMOS control signal SAP1D by delaying the sense amplifier activation / deactivation signal SAE, and the delay unit 114 delays and outputs the sense amplifier PMOS control signal SAP1D. do. The transfer gate TG111 transfers the output signal of the delay unit 114 under the control of the test mode signal TRTO, and the transfer gate TG112 transmits the sense amplifier PMOS control signal SAP1D under the control of the test mode signal TRTO. ). The NAND gate ND111 inverts and outputs the signal output from the transfer gate TG111 or the transfer gate TG112 and the sense amplifier activation / deactivation signal SAE. The inverter IV114 inverts the output signal of the NAND gate ND111 to output the sense amplifier PMOS control signal SAPD. The delay unit 113 delays the sense amplifier activation / deactivation signal SAE to output the sense amplifier NMOS control signal SAN1D, and the delay unit 115 delays and outputs the sense amplifier NMOS control signal SAN1D. do. The transfer gate TG113 transfers the sense amplifier NMOS control signal SAN1D under the control of the test mode signal TSB, and the transfer gate TG114 outputs the delay unit 115 under the control of the test mode signal TSB. Pass the signal. The NAND gate ND112 inverts and outputs the signal output from the transfer gate TG113 or the transfer gate TG115 and the sense amplifier activation / deactivation signal SAE. The inverter IV115 inverts the output signal of the NAND gate ND112 and outputs the sense amplifier NMOS control signal SAND.

In FIG. 4, the pulse generator 120 includes a delay unit 121, a NAND gate ND121, and inverters IV121 to IV122. The delay unit 121 delays and outputs the sense amplifier PMOS control signal SAPD. The inbuffer IV121 inverts the output signal of the delay unit 121 and outputs it, and the NAND gate ND121 inverts and outputs the output signal of the delay unit 121 and the sense amplifier PMOS control signal SAPD. The inverter IV122 inverts the output signal of the NAND gate ND121 and outputs the inverted signal.

In FIG. 4, the sense amplifier driver 130 includes inverters IV131-IV136, NOR gates NR131, and level shifters 131-133. The inverter IV131 inverts and outputs the sense amplifier PMOS control signal SAPD, and the NOR gate NR131 inverts and outputs the output signal of the inverter IV131 and the output signal of the inverter IV122. The inverters IV132 and IV133 buffer and output the sense amplifier NMOS control signal SAND. The level shifter 131 level shifts the output signal of the inverter IV122, and the level shifter 132 level shifts the output signal of the NOR gate NR131, and the level shifter 133 outputs the inverter IV133. Level shifts the output signal. The inverter IV134 inverts the output signal of the level shifter 131 to output the overdriving signal SAP1, and the inverter IV135 inverts the output signal of the level shifter 132 to sense amplifier PMOS driving signal SAP2. The inverter IV136 inverts the output signal of the level shifter 133 and outputs the sense amplifier NMOS driving signal SAN.

FIG. 5A illustrates a normal operation of the sense amplifier control circuit of FIG. 4, and FIG. 5B illustrates a case in which a test mode signal TRTO (test mode for delaying the sensing enable time of the RTO compared to the normal operation) is enabled. 5C illustrates a case where the test mode signal TSB (test mode for delaying the sensing enable time of the SB compared to the normal operation) is enabled.

Hereinafter, the operation of the sense amplifier control circuit according to the first embodiment of the present invention will be described with reference to FIGS. 4 and 5A to 5C.

First, the sense amplifier activation signal SA_ACTBP is activated so that both the sense amplifier PMOS control signal SAP1D and the sense amplifier NMOS control signal SAN1D are logic high. Here, it is assumed that the delay amounts of the delay unit 112 and the delay unit 113 are the same.

Referring to FIG. 5A, the normal operation will be described. In the normal operation, the test mode signals TRTO and TSB are all logic low (“L”). In this case, the transfer gate TG112 is turned on to transmit the sense amplifier PMOS control signal SAP1D without delay, and the transfer gate TG113 is turned on to transmit the sense amplifier NMOS control signal SAN1D without delay. do. Then, the NAND gate ND111 inverts the logic high by multiplying the sense amplifier activation / deactivation signal SAE of the logic high and the sense amplifier PMOS control signal of the logic high transmitted through the transfer gate TG112, and outputs a logic low. IV14 inverts the NAND gate ND111 output signal of the logic low to output the sense amplifier PMOS control signal SAPD of logic high. The NAND gate ND112 inverts the logic high by multiplying the sense amplifier activation / deactivation signal SAE of logic high and the sense amplifier NMOS control signal of logic high transferred through the transfer gate TG113, and outputs a logic low, and the inverter IV115. Inverts the output signal of the logic low NAND gate ND112 and outputs the sense amplifier NMOS control signal SAND of logic high. The delay of the SAPD is output, and the inverter IV121 inverts the logic high sense amplifier PMOS control signal SAPD and outputs the logic low to the node N1. The PMOS control signal SAPD is inversely logically multiplied to output a low pulse to the node N2 as shown in Fig. 5A, and the inverter IV122 inverts the node N2 to transfer the high pulse to the node N3. Logic The high sense amplifier NMOS control signal SAPD is inverted and output to node N4. The inverters IV132 and IV133 buffer and output the sense amplifier NMOS control signal SAND. Inverts and sums the signal of node N4 and the signal of node N4 to output logic high to node N5. The level shifter 131 level shifts the node N3 of the high pulse to output a low pulse, and the inverter IV134 inverts the low pulse. The level shifter 132 outputs a logic low by level shifting the logic high of the node N5, and the inverter IV135 inverts the logic low to output a logic high sense amplifier. The PMOS driving signal SAP2 is output, and the level shifter 133 level-shifts the inverter IV133, and the inverter IV136 inverts the output signal of the level shifter 133 to sense a logic high sense amplifier. Moss And it outputs the same signal (SAN).

Next, a test mode for delaying a sensing enable time of the power supply line RTO of the sense amplifier SA of FIG. 1 will be described with reference to FIG. 5B. In this case, the test mode signal TRTO is enabled at logic high, and the test mode signal TSB is disabled at logic low. Then, the transfer gate TG111 is turned on to transmit the sense amplifier PMOS control signal SAP1D delayed by D1 through the delay unit 114, and the transfer gate TG113 is turned on to sense amplifier NMOS control signal. (SAN1D) is delivered without delay. Then, the NAND gate ND111 inverts the logic high of the sense amplifier PMOS control signal of logic high, which is delayed by D1 through the transfer gate TG111, and the sense amplifier activation / deactivation signal SAE, and outputs a logic low. Inverter IV114 inverts the logic low and outputs a logic high. In this test mode, the sense amplifier PMOS control signal SAPD is delayed by D1 as compared to normal operation, and becomes logic high. The NAND gate ND112 operates in the same manner as the normal operation, so that the sense amplifier NMOS control signal SAND has the same waveform as the sense amplifier NMOS control signal SAND shown in FIG. 5A. Operation of the pulse generator 120 and the sense amplifier driver 130 is the same as that of FIG. 5A. However, if there is a difference, since the sense amplifier PMOS control signal SAPD is logic high after being delayed by D1 compared to normal operation, the signals of node N1, node N2, node N3, and node N5 are all D1 than normal operation. Since it is generated after the delay, the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are generated after being delayed by D1 as compared with the normal operation.

Next, a test mode for delaying a sensing enable time of the power supply line SB of the sense amplifier SA of FIG. 1 will be described with reference to FIG. 5C. In this case, the test mode signal TRTO is disabled to a logic low and the test mode signal TSB is enabled to a logic high. Then, the transfer gate TG112 is turned on so that the sense amplifier PMOS control signal SAP1D is transferred without delay, and the transfer gate TG114 is turned on and delayed by D2 through the delay unit 115 by the delay amplifier 115. The control signal SAP1D is transmitted. Then, the NAND gate ND111 operates as in the normal operation, and the sense amplifier PMOS control signal SAPD has the same waveform as the sense amplifier PMOS control signal shown in FIG. 5A. The NAND gate ND112 inverts the logic high of the sense amplifier NMOS control signal and the sense amplifier enable / disable signal SAE, which are delayed by D2 through the transfer gate TG114, and outputs a logic low, and outputs a logic low. IV115) inverts the logic low to output a logic high. In this test mode, unlike the normal operation, the sense amplifier NMOS control signal SAND is delayed by D2 compared to the normal operation, and becomes logic high. Operation of the pulse generator 120 and the sense amplifier driver 130 is the same as that of FIG. 5A. The difference is that since the sense amplifier NMOS control signal SAND is logic high after being delayed by D2 compared to the normal operation, the sense amplifier NMOS driving signal SAN is generated after being delayed by D2 compared to the normal operation. .

As described above, the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are sensed not passing through the sense amplifier PMOS control signal SAPD and the pulse generator 120 that have passed through the pulse generator 120. It is made by combining the amplifier PMOS control signal (SAPD). That is, since the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are made independently of the sense amplifier NMOS control signal SAND, the power supply line RTO of the sense amplifier SA of FIG. 1. In the test mode for delaying the sensing enable time of the conventional problem does not occur. In addition, the sense amplifier NMOS driving signal SAN1 is made independent of the sense amplifier PMOS control signal SAPD.

6 shows a sense amplifier control circuit according to a second preferred embodiment of the present invention.

The configuration of the sense amplifier control circuit of FIG. 6 is identical to that of the sense amplifier control circuit of FIG. 4. However, if there is a difference, it is a detailed configuration of the pulse generator 120.

Unlike FIG. 4, the pulse generator 120 of FIG. 6 includes a pulse generator 122, NAND gates ND122 and ND123, a delay unit 123, and an inverter IV123. The pulse generator 122 receives the sense amplifier PMOS control signal SAPD and outputs a low pulse as shown in FIG. 7A to the node N2. NAND gates ND122 and ND123 form a latch. The delay unit 123 delays and outputs the output signal of the NAND gate N122, and the inverter IV123 inverts and outputs the output signal of the delay unit 123.

Hereinafter, the operation of the sense amplifier control circuit according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 6 and 7A to 7C.

First, the normal operation will be described with reference to FIG. 7A. The pulse generator 122 receives the sense amplifier PMOS control signal SAPD and outputs a low pulse as shown in FIG. 7A to the node N2. Then, the NAND gate ND122 outputs a high pulse having a waveform as shown in FIG. 7A to the node N3, and the delay unit 123 outputs the high pulse of the node N3 by delaying it. The inverter IV123 inverts the high pulse and outputs a low pulse to the node N3. Since the waveforms of the nodes N3, N4, and 5 are the same as those of FIG. 5A, the operation of the sense amplifier driver 130 is the same as that of FIG. 4.

Next, a test mode for delaying a sensing enable time of the power supply line RTO of the sense amplifier SA of FIG. 1 will be described with reference to FIG. 7B. In this case, since the sense amplifier PMOS control signal SAPD is delayed by D1, the nodes N1 to N5 are delayed by D1 than the normal operation of FIG. 7A. As a result, the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are delayed by D1 than the normal operation of FIG. 7A.

Next, a test mode for delaying a sensing enable time of the power supply line SB of the sense amplifier SA of FIG. 1 will be described with reference to FIG. 7C. In this case, since the sense amplifier NMOS control signal SAND is generated delayed by D2, the sense amplifier NMOS driving signal SAN is delayed by D2 than the normal operation of FIG. 7A.

As described above, the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are sensed not passing through the sense amplifier PMOS control signal SAPD and the pulse generator 120 that have passed through the pulse generator 120. It is made by combining the amplifier PMOS control signal (SAPD). That is, since the overdriving signal SAP1 and the sense amplifier PMOS driving signal SAP2 are made independently of the sense amplifier NMOS control signal SAND, the power supply line RTO of the sense amplifier SA of FIG. 1. In the test mode for delaying the sensing enable time of the conventional problem does not occur. In addition, the sense amplifier NMOS driving signal SAN1 is made independent of the sense amplifier PMOS control signal SAPD.

8 is a circuit diagram illustrating the level shifter shown in FIGS. 4 and 6.

Referring to FIG. 8, when the input signal corresponding to the logic low is input to the level shifter, the input signal of the logic low is not input to the gate of the PMOS transistor MP12 through the NMOS transistor MN11 which is always turned on. The high voltage VPP is input to the gate of the PMOS transistor MP12 through the PMOS transistor MP11 that is already turned on. In this case, the PMOS transistor MP12 is turned on to output an output signal corresponding to the level of the high voltage VPP. On the other hand, when an input signal corresponding to logic high is input to the level shifter, the logic high input signal is input to the gate of the PMOS transistor MP12 through the NMOS transistor MN11 which is always turned on. In this case, the PMOS transistor MP12 is turned off, but the NMOS transistor MN12 is turned on to output an output signal corresponding to the level of the ground voltage VSS.

The reason for the above-described level shifter is to make the output signal larger than the input signal.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a test for delaying the sensing enable time of the power supply line RTO of the sense amplifier as well as a test mode for delaying the sensing enable time of the power supply line SB of the sense amplifier. In this mode, the sense amplifier control circuit can be operated without problems.

Claims (14)

A sense amplifier driving controller configured to generate sense amplifier control signals using external active command signals and test mode signals; A pulse generator for receiving one of the sense amplifier control signals and generating a pulse signal; And A sense amplifier driver configured to generate an overdriving signal and a first sense amplifier driving signal by combining one of the pulse signal and one of the control signals, and to generate a second sense amplifier driving signal by buffering the other of the control signals A sense amplifier control circuit of a semiconductor memory device comprising. The method of claim 1, The sense amplifier driving controller outputs the sense amplifier control signals by delaying the sense amplifier control signals for a predetermined time in the test mode in response to the test mode signals, and outputs the sense amplifier control signals without delay during the normal operation. Sense amplifier control circuit of the device. The method of claim 1, The pulse generator may include a delay unit configured to delay one of the sense amplifier control signals; And And a logic circuit for combining and outputting one of the output signal of the delay unit and the sense amplifier control signals. The method of claim 1, The pulse generator may include a pulse generator configured to receive one of the sense amplifier control signals and generate a low pulse; A delay unit for delaying an output signal of the pulse generator; An inverting element for inverting the output signal of the delay unit; And And a latch unit configured to invert and latch an output signal of the pulse generator and an output signal of the inverting element. The method of claim 1, And wherein the sense amplifier driver generates the overdriving signal and the first and second sense amplifier driving signals by delaying the normal operation in a test mode, rather than the normal operation. The method of claim 1, The sense amplifier driving controller is configured to delay the first over-driving signal and the first sense amplifier driving signal than the normal operation in a test mode for delaying a sensing enable time of a power supply line connected to the PMOS of the sense amplifier. And in the test mode for delaying the sensing enable time of the power supply line connected to the NMOS of the sense amplifier, the second sense amplifier driving signal is generated by delaying the normal operation than the normal operation. Amplifier control circuit. The method of claim 1, And the sense amplifier driver generates the first sense amplifier driving signal by inverting and summing one of an output signal of the pulse generator and one of the sense amplifier control signals. The method of claim 1, The sense amplifier driver may include: a first level shifter for level shifting the output signal of the pulse generator; A first inverting element inverting the output signal of the first level shifter to output the overdriving signal; A second inverting element inverting and outputting one of the sense amplifier control signals; A NOR gate outputting the inverse logic sum of the output signal of the pulse generator and the output signal of the second inverting element; A second level shifter for level shifting and outputting the NOR gate; A third inverting element inverting the second level shifter to generate the first sense amplifier driving signal; A buffering unit for buffering and outputting another one of the control signals; A third level shifter for level shifting and outputting the output signal of the buffering unit; And And a fourth inverting element configured to invert the second level shifter to output the second sense amplifier driving signal. Generating sense amplifier control signals using external active command signals and test mode signals; Generating a pulse signal by receiving one of the sense amplifier control signals; Combining the pulse signal and one of the control signals to generate an overdriving signal and a first sense amplifier driving signal; Buffering another one of the control signals to generate a second sense amplifier driving signal; And And controlling the driving of the sense amplifier in response to the over-driving signal and the first and second sense amplifier driving signals. The method of claim 9, And in response to the test mode signals, delay the sense amplifier control signals in a test mode and not delay the sense amplifier control signals in a normal operation. The method of claim 9, The method of claim 1, wherein the over-driving signal and the first and second sense amplifier driving signals are delayed and generated in a test mode rather than a normal operation. The method of claim 9, In the test mode for delaying the sensing enable time of the power supply line connected to the PMOS of the sense amplifier, the first overdriving signal and the first sense amplifier driving signal are generated by delaying the normal operation, and And generating the second sense amplifier driving signal by delaying the second sense amplifier driving signal from a normal operation in a test mode for delaying a sensing enable time of a power supply line connected to an NMOS. The method of claim 9, Wherein the pulse signal is level shifted to generate the overdriving signal, and the first sense amplifier driving signal is generated by level shifting after inverting and summing one of the pulse signal and the sense amplifier control signals. A method of controlling a sense amplifier of a memory device. The method of claim 9, And generating a second sense amplifier driving signal by level shifting the other one of the control signals after buffering the other one of the control signals.

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