KR20070014407A - Method of forming a gate - Google Patents

Abstract

A method for forming a gate is provided to reduce tensile stress as compared with a conventional silicon nitride layer by forming a hard mask pattern made of SiCN wherein a conductive layer is patterned by using the hard mask pattern. A gate oxide layer and a conductive layer are sequentially formed on a substrate(100). A hard mask layer is formed on the conductive layer, made of a material having lower tensile stress than that of silicon nitride. The gate oxide layer, the conductive layer and the hard mask layer are partially etched to form a gate(122) composed of a gate oxide layer pattern(116), a conductive layer pattern(118) and a hard mask pattern. The material having low tensile stress includes SiCN.

Description

Method of forming a gate

1 to 5 are schematic cross-sectional views illustrating a gate forming method according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation pattern

104: gate oxide film 106: polysilicon layer

108: metal layer 110: conductive film

112: hard mask film 114: second photoresist pattern

116: gate oxide film pattern 118: conductive film pattern

120: second hard mask pattern 122: gate

124: Spare Source / Drain Area

The present invention relates to a gate forming method. More specifically, the present invention relates to a method of forming a gate including a hard mask pattern on a conductive film pattern.

In the rapidly developing information society, highly integrated devices with high data transfer speeds are required to process large amounts of information more quickly. In order to manufacture highly integrated semiconductor devices, design rules of semiconductor devices are rapidly decreasing. Therefore, semiconductor devices require more fine patterns.

Due to the development of such a fine circuit process, the line width of the gate is also reduced, and as the line width of the gate becomes fine, the height of the gate increases. Thus, the aspect ratio of the gate is increasing.

In addition, a hard mask pattern is used as an etching mask to pattern the gate as described above, and the hard mask pattern is typically made of silicon nitride (SiN). Since the silicon nitride is hardly etched while the gate conductive layer is etched, the silicon nitride is suitable for use as a hard mask pattern.

The gate having a high aspect ratio may be formed by patterning a conductive layer formed under the hard mask pattern using the hard mask pattern as an etching mask.

All materials have inherent stresses during the formation of a material film of each material. The hard mask film made of silicon nitride has a relatively higher tensile stress than other material films used in semiconductor devices. Have

However, since the hard mask pattern is made of silicon nitride, it has a very large tensile stress. Accordingly, the gate is subjected to stress in the width direction, and the gate may be leaned due to the stress as described above, and in severe cases, the gate may collapse and the upper part of the neighboring gate may be in contact with the gate. Can be.

An object of the present invention for solving the above problems is to provide a gate forming method for suppressing the inclination or collapse of the gate.

In the gate forming method according to an embodiment of the present invention for achieving the above object, first, a gate oxide film and a conductive film are sequentially formed on a substrate. A hard mask film made of a material having a tensile stress smaller than silicon nitride (SiN) is formed on the conductive film. Next, the gate oxide film, the conductive film, and the hard mask film are partially etched to complete a gate formed of the gate oxide film pattern, the conductive film pattern, and the hard mask pattern.

The material having a smaller tensile stress than the silicon nitride (SiN) may include silicon carbide nitride (SiCN).

According to the present invention as described above, by using a film containing silicon carbide nitride (SiCN) having a smaller tensile stress than the silicon nitride film as a hard mask film can be prevented from tilting or falling down of the gate formed later.

Hereinafter, a gate forming method according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5 are schematic cross-sectional views illustrating a gate forming method according to an embodiment of the present invention.

Referring to FIG. 1, the trench isolation layer pattern 102 is formed on the semiconductor substrate 100 by performing an isolation process.

Specifically, first, a pad oxide film (not shown), a mask silicon nitride film (not shown), and a first photoresist pattern (not shown) are sequentially stacked on the semiconductor substrate 100, and the The pad oxide layer and the silicon nitride layer are partially etched using the first photoresist pattern as an etching mask to form a pad oxide layer pattern (not shown) and a first hard mask pattern (not shown).

In this case, a first organic anti-reflection layer (ALL, not shown) may be further formed on the silicon nitride layer. The first organic antireflection film is a film provided to prevent the photoresist sidewall profile from being poorly reflected by diffuse reflection in a subsequent photolithography process, and may be a silicon oxynitride layer (SiON). After forming the first hard mask pattern, the first photoresist pattern is removed through an ashing or strip process.

Subsequently, the semiconductor substrate 100 exposing the first hard mask pattern as an etching mask is partially etched to form a trench (not shown). After the trench is formed, a thermal oxide film (not shown) and an insulating film liner (not shown) may be optionally formed inside the trench.

The thermal oxide film is formed inside the trench at a very thin thickness by thermally oxidizing the trench surface to cure surface damage generated during the previous dry etching process. An insulating film liner is formed to a thickness of several hundreds of microseconds on the inner surface and the bottom surface of the trench in which the thermal oxide film is formed and the surface of the hard mask pattern.

The insulating film liner is formed to reduce stress in the silicon oxide film for device isolation embedded in the trench by a subsequent process and to prevent impurity ions from penetrating into the field region. The insulating film liner should be formed of a material having a high etching selectivity with respect to a silicon oxide film, which will be described later, under specific etching conditions. For example, the insulating film liner may be formed of silicon nitride (SiN).

Subsequently, an oxide film having excellent gap filling characteristics such as Undoped Silicate Glass (USG), O ₃ -TEOS USG (O ₃ -Tetra Ethyl Ortho Silicate Undoped Silicate Glass), or High Density Plasma (HDP) oxide film is used to fill the trench. Is deposited by a chemical vapor deposition (CVD) method to form a device isolation film (not shown). Preferably, a high density plasma oxide film is formed by generating a high density plasma using SiH ₄ , O ₂ and Ar gases as the plasma source. At this time, the trench is embedded by improving the gap filling capability of the high density plasma oxide film so that cracks or voids are not formed inside the trench.

In addition, if necessary, an annealing process may be performed on the device separator under a high temperature and an inert gas atmosphere at about 800 to 1050 ° C. to densify the device separator to lower the wet etch rate for subsequent cleaning processes. Can be.

Next, the device isolation layer is polished to expose the top surface of the hard mask pattern by etching back or chemical mechanical polishing (CMP) to form the device isolation layer pattern 102 inside the trench. do. As such, by forming the device isolation layer pattern 102, the semiconductor substrate 100 is limited to an active area and a field area.

Referring to FIG. 2, a gate oxide film 104 and a conductive film 110 are sequentially formed on the semiconductor substrate 100.

In more detail, the gate oxide film 104 may be formed on the semiconductor substrate 100 by a thermal oxidation process, and then, the conductive film 110 may be used as the gate electrode on the gate oxide film 104. ).

The conductive layer 110 may be formed of a laminated structure of the polysilicon layer 106 and the metal layer 108 or the polysilicon layer 106 and the metal silicide layer. In detail, a polysilicon layer 106 doped with a high concentration of impurities is formed by a doping process such as a diffusion process, an ion implantation process, or an in-situ doping process. Subsequently, the conductive layer 110 is formed by forming a metal layer 108 or metal silicide such as tungsten (W), titanium (Ti), tungsten silicon (WSi), titanium nitride (TiN), or the like on the polysilicon layer 106. ) Can be completed.

Referring to FIG. 3, a second hard mask layer 112 including silicon carbide nitride (SiCN) is formed on the conductive layer 110. The silicon carbide nitride (SiCN) has a smaller tensile stress than the silicon nitride film (SiN) used in the prior art, thereby preventing the gate (not shown) formed later from tilting or falling down. This will be described later in detail.

Referring to FIG. 4, a second photoresist pattern 114 is formed on the second hard mask layer 112 to selectively expose the second hard mask layer 112. Subsequently, the exposed second hard mask layer 112 is etched using the second photoresist pattern 114 as an etch mask to form a second hard mask pattern 120.

In this case, a second organic anti-reflection layer (ALL, not shown) may be further formed on the second hard mask layer 112. The second organic anti-reflection film is a film provided to prevent the photoresist sidewall profile from being poorly reflected by diffuse reflection in a subsequent photolithography process, and may be a silicon oxynitride film (SiON).

After the second hard mask pattern 120 is formed, the second photoresist pattern 114 is removed through an ashing or strip process.

Referring to FIG. 5, the conductive layer 110 and the gate oxide layer 104 exposed by the second hard mask pattern 114 are selectively etched using the second hard mask pattern 114 as an etch mask, thereby electrically conducting. A gate 122 in which a film pattern 118 and a gate oxide film pattern 116 are stacked is formed.

Here, the second hard mask pattern 120 formed on the gate 122 is formed of silicon carbide nitride (SiCN), so that the tensile stress is smaller than that of silicon nitride conventionally used as a hard mask pattern. As a result, the stress affecting the gate 122 is smaller than in the related art, so that the gate tilt or collapse may be suppressed even though the aspect ratio of the gate 122 is increased.

In addition, the silicon carbide nitride is excellent in etching resistance and is hardly etched during the etching of the conductive layer 110 using the hard mask. Therefore, in forming the gate 122 having a large aspect ratio, the profile of the gate 122 may be formed to be substantially vertical.

Subsequently, impurity implantation is performed using the gate 122 as a mask to form a preliminary source / drain 124 on the exposed surface of the semiconductor substrate 100. The preliminary source / drain regions 124 may be formed by ion implantation or diffusion, and the implanted impurities may be a group III element such as phosphorus (P), and the source / drain regions may be N-type semiconductor regions. .

Although not shown, a second silicon nitride film (not shown) for spacers is continuously formed on the gate 122 and the exposed semiconductor substrate 100, and anisotropic etching of the second silicon nitride film is performed on the gate to form the gate. Spacers (not shown) are formed on the sidewalls of the pattern.

Impurity implantation is performed in the preliminary source / drain region 124 using the gate 122 and the spacer as a mask to form a source / drain region (not shown).

By performing the impurity implantation as described above, a transistor (not shown) including a gate pattern and a source / drain region is formed in the active region of the semiconductor substrate 100.

As described above, according to the preferred embodiment of the present invention, the hard mask pattern for patterning the conductive film is disposed on the conductive film pattern is made of silicon carbide nitride (SiCN), the tensile stress is higher than the conventional silicon nitride film It is small and can prevent the fall of the gate formed later.

In addition, the etching resistance of the silicon carbide nitride film is also excellent, so that the hard mask pattern is hardly etched while the conductive film is patterned, so that the profile of the gate formed thereafter is substantially vertical.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (2)

Sequentially forming a gate oxide film and a conductive film on the substrate; Forming a hard mask film made of a material having a tensile stress lower than that of silicon nitride (SiN) on the conductive film; And Partially etching the gate oxide layer, the conductive layer, and the hard mask layer to form a gate including a gate oxide layer pattern, a conductive layer pattern, and a hard mask pattern. The method of claim 1, wherein the low tensile stress material comprises silicon carbide nitride (SiCN).

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