KR20070010863A - Array substrate, method of manufacturing the same and display device having the same - Google Patents

Abstract

An array substrate, a method for manufacturing the same, and a display device having the same are provided to prevent inferiority of horizontal stripes by preventing local charge trapping by preventing under-cut in patterning, thereby improving display quality. A substrate has a display area(DA) and peripheral areas(PA1,PA2) formed around the display area. Switching devices(220) are formed at the display area. Each switching device has a gate electrode(221), a source electrode(225) and a drain electrode(226). The gate electrode has a first metal film, a second metal film accumulated on the first metal film, and a third metal film formed on the second metal film through nitriding of the second metal film. A pixel electrode(250) is electrically connected with the second metal film through an insulator film and contact holes(245) formed at the third metal film.

Description

ARRAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND DISPLAY DEVICE HAVING THE SAME

1 is a cross-sectional view showing a liquid crystal display panel according to the present invention.

FIG. 2 is a plan view illustrating the array substrate of FIG. 1.

3 is a cross-sectional view of the gate electrode.

4A through 4H are cross-sectional views illustrating a process of manufacturing the array substrate illustrated in FIG. 2.

FIG. 5 is a diagram illustrating a reactive sputtering apparatus for forming the third metal film illustrated in FIG. 4B.

FIG. 6 is a view showing a plasma chemical vapor deposition apparatus for forming the third metal film shown in FIG. 4B.

7 is an exploded perspective view showing a liquid crystal display device having a liquid crystal display panel according to the present embodiment.

* Description of the symbols for the main parts of the drawings *

100 liquid crystal display panel 200 array substrate

260: gate electrode pad 280: data electrode pad

300: color filter substrate 400: liquid crystal layer

600: reactive sputtering apparatus 700: plasma chemical vapor deposition apparatus

800: display unit 900: backlight assembly

The present invention relates to an array substrate, a display device having the same, and a method of manufacturing the array substrate, and more particularly, to an array substrate capable of improving display quality, and a display device and the method of manufacturing the array substrate.

In general, a liquid crystal display device includes an array substrate, a color filter substrate facing the array substrate, and a liquid crystal layer interposed between the array substrate and the color filter substrate.

The array substrate is composed of a plurality of pixels which are the minimum units representing an image. Each of the pixels includes a gate line provided with a gate signal, a data line provided with a data signal, a thin film transistor connected to the gate line and the data line, and a pixel electrode configured to receive a data signal and apply a voltage to the liquid crystal layer.

The electrodes, the gate line, and the data line of the thin film transistor have a double layer structure to reduce contact resistance and wiring resistance with the pixel electrode. In this case, the electrodes, the gate line and the data line are made of a chromium (Cr) film and an aluminum neodymium film stacked on the chromium film.

When the chromium film is patterned to form the electrodes, the gate line, or the data line, an under-cut phenomenon occurs in which more etching is performed in the lower region.

A local charge trapping phenomenon occurs in which electrons are concentrated in an area where the under-cut phenomenon occurs. As a result, the capacitance of the insulating film formed thereon increases, and as the capacitance increases, the pixel voltage of the pixel region changes. Therefore, the luminance is changed by the change of the pixel voltage, and a defect in the form of horizontal lines occurs.

Accordingly, an object of the present invention is to provide an array substrate for improving display quality by preventing defects.

Another object of the present invention is to provide a method of manufacturing the above-described array substrate.

Another object of the present invention is to provide a display device having the array substrate.

An array substrate according to the present invention for achieving the above object includes a substrate, a switching element, an insulating film and a pixel electrode. The substrate has a display area and a peripheral area formed around the display area. The switching element is formed in the display area, and has a first electrode, a second electrode, and a third electrode, and at least one of the first to third electrodes is stacked on the first metal film and the first metal film. And a third metal film formed on the second metal film through nitriding treatment of the second metal film and the second metal film. The pixel electrode is electrically connected to the second metal film through contact holes formed in the insulating film and the third metal film.

Here, the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx).

In addition, the array substrate according to the present invention further includes an electrode pad and a transparent electrode. The electrode pad extends from one of the first to third electrodes and is formed in the peripheral area, and has the first metal film, the second metal film, and the third metal film. The transparent electrode is electrically connected to the second metal layer of the electrode pad through a via hole formed in the insulating layer and the third metal layer of the electrode pad.

In order to achieve the another object of the present invention, the display region on the substrate has a first electrode, a second electrode and a third electrode, wherein at least one of the first to third electrodes is a first metal film, the first metal film A switching element including a second metal film stacked on the second metal film and a third metal film formed on the second metal film is formed by nitriding the second metal film. Next, an insulating layer is formed on the switching element, and a pixel electrode electrically connected to the second metal layer of the switching element is formed through the contact hole formed in the insulating layer and the third metal layer of the switching element.

A display device for achieving another object of the present invention includes an upper substrate, an array substrate and a liquid crystal layer. The upper substrate has a first transparent electrode. The array substrate faces the upper substrate, and has a first electrode, a second electrode, and a third electrode, wherein at least one of the first to third electrodes is stacked on the first metal film and the first metal film. A switching element having a third metal film formed on the second metal film through a nitriding treatment of the second metal film and the second metal film, an insulating film formed on the switching device, and facing the first transparent electrode; A second transparent electrode electrically connected to the second gold layer of the switching element and an electrode of one of the first to third electrodes through a contact hole formed in the third metal layer of the switching element; An electrode pad formed of a first metal film, the second metal film, and the third metal film; and the second electrode of the electrode pad through a via hole formed in the insulating film and the third metal film of the electrode pad. The third transparent electrode is electrically connected to the metal film. The liquid crystal layer is formed between the upper substrate and the array substrate.

According to such an array substrate, a display panel having the same, and a method of manufacturing the array substrate, it has a triple layer structure of aluminum neodymium, chromium, and chromium nitride, so that under-cut phenomenon does not occur, and pure chromium, a pixel electrode, and a transparent electrode Each of these contacts causes the contact resistance to decrease.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view showing a liquid crystal display panel according to the present invention, FIG. 2 is a plan view showing the array substrate shown in FIG. 1, and FIG.

As shown in FIGS. 1 and 2, the liquid crystal display panel 100 according to the present invention is formed between the array substrate 200, the color filter substrate 300, the array substrate 200, and the color filter substrate 300. It consists of a liquid crystal layer 400 to display an image.

The liquid crystal display panel 100 is positioned on a display area DA where an image is displayed, a first peripheral area PA1 positioned on a first side of the display area DA, and a second side of the display area DA. It is divided into a second peripheral area PA2.

In the display area DA, a plurality of gate lines GL extending in a first direction D1 and a plurality of data lines DL extending in a second direction D2 perpendicular to the first direction D1. A plurality of pixel areas are defined by.

The array substrate 200 may include a thin film transistor (TFT) 220, a passivation layer 230, an organic insulating layer 240, and a pixel electrode formed corresponding to the pixel area on the first insulating substrate 210. 250.

The TFT 220 includes a gate electrode 221 branched from the gate line GL, a source electrode 225 branched from the data line DL, and a drain electrode 226 electrically connected to the pixel electrode 250. do. In addition, the TFT 220 includes a gate insulating film 222 and an active layer 224 formed on the gate electrode 221.

In this case, the gate electrode 221, the source electrode 225, and the drain electrode 226 have a triple layer structure.

That is, the gate electrode 221 includes the first gate electrode layer 221a, the second gate electrode layer 221b, and the third gate electrode layer 221c. In this case, the second gate electrode layer 221b is stacked on the first gate electrode layer 221a, and the third gate electrode layer 221c is stacked on the second gate electrode layer 221b. The first gate electrode layer 221a is made of aluminum neodymium (AlNd), and the second gate electrode layer 221b is made of chromium (Cr). The third gate electrode layer 221c is made of chromium nitride (CrNx) in which chromium is nitrided to form the second gate electrode layer 221b.

 The source electrode 225 includes a first source electrode layer 225a, a second source electrode layer 225b, and a third source electrode layer 225c. The second source electrode layer 225b is stacked on the first source electrode layer 225a, and the third source electrode layer 225c is stacked on the second source electrode layer 225b. Here, the first source electrode layer 225a is made of aluminum neodymium, and the second source electrode layer 225b is made of chromium. The third source electrode layer 225c is made of chromium nitride.

In addition, the drain electrode 226 includes a first drain electrode layer 226a, a second drain electrode layer 226b, and a third drain electrode layer 226c. In this case, the second drain electrode layer 226b is stacked on the first drain electrode layer 226a, and the third drain electrode layer 226c is stacked on the second drain electrode layer 226b. The first drain electrode layer 226a is made of aluminum neodymium, and the second drain electrode layer 226b is made of chromium. The third drain electrode layer 226c is made of chromium nitride.

Here, the gate electrode 221, the source electrode 225, and the drain electrode 226 of the TFT 220 have a tapered shape at both ends of the cut surface cut in a direction perpendicular to the first insulating substrate 210. That is, under-cut does not occur in the gate electrode 221, the source electrode 225, and the drain electrode 226.

As shown in FIG. 3, the cut surface cut in the direction perpendicular to the first insulating substrate 210 of the gate electrode 221 has a relatively wider width than the upper region. Therefore, both ends of the cut surface of the gate electrode 221 have a tapered shape. In the above description, the gate electrode 221 has been described as an example, but the source electrode 225 and the drain electrode 226 also have a cutting surface having a tapered shape at both ends, like the gate electrode 221.

As such, the first gate electrode layer 221a of the gate electrode 221, the first source electrode layer 225a of the source electrode 225, and the first drain electrode layer 226a of the drain electrode 226 are made of aluminum neodymium. The above under-cut does not occur. Therefore, local charge trapping in which electrons are concentrated to a portion where the under-cut has occurred does not occur, and thus an increase in capacitance does not occur. As a result, since the pixel voltage does not change, generation of a horizontal line defect due to a change in luminance is prevented.

The gate insulating layer 223 is formed on the entire surface of the first insulating substrate 210 on which the gate electrode 221, the source electrode 225, and the drain electrode 226 are formed. The gate insulating film 223 is formed of, for example, silicon nitride film (SiNx).

The active layer 224 is formed on the gate insulating layer 223. In this case, the active layer 224 includes a semiconductor layer 224a and an ohmic contact layer 225b stacked on the semiconductor layer 224a. For example, the semiconductor layer 224a is made of amorphous silicon (a-Si), and the ohmic contact layer 224b is made of amorphous silicon (n + a-Si) doped with a high concentration of n-type impurities. Is done. A portion of the ohmic contact layer 224b is removed to partially expose the semiconductor layer 224a.

The passivation layer 230 and the organic insulating layer 240 are sequentially formed on the entire surface of the first insulating substrate 210 on which the TFT 220 is formed. In other words, the passivation layer 230 and the organic insulating layer 240 are formed in the display area DA and the first and second peripheral areas PA1 and PA2 on the first insulating substrate 210. The passivation layer 230 and the organic insulating layer 240 are made of silicon nitride.

In addition, the protective film 230 and the organic insulating film 240 have a contact hole 245 that partially exposes the drain electrode 226 of the TFT 220. That is, the passivation layer 230 and the organic insulating layer 240 are partially removed to expose the drain electrode 226. At this time, the third drain electrode layer 226c of the drain electrode 226 is also removed at the same time. The third drain electrode layer 226c is simultaneously etched by a predetermined etchant that etches the passivation layer 230 and the organic insulating layer 240. Therefore, the second drain electrode layer 226b of the drain electrode 226 is partially exposed by the contact hole 245.

The pixel electrode 250 is formed on the organic insulating layer 240. The pixel electrode 250 is made of a transparent conductive material through which light can pass. For example, the pixel electrode 250 is made of indium zinc oxide (IZO) or indium tin oxide (ITO). In this case, the pixel electrode 250 is electrically connected to the drain electrode 226 of the TFT 220 through the contact hole 245. In detail, the pixel electrode 250 directly contacts the second drain electrode layer 226b of the drain electrode 226. In this case, since the second drain electrode layer 226b is made of pure chromium, the contact resistance is reduced when contacting the pixel electrode 250.

In addition, the gate line GL and the data line DL also have a triple layer structure. That is, the gate line GL and the data line DL are made of aluminum neodymium, chromium, and chromium nitride.

A gate electrode pad 260 extending from the gate line GL and having a width wider than the gate line GL is formed in the first peripheral area PA1. The gate electrode pad 260 includes a first gate electrode pad layer 260a, a second gate electrode pad layer 260b, and a third gate electrode pad layer 260c. The second gate electrode pad layer 260b is stacked on the first gate electrode pad layer 260a, and the third gate electrode pad layer 260c is stacked on the second gate electrode pad layer 260b.

In this case, the gate electrode pad 260 is formed of the same material in the same process when forming the gate electrode 221. Accordingly, the first gate electrode pad layer 260a is made of aluminum neodymium, the second gate electrode pad layer 260b is made of chromium, and the third gate electrode pad layer 260c is made of chromium nitride.

In addition, a first via hole 265 partially exposing the gate electrode pad 260 is formed in the first peripheral area PA1. The first via hole 265 is formed by partially removing the gate insulating layer 223, the passivation layer 230, the organic insulating layer 240, and the third gate electrode pad layer 260c on the gate electrode pad 260.

A first transparent electrode 270 is formed on the gate electrode pad 260 to be electrically connected to the gate electrode pad 260 through the first via hole 265. The first transparent electrode 270 is formed of the same material in the same process when forming the pixel electrode 250. That is, the first transparent electrode 270 is made of ITO or IZO.

The first transparent electrode 270 is in direct contact with the second gate electrode pad layer 260b of the gate electrode pad 260 through the first via hole 265. In this case, since the second gate electrode pad layer 260b is made of pure chromium, the contact resistance between the first transparent electrode 270 and the second gate electrode pad layer 260b is reduced.

A data electrode pad 280 extending from the data line DL and having a width wider than that of the data line DL is formed in the second peripheral area PA2. The data electrode pad 280 includes a first data electrode pad layer 280a, a second data electrode pad layer 280b, and a third data electrode pad layer 280c. The second data electrode pad layer 280b is stacked on the first data electrode pad layer 280a, and the third data electrode pad layer 280c is stacked on the second data electrode pad layer 280b.

In this case, the data electrode pad 280 is formed of the same material in the same process when forming the source electrode 225 and the drain electrode 226. Therefore, the first data electrode pad layer 280a is made of aluminum neodymium, the second data electrode pad layer 280b is made of chromium, and the third data electrode pad layer 280c is made of chromium nitride.

In addition, a second via hole 285 partially exposing the data electrode pad 280 is formed in the second peripheral area PA2. The second via hole 285 is formed by partially removing the passivation layer 230, the organic insulating layer 240, and the third data electrode pad layer 280c on the data electrode pad 280.

A second transparent electrode 290 is formed on the data electrode pad 280 to be electrically connected to the data electrode pad 280 through the second via hole 285. The first transparent electrode 290 is formed of the same material in the same process when forming the pixel electrode 250. That is, the second transparent electrode 270 is made of ITO or IZO.

The second transparent electrode 290 is in direct contact with the second data electrode pad layer 280b of the data electrode pad 280 through the second via hole 285. In this case, since the second data electrode pad layer 280b is made of pure chromium, the contact resistance between the second transparent electrode 290 and the second data electrode pad layer 280b is reduced.

The gate electrode pad 260 and the data electrode pad 280 having the above-described configuration are electrically connected to the flexible printed circuit board (not shown) through an anisotropic conductive film (ACF) (not shown). Accordingly, the gate electrode pad 260 and the data electrode pad 280 output the gate signal and the data signal input from the flexible printed circuit board to the gate line GL and the data line DL, respectively.

The color filter substrate 300 includes a light blocking film 320, a color filter 330, and a common electrode 340 formed on the second insulating substrate 310. The color filter 330 is formed of R, G, and B pixels, and the light shielding film 320 is formed in a matrix form between the R, G, and B pixels to form the matrix between the R, G, and B pixels. It prevents light from leaking. In addition, the common electrode 340 is an electrode facing the pixel electrode 250 formed on the array substrate 200.

In the present invention, the gate electrode 221, the source electrode 225, the drain electrode 226, the gate electrode pad 260, and the data electrode pad 280 are formed in a triple layer structure by a reactive sputtering method. can do. In addition, the present invention is a triple layer structure of the gate electrode 221, the source electrode 225, the drain electrode 226, the gate electrode pad 260 and the data electrode pad 280 by nitriding treatment using plasma chemical vapor deposition. It can be formed as.

4A through 4G are cross-sectional views illustrating a process of manufacturing the array substrate illustrated in FIG. 2. FIG. 5 illustrates a reactive sputtering apparatus for forming the third metal film illustrated in FIG. 4B, and FIG. 6 illustrates a plasma chemical vapor deposition apparatus for forming the third metal film illustrated in FIG. 4B.

Referring to FIG. 4A, the first metal film 500 is formed on the entire surface of the first insulating substrate 210 by a sputtering method or a chemical vapor deposition method targeting aluminum neodymium. The first metal film 500 is formed in the display area DA and the first and second peripheral areas PA1 and PA2 of the first insulating substrate 210.

As shown in FIG. 4B, a second metal film 510 made of chromium is formed on the entire surface of the first insulating substrate 210 on which the first metal film 500 is formed. The second metal film 210 is formed by a sputtering method using chromium as a target. In addition, the second metal film 510 is formed in the display area DA and the first and second peripheral areas PA1 and PA2 on the first insulating substrate 210.

Subsequently, a third metal film 520 made of chromium nitride is formed on the entire surface of the first insulating substrate 210 on which the second metal film 510 is formed. The third metal film 520 is formed by a reactive sputtering method using nitrogen gas (N 2) or by a plasma chemical image deposition method using nitrogen gas and ammonia gas (NH 3). In this case, the second metal film 510 and the third metal film 520 are formed in the same chamber.

As shown in FIG. 5, the reactive sputtering apparatus 600 includes a chamber for treating the first insulating substrate 210 using argon (Ar) gas for sputtering and nitrogen (N 2) gas for nitriding. 610). The chamber 610 is provided with a chuck 620 on which the first insulating substrate 210 is placed and a metal target 630 made of chromium (Cr). In general, a negative voltage provided through the power supply unit 640 is applied to the metal target 630.

The reactive sputtering apparatus 600 further includes a gas supply unit 650 for uniformly providing a gas for processing the first insulating substrate 210 in the chamber 610. Argon gas is injected into the chamber 610 through the gas supply part 650. At this time, the chamber 610 is in a vacuum state.

Subsequently, when a negative voltage is applied to the metal target 630, secondary electrons having the same energy as the voltage applied to the metal target 630 are emitted to the surface of the metal target 630. The secondary electrons strike the argon gas in the chamber 610, whereby the argon gas impinges on the metal target 630.

When the impact energy applied to the metal target 630 is greater than the binding energy between metal atoms, atoms on the surface of the metal target 630 are separated. The separated atoms are sputtered on the first metal film 500 on the first insulating substrate 210, and the sputtered atoms are bonded to each other to form a thin film. As a result, a second metal film 520 made of chromium is formed on the first metal film 500.

Subsequently, when the argon gas and the nitrogen gas are injected into the chamber 610 through the gas supply unit 650, and a negative voltage is applied to the metal target 630, a secondary having the same energy as the voltage applied to the metal target 630. Electrons come out of the surface of the metal target 630. The secondary electrons strike the argon gas in the chamber 610, whereby the argon gas impinges on the metal target 630.

Atoms on the surface of the metal target 630 are separated by the impact energy applied to the metal target 630, and the separated atoms are combined with nitrogen gas to form a second metal film on the first insulating substrate 210. Sputtered on 510. The atoms sputtered on the second metal layer 510 are bonded to each other to form a thin film. As a result, a third metal film 520 made of chromium nitride is deposited on the second metal film 510 of the first insulating substrate 210.

Here, chromium nitride containing nitrogen ions may be formed only in the upper region on the second metal film 510 by adjusting the amount of nitrogen gas and the injection time of the nitrogen gas injected into the chamber 610.

Meanwhile, as shown in FIG. 6, the plasma chemical vapor deposition apparatus 700 includes a chamber 710 for processing the first insulating substrate 210 using plasma. The chamber 710 is provided with a chuck 720 and a metal target 730 on which the first insulating substrate 210 is placed. The metal target 730 serves as an electrode to which power is applied to form the injected gas into the plasma. In general, a high voltage DC voltage provided through the power supply unit 740 is applied to the metal target 730.

The plasma chemical vapor deposition apparatus 700 further includes a gas supply unit 750 for uniformly providing a gas for processing the first insulating substrate 210 in the chamber 710. Nitrogen gas or ammonia gas is injected into the chamber 710 through the gas supply unit 750, or nitrogen gas and ammonia gas are simultaneously injected.

First, ammonia gas is injected into the chamber 710 through the gas supply unit 750, and the plasma is discharged from the discharge space 760 on the first metal film 500 on the first insulating substrate 210. 2 metal film 510 is formed.

Subsequently, when nitrogen gas is further injected into the chamber 710 through the gas supply unit 750, and the nitrogen gas and the ammonia gas are activated in the plasma state through the plasma discharge generated in the discharge space 760, the first insulating substrate 210 is formed. Nitriding treatment is performed in which nitrogen ions penetrate into the second metal film 510. As a result, a third metal layer 530 made of chromium nitride is deposited on the second metal layer 510.

As described above, since the second metal film 510 and the third metal film 520 are formed in the same chambers 610 and 710, the third metal film 510 is not in contact with the air. The metal film 520 is deposited. Therefore, the second metal film 510 is made of pure chromium.

As shown in FIG. 4C, the photoresist 535 is deposited on the entire surface of the first insulating substrate 210 on which the first to third metal layers 500, 510, and 520 are deposited, and then exposed using a predetermined mask. Subsequently, the second and third metal layers 510 and 520 are simultaneously etched by the first etchant. Accordingly, the third gate electrode layer 221c and the second gate electrode layer 221b are formed in the display area DA of the first insulating substrate 210, and the third gate electrode pad layer is formed in the first peripheral area PA1. 270c and a second gate electrode pad layer 270b are formed.

Here, a baking process for curing the photoresist 535 is performed after the exposure process.

Referring to FIG. 4D, after etching the first metal film 500 using the second etchant, the photoresist 535 is removed. As a result, the gate electrode 221 including the first to third gate electrode layers 221a, 221b, and 221c is formed in the display area DA of the first insulating substrate 210. In addition, a gate electrode pad 270 including first to third gate electrode pad layers 270a, 270b, and 270c is formed in the first peripheral area PA1 of the first insulating substrate 210.

In this case, the first metal layer 500 forming the first gate electrode layer 221a and the first gate electrode pad layer 270a may have an under cut in which lower regions of the first metal substrate 500 that are in contact with the first insulating substrate 210 are relatively etched. This does not happen. Therefore, the gate electrode 221 and the gate electrode pad 270 have a tapered shape at both ends of the cut surface cut in the direction perpendicular to the first insulating substrate 210.

After the etching process of the second and third metal layers 510 and 520 by the first etchant, a baking process for curing the photoresist 535 is performed.

Referring to FIG. 4E, a gate insulating layer 223 made of silicon nitride (SiNx) is formed on the first insulating substrate 210 on which the gate electrode 221 and the gate electrode pad 270 are formed.

Next, an active layer 224 is formed on the gate insulating layer 223 on which the gate electrode 221 is formed. That is, the semiconductor layer 224a and the ohmic contact layer 224b are sequentially formed on the gate insulating layer 223.

The fourth metal film 530, the fifth metal film 540, and the sixth metal film 550 are sequentially formed on the first insulating substrate 210 on which the active layer 224 is formed. The fourth metal film 530 and the fifth metal film 540 are formed by a sputtering method or a chemical vapor deposition method. In addition, the sixth metal film 550 is formed by the reactive sputtering apparatus 600 illustrated in FIG. 5 or by the plasma chemical vapor deposition apparatus 700 illustrated in FIG. 6. The fifth and sixth metal films 540 and 550 are formed in the same chamber. The fourth metal film 530 is made of aluminum neodymium, the fifth metal film 540 is made of chromium, and the sixth metal film 550 is made of chromium nitride.

As shown in FIG. 4F, the first insulating substrate 210 on which the fourth to sixth metal layers 530, 540, and 550 are formed is exposed using a predetermined mask, and then fifth and sixth using the first etchant. The metal films 540 and 550 are simultaneously etched. Subsequently, the fourth metal film 530 is etched using the second etchant. As a result, the source electrode 225 and the drain electrode 226 are formed in the display area DA of the first insulating substrate 210, and the data electrode pad 280 is formed in the second peripheral area PA2.

The source electrode 225 includes a first source electrode layer 225a, a second source electrode layer 225b, and a third source electrode layer 225c, and the drain electrode 226 includes the first drain electrode layer 226a and the second. A drain electrode layer 226b and a third drain electrode layer 226c are included. In addition, the data electrode pad 280 includes a first data electrode pad layer 280a, a second data electrode pad layer 280b, and a third data electrode pad layer 280c.

At this time, the fourth metal layer 230 forming the first source electrode layer 225a, the first drain electrode layer 226a, and the first data electrode pad layer 280a may have an undercut in which lower regions are relatively etched. Does not occur. Accordingly, the source electrode 225, the drain electrode 226, and the data electrode pad 280 have a tapered shape at both ends of the cut surface cut in the direction perpendicular to the first insulating substrate 210.

Next, the passivation layer 230 is formed on the entire surface of the first insulating substrate 210 on which the source electrode 225, the drain electrode 226, and the data electrode pad 280 are formed. At this time, the protective film 230 is made of a silicon nitride film. In addition, the organic insulating layer 240 is formed on the entire surface of the first insulating substrate 210 on which the passivation layer 230 is formed.

Referring to FIG. 4G, a first hole is formed on the first insulating substrate 210 corresponding to the contact hole 245 and the first peripheral area PA1 on the first insulating substrate 210 corresponding to the display area DA. The via hole 265 is formed, and the second via hole 265 is formed on the first insulating substrate 210 corresponding to the second peripheral area PA2.

In other words, a portion of the gate drain layer 223, the passivation layer 230, the organic layer 240, and the third drain electrode layer 226c of the display area DA is removed to expose a portion of the second drain electrode layer 226b. The hole 245 is formed. In addition, a portion of the gate insulating layer 223, the passivation layer 230, the organic insulating layer 240, and the third gate electrode pad layer 260c of the first peripheral area PA1 is removed to form the second gate electrode pad layer 260b. A first via hole 265 is formed to expose a portion of the first via hole 265. A second portion exposing a portion of the second data electrode pad layer 280b by removing a portion of the passivation layer 230, the organic insulating layer 240, and the third data electrode pad layer 280c of the second peripheral area PA2. Via holes 285 are formed.

Referring to FIG. 4H, the pixel electrode 250 made of ITO or IZO, and first and second transparent electrodes 270 and 290 are formed on the organic insulating layer 240. The pixel electrode 250 is formed to correspond to the display area DA of the first insulating substrate 210 and is electrically connected to the drain electrode 226 through the contact hole 245.

In this case, the pixel electrode 250 is in direct contact with the second drain electrode layer 226b made of chromium. Therefore, as the pixel electrode 250 contacts the second drain electrode layer 226b, the contact resistance between the pixel electrode 250 and the drain electrode 226 decreases.

In addition, the first transparent electrode 270 is formed to correspond to the first peripheral area PA1 of the first insulating substrate 210 and is electrically connected to the gate electrode pad 260 through the first via hole 265. In this case, the first transparent electrode 270 is in direct contact with the second gate electrode pad layer 260b made of pure chromium. Therefore, as the first transparent electrode 270 contacts the second gate electrode pad layer 260b, the contact resistance between the first transparent electrode 270 and the gate electrode pad 260 decreases.

The second transparent electrode 290 is formed to correspond to the second peripheral area PA2 of the first insulating substrate 210 and is electrically connected to the data electrode pad 280 through the second via hole 285. In this case, the second transparent electrode 290 is in direct contact with the second data electrode pad layer 280b made of pure chromium. Therefore, as the second transparent electrode 290 contacts the second data electrode pad layer 280b, the contact resistance between the second transparent electrode 290 and the data electrode pad 280 decreases.

7 is an exploded perspective view showing a liquid crystal display device having a liquid crystal display panel according to the present embodiment.

As shown in FIG. 7, the liquid crystal display according to the present invention includes a display unit 800 and a backlight assembly 900 formed under the display unit 800.

The display unit 800 includes a liquid crystal display panel 100 displaying an image, a source printed circuit board 810 and a gate printed circuit board 820 providing a driving signal for driving the liquid crystal display panel 100. Include.

The driving signals provided from the source printed circuit board 810 and the gate printed circuit board 820 are applied to the liquid crystal display panel 100 through the data flexible circuit film 830 and the gate flexible circuit film 840. The data and gate flexible circuit films 830 and 840 may include, for example, a tape carrier package (TCP) or a chip on film (COF). Here, the data and gate flexible circuit films 830 and 840 may be configured to apply driving signals provided from the source printed circuit board 810 and the gate printed circuit board 820 to the liquid crystal display panel 100 at an appropriate timing. A data driving chip 850 and a gate driving chip 860 for controlling timing are further included.

Since the liquid crystal display panel 100 is the same as the liquid crystal display panel illustrated in FIGS. 1 and 2, the same reference numerals are used, and overlapping descriptions are omitted.

Meanwhile, the backlight assembly 900 may include a lamp unit 910 that generates the light, a light guide plate 920 that guides the light path to the liquid crystal display panel 100, and a lamp unit 910 and the light guide plate 920. A storage container 930 for storing is provided.

In addition, the backlight assembly 900 is formed on the light guide plate 920 to improve the optical characteristics of the light provided from the light guide plate 920 and light formed under the light guide plate 920 and leaked from the light guide plate 920. It further includes a reflecting plate 950 for reflecting to the display unit 800 side.

When the reflecting plate 950 is accommodated in the storage container 930, the light guide plate 920 and the lamp unit 910 are stored thereon. Thereafter, the optical sheets 940 are accommodated on the light guide plate 920, and the liquid crystal display panel 100 is seated thereon. The source printed circuit board 810 is bent to the outside of the storage container 930 and fixed to the rear surface.

An upper portion of the liquid crystal display panel 100 is provided with a chassis 960 which is coupled to the storage container 930 so as to fix the liquid crystal display panel 100 to the storage container 930.

According to the liquid crystal display device, under-cutting is prevented when the gate electrode 221, the source electrode 225, the drain electrode 226, the gate electrode pad 260, and the data electrode pad 280 are formed. Can be. In addition, as the pure chromium is directly in contact with the pixel electrode or the transparent electrode, the contact resistance can be reduced.

As described above, the present invention has a gate electrode, a source electrode, a drain electrode, a gate electrode pad, and a data electrode pad having a triple layer structure in which metal films made of aluminum neodymium, chromium, and chromium nitride are sequentially stacked.

Therefore, when the electrodes and the pad are formed, a metal film made of aluminum neodymium is first formed and then chromium and chromium nitride are formed, so that under-cutting does not occur during patterning.

Therefore, the present invention can prevent the local charge traffic phenomenon as the under-cut occurrence is prevented, so that a failure in the form of a horizontal line is prevented. For this reason, the display quality of a liquid crystal display device can be improved.

In addition, since the present invention contacts the pure chromium film when the pixel electrode and the drain electrode contact, the transparent electrode and the gate electrode pad or the data electrode pad contact, the contact resistance is reduced. Therefore, the fall of display quality by contact resistance can be prevented.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (36)

A substrate having a display area and a peripheral area formed around the display area; And And a gate electrode, a source electrode, and a drain electrode formed in the display area, and the gate electrode is formed through nitriding treatment of a first metal film, a second metal film stacked on the first metal film, and the second metal film. And a switching element having a third metal film formed on the second metal film. The method of claim 1, wherein the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx). Array substrate. The semiconductor device of claim 1, further comprising a first metal film, a second metal film stacked on the first metal film, and a second metal film stacked on the first metal film. An electrode pad having a third metal film; An insulating film formed on the electrode pad; And And a transparent electrode formed on the insulating film and electrically connected to the second metal film of the electrode pad through via holes formed in the insulating film and the third metal film. The array substrate of claim 3, wherein the electrode pad is a gate electrode pad that provides a gate signal to the switching device. The array substrate of claim 1, wherein the gate electrode has a tapered shape of at least one cut surface. The semiconductor device of claim 1, wherein the source electrode or the drain electrode includes the first metal film, the second metal film stacked on the first metal film, and the third metal film stacked on the second metal film. Array substrate, characterized in that made. The method of claim 6, wherein the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx). Array substrate. The semiconductor device of claim 6, further comprising: an insulating film formed on the switching element; And And a pixel electrode formed on the insulating layer and electrically connected to the switching element through a contact hole formed in the insulating layer and the third metal layer. The semiconductor device of claim 6, wherein the second metal film and the second metal film are formed on the first metal film, the first metal film, and the second metal film. An electrode pad having the third metal film laminated thereon; An insulating film formed on the electrode pad; And And a transparent electrode formed on the insulating film and electrically connected to the second metal film of the electrode pad through via holes formed in the insulating film and the third metal film. The array substrate of claim 9, wherein the electrode pad is a data electrode pad that provides a data signal to the switching element. The array substrate of claim 6, wherein at least one cut surface of the source electrode or the drain electrode has a tapered shape. A substrate having a display area and a peripheral area formed around the display area; A switching element formed in the display area and having a first electrode, a second electrode, and a third electrode; The first metal film extends from one of the first to third electrodes and is formed in the peripheral region, and is nitrided through the first metal film, the second metal film stacked on the first metal film, and the second metal film. An electrode pad having a third metal film formed on the second metal film; An insulating film formed on the electrode pad; And And a transparent electrode formed on the insulating film and electrically connected to the second metal film through via holes formed in the insulating film and the third metal film. The array substrate of claim 12, wherein at least one of the first to third electrodes of the switching element is formed of the first to third metal films sequentially stacked. The array substrate of claim 12, wherein the first metal film is made of aluminum neodymium film, the second metal film is made of chromium film, and the third metal film is made of chromium nitride. The array substrate of claim 12, wherein the cut surface of the electrode pad has a tapered shape. A substrate having a display area and a peripheral area formed around the display area; A second metal layer formed on the display area, the first electrode, a second electrode, and a third electrode, wherein at least one of the first to third electrodes is a first metal layer and a second metal layer stacked on the first metal layer And a third metal film formed on the second metal film through nitriding of the second metal film. The first metal film extends from one of the first to third electrodes and is formed in the peripheral area, and is stacked on the first metal film, the second metal film, and the third metal film stacked on the first metal film. An electrode pad having a third metal film; An insulating film formed on an entire surface of the substrate on which the switching element and the electrode pad are formed; A first transparent electrode formed on the insulating film and electrically connected to the second metal film of the switching element through a contact hole formed in the insulating film and the third metal film of the first to third electrodes; And And a second transparent electrode formed on the insulating film and electrically connected to the second metal film of the electrode pad through a via hole formed in the insulating film and the third metal film of the electrode pad. The method of claim 16, wherein the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx). Array substrate. Board; A first metal film on the substrate, a second metal film stacked on the first metal film, and a second metal film stacked on the second metal film and formed on the second metal film through nitriding treatment of the second metal film. A first signal line consisting of three metal films; An insulating layer formed on the first signal line; And And a second signal line formed to intersect the first signal line. 19. The array substrate of claim 18, wherein the second signal line comprises the first to third metal layers sequentially stacked. The method of claim 18, A switching element comprising a first electrode, a second electrode, and a third electrode electrically connected to the first and second signal lines; Further comprising a pixel electrode electrically connected to the switching element, At least one of the first to third electrodes is formed of the first to third metal films sequentially stacked, And the pixel electrode is electrically connected to a second metal film of the switching element through a contact hole formed in the insulating film and the third metal film. The method of claim 18, An electrode pad extending from one of the first and second signal lines and formed of the first to third metal layers sequentially stacked; And And a transparent electrode formed on the insulating film and electrically connected to the second metal film of the electrode pad through a via hole formed in the insulating film and the third metal film of the electrode pad. 19. The method of claim 18, wherein the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx). Array substrate. A second metal film having a first electrode, a second electrode, and a third electrode in a display area on a substrate, wherein at least one of the first to third electrodes is stacked on the first metal film, the first metal film, and the Forming a switching element made of a third metal film formed on the second metal film by nitriding a second metal film; Forming an insulating film on the substrate on which the switching element is formed; And And forming a pixel electrode on the insulating layer, the pixel electrode electrically connected to the second metal layer of the switching element through a contact hole formed in the insulating layer and the third electrode of the switching element. 24. The method of claim 23, wherein the first metal film is made of aluminum neodymium, the second metal film is made of chromium, and the third metal film is made of chromium nitride. The method of claim 23, wherein forming the switching device Forming the first metal film on the entire surface of the substrate in a first chamber; Forming the second metal film on an entire surface of the substrate on which the first metal film is formed in a second chamber; And Injecting nitriding gas into the second chamber to form the third metal film on the second metal film; And And patterning the first to third metal films to form the first to third electrodes. The method of claim 25, wherein forming the first to third electrodes Simultaneously patterning the second metal film and the third metal film; And And patterning the first metal layer. 26. The method of claim 25, wherein the second chamber is in a vacuum plasma state. 24. The method of claim 23, further comprising forming the contact hole exposing a portion of the second metal film by simultaneously removing the insulating film and the third metal film. 29. The method of claim 28, wherein the third metal film is etched by the same etching solution as the insulating film. The method of claim 23, wherein Forming an electrode pad formed of the first to third metal layers sequentially extending from one of the first to third electrodes and sequentially stacked in a peripheral area in contact with the display area; And And forming a transparent electrode electrically connected to the second metal film of the electrode pad through a via hole formed in the insulating film and the third metal film of the electrode pad. 31. The method of claim 30, further comprising forming the via hole exposing the second metal film of the electrode pad by simultaneously etching the insulating film and the third metal film of the electrode pad. A substrate having a display area and a peripheral area formed around the display area; A first electrode, a second electrode, and a third electrode, wherein the at least one of the first to third electrodes is stacked on the first metal film and the first metal film; A switching element made of a second metal film which is nitrided to include nitrogen ions therein; And And a pixel electrode electrically connected to one of the first to third electrodes of the switching element. 33. The array substrate of claim 32, wherein the first metal film is made of aluminum neodymium, and the second metal film is made of chromium. The method of claim 32, An electrode pad extending from one of the first to third electrodes and formed in the peripheral region, the electrode pad including the first metal film and the second metal film stacked on the first metal film; And And a transparent electrode formed on the electrode pad and electrically connected to the electrode pad. An upper substrate having a first transparent electrode; A first electrode, a second electrode, and a third electrode facing the upper substrate, wherein at least one of the first to third electrodes is subjected to nitriding treatment of the first metal film, the second metal film, and the second metal film; A switching device having a third metal film formed on the second metal film, an insulating film formed on the switching device, and a contact hole formed in the insulating film and the third metal film of the switching device so as to face the first transparent electrode. A second transparent electrode electrically connected to the second metal film of the switching element and extending from one of the first to third electrodes through the first metal film, the second metal film, and the An electrode pad having a third metal film; and a third transparent electrode electrically connected to the second metal film of the electrode pad through a via hole formed in the insulating film and the third metal film of the electrode pad. This substrate; And And a liquid crystal layer formed between the upper substrate and the array substrate. 36. The method of claim 35, wherein the first metal film is made of aluminum neodymium (AlNd), the second metal film is made of chromium (Cr), and the third metal film is made of chromium nitride (CrNx). Display.

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