KR20070010595A - Synchronized serial data bus apparatus for the pcb and the method thereof - Google Patents

Abstract

A synchronized serial data bus device in a PCB(Printed Circuit Board) and a data transfer method thereof are provided to enable diverse devices to perform data communication with a single data bus structure by having a synchronized data/clock/address bus, and making a master device offer a synchronized clock to each device and control a data transfer rate of each device. A master device(M) controls the data communication among slave devices(S1,S2) by assigning an address of the slave devices and offering the synchronized clock. A synchronized address bus(103) transfers an address appointing the slave device and data location information for the data communication. The synchronized sync data bus(101) transfers the data for the data communication. The synchronized clock bus(102) supplies the synchronized clock generated in the master device. The synchronized data bus comprises I data bus and Q data bus for IQ data transfer.

Description

Synchronized serial data bus apparatus for the board and the method

1 is a block diagram of a mobile communication terminal to which the I2C method is applied as a synchronous serial data bus method according to the related art.

2 is a view showing the structure of the on-board synchronous serial data bus device of the present invention,

3 is a view showing a data transmission format by the on-board synchronous serial data bus device of the present invention;

4 is a flowchart illustrating a detailed process of the on-board synchronous serial data transmission method of the present invention.

5 is a block diagram of a mobile communication terminal to which an embodiment of the on-board synchronous serial data bus device of the present invention is applied;

FIG. 6 is a diagram illustrating a data format transmitted from the synchronous serial data bus device of FIG. 5.

* Description of Major Symbols in Drawings *

1, 110: MSM

2: I2C clock port (I2C_SCLP: Inter Integrated Circuit Serial clock Port)

3: I2C data port (I2C_SDAP: Inter Integrated Circuit Serial data Port)

4: Data port (DATAP) 5: Clock port (CLKP)

10: I2C bus

11: I2C_SCL: Inter Integrated Circuit Serial clock bus

12: I2C_SDA: Inter Integrated Circuit Serial data bus

20: databus

21: data bus 22: clock bus

100, 120: on-board synchronous serial databus

101: General Control Data bus (GCDB)

104, 104 ': Synchronous Data Port (GCD_P: General Control Data Port)

M: master device

S1: slave1 (slave device 1)

S2: slave2 (slave device 2)

111: I data port (GCD_IP: General Control Data In_phase Port)

112: Q data port (GCD_QP: General Control Data Quad_phase Port)

105, 105 ', 113: Synchronous Clock Port (GCC_P: General Control Clock Port)

106, 106 ', 114: Synchronous address port (GCA_P)

121: I data bus (GCD_IB: General Control Data In_phase bus)

122: Q data bus (GCD_QB: General Control Data Quad_phase bus)

102, 123: General Control Clock bus (GCCB)

103, 124: General Control Address bus (GCAB)

30, 130: Power Management IC (PMIC)

40, 140: Charge Pump (CP)

50, 150: camera unit

60, 160: user information module (UIM)

70, 170: Multi Media Card (MMC)

The present invention relates to a bus for transmitting data in a synchronous serial manner in an electronic device, and more particularly, to an on-board synchronous serial data bus apparatus having a data, clock, and address signal line.

In general, an I2C (Inter Integrated Circuit) method using a synchronous data serial transmission method is used for data and clock transmission in a PCB.

The I2C described above was proposed by Philips as a serial communication protocol for connecting ICs and other electronic systems that transmit data at a relatively low data rate in a board.

The structure of the I2C bus is composed of an I2C-SDA (serial data) bus used for data transmission and an I2C-SCL (serial clock) bus used for clock signal transmission. In addition, at least one master device and a plurality of slave devices, which generate a clock on two buses and allocate addresses of the devices to control synchronous serial data transmission between the devices, are connected. In addition, the slaves perform data communication in synchronization with a clock generated by the master, and a general data transfer rate is 100K bits / second in the classic mode and up to 400K bits / second in the fast mode. In case of High Speed Mode, the maximum transmission speed is 3.4M bits / second.

Various serial devices such as microcontrollers, EEPROMs, real-timers, interface chips, LCD drivers, and A / D converters can be attached to the I2C bus.

The I2C bus as described above enables the close installation of digitally controlled components at their point of use and enables the use of smaller packages of ICs by reducing the number of pins for connecting each device device. . Therefore, it is possible to significantly reduce the complexity of the board by reducing the number of signal lines for connecting each device in the board, and has a feature that can reduce the manufacturing cost of the board.

1 is a block diagram of a mobile communication terminal to which the above-described I2C bus of the related art is applied.

As shown in FIG. 1, the MSM 1 of the prior art has an I2C clock port (hereinafter referred to as "I2C_SCLP") 2 and an I2C data port (hereinafter referred to as "I2C_SDAP") for I2C data communication. And a data port 4 and a clock port 5 using a data rate and clock other than the I2C method.

Power management IC (PMIC) 30, charge pump (CP) 40, camera unit 50, etc., which transmit and receive relatively low-speed data, are connected to the I2C bus of the MSM 1 A user identification module (UIM) 60 having a different clock and data rate than the I2C, and a multimedia card (MMC) (70). Is connected to the data port 4 and the clock port 5 to receive a clock and perform data communication with other devices of the mobile communication terminal.

In the above-described configuration, the MMS 1 provides a clock for the I2C devices, assigns addresses to the devices, and operates as a master device that controls data transmission by the I2C bus. A control IC (PMIC: Power Management IC) 30, a charge pump (CP) 40, and the camera unit 50 are controlled. In addition, the MSM 1 supplies a clock different from the I2C to the UIM 60 and the MMC 70 using a different clock and data transmission frequency than the I 2 C through the separate data port 4 and the clock port 5. Control the transmission and reception of data.

However, the prior art I2C as described above provides data synchronous serial data communication for devices having relatively low data rates, and does not support data communication for devices having a clock and data rates different from those of I2C. Therefore, for devices having a different clock and data rate than I2C, a separate clock and data port must be provided in a control unit such as an MSM.

In addition, since the board needs to add a separate line for the synchronous clock and data transmission through the clock and data ports added to the control unit such as MSM, it is difficult to design the device and the board and develop the software for the control thereof. Has

In addition, there is a problem that can not vary the clock and data rate of the devices.

Accordingly, the present invention is to solve the above-mentioned problems in the prior art, and has a synchronous data bus, a synchronous clock bus, and a synchronous address bus, wherein the master device provides a synchronous clock to each device and also provides a data rate of each device. The purpose of the present invention is to provide an on-board serial data bus device and a method of transmitting the same so that various devices can perform data communication using a single data bus structure.

An onboard synchronous serial data bus apparatus of the present invention for achieving the above object comprises: a master device for addressing slave devices and providing a synchronous clock to control data communication of the slave devices; A synchronous address bus for transmitting an address and data position information designating a slave device for the data communication; A synchronous data bus for transmitting data for the data communication; And a synchronous clock bus for supplying a synchronous clock generated by the master device.

The synchronous data bus is characterized by consisting of an I data bus and a Q data bus for IQ data transmission.

The master device includes a synchronous address port connected to the synchronous address bus; A synchronous data port connected to said synchronous data bus; And a synchronous clock port connected to the synchronous clock bus to output a synchronous clock.

The slave device includes a synchronous address port connected to the synchronous address bus; A synchronous data port connected to said synchronous data bus; It has a synchronous clock port for receiving the synchronous clock.

The synchronous data ports of the master device and the slave device are configured as I data port and Q data port for IQ data transmission.

In-board synchronous serial data transmission method of the present invention for achieving the above object, in the data transmission method of the synchronous serial data bus having a synchronous clock bus, synchronous data bus, synchronous address bus, by generating a reference synchronous clock A synchronous clock generation process provided by the synchronous clock bus; An addressing process of allocating address information after recognizing devices connected to the synchronous serial data bus; Synchronizes the clock of the synchronous clock bus to input and output destination address and data position information to the synchronous address bus, and inputs and outputs data using the destination address and data position information transmitted from the synchronous address bus to the synchronous data bus. Characterized in that the data communication process to perform.

The sync clock generation process may further include a sync clock variable process of varying the generated sync clock.

The addressing process may further include a data area allocation process of setting a data bit occupancy rate of the devices in a reference bit string transmitted from the data bus per one clock period of the synchronous clock. This allows each device to have a different data rate.

The data transmission process includes: a data transmission process of outputting data to the synchronous data bus in synchronization with the synchronous clock, and transmitting the destination address of the data and data position information in the synchronous data bus to the synchronous address bus; And a data receiving process for receiving data corresponding to the data position in the synchronous data bus after receiving the destination address of the data and the position information in the synchronous data bus to the synchronous address bus in synchronization with the synchronous clock. It features.

The above-described present invention further improves the data rate by further configuring an address data bus having address information of devices in a structure of an in-board synchronous serial data bus.

In addition, since the master device can vary the synchronous clock, and the data of each device transmitted to the synchronous data bus can be set to occupy a certain region of the reference bit string allocated in one clock period, serial data of devices having various data rates. Provide communication.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 is a view showing the structure of the on-board synchronous serial data bus device of the present invention.

As shown in Fig. 2, a synchronous data bus (General Control Data bus, hereinafter referred to as " GCDB ") 101, a synchronous clock bus (hereinafter referred to as " GCCB ") 102, synchronous address bus A synchronous serial data bus 100 having a General Control Address bus (hereinafter referred to as " GCAB ") 103 is disposed on the board PCB.

The synchronous data port (hereinafter referred to as "GCD_P") 104, the synchronous clock port (hereinafter referred to as "GCC_P") 105, the synchronous address port (General Control Address Port) GCD_P 104 for GCDB 101, GCC_P 105 for GCCB 105, and GCA_P 106 for GCAB 103, where the master device M has a " GCA_P " It is connected to the synchronous serial data bus 100.

The other slave devices (slave 1 (S1), slave 2 (S2), ...) also have GCD_P 104 ', GCC_P 105', GCA_P 106 ', respectively, and GCD_P 104'. Is connected to GCDB 101, GCC_P 105 'to GCCB 102, and GCA_P 106' to GCAB 103, to synchronous serial data bus 100.

In the above-described configuration, the master device M generates a synchronous clock for synchronous data communication of the slave devices and outputs them to the GCCB 102, and also assigns addresses to the slave devices in order to distinguish various devices, and transmits data. The address information and data location information are output to the GCAB 103 so that the slave device, which is a transmission / reception target of the time data, can be identified.

The slave devices (slave 1 (S1), slave 2 (S2), ...) receive a clock from the GCCB 102 and are synchronized with each other.

At the time of data transmission, the master device M and the slave devices (slave 1 (S1), slave 2 (S2),...) Are address information of the receiving device and data transmitted by the master device M and the slave devices. Position information is transmitted, and data is transmitted to the GCDB 101 in accordance with the synchronous clock.

When the data is received, the master device M and the slave devices (slave 1 (S1), slave 2 (S2), ...) read their address information and data position information from the GCAB 103 and then themselves. If the address of is assigned, the data location information transmitted together with the address information is read from the data transmitted to the GCAB 103, and the data to be transmitted to itself is read from the data transmitted to the GCDB 101.

For the above operation, the master device M has a function of storing and managing address information of devices therein and a memory storing address information. Then, the master device (M) and the slave devices compare the bit strings having the received address information with the bit strings allocated to them, and if the match is enabled, interprets the address information in the same manner as reading the data. It has a function to read and read its own data, which can be implemented in various ways in the prior art by a program embedded in each device, the detailed description thereof will be omitted.

3 is a diagram illustrating a data transmission format by the synchronous serial data bus apparatus of FIG. 2 described above.

As shown in FIG. 3, the synchronous serial data bus of FIG. 2 includes data, clocks, and addresses in units of reference bit strings (eg, 64-bit, 128-bit, ..., etc.) designated for signal processing. Send it.

That is, as shown in FIG. 3, data of devices located at specific positions in the reference bit string is transmitted to the GCDB 101, and a synchronous clock output from the master device M is transmitted to the GCCB 102. The GCAB 103 transmits the destination device address and location information of the corresponding data transmitted to the GCDB 101.

Each device is synchronized with a synchronous clock provided from the master device M, and performs data communication through the GCDB 101 through address information and data location information transmitted to the GCAB 103. In this case, the data rate may be variably controlled by controlling the occupancy rate of each device with respect to the reference bit string for data transmission. The synchronous clock may also be variably controlled by the master device (M).

4 is a flowchart illustrating a detailed process of the on-board synchronous serial data transmission method, which will be described in detail with reference to FIGS. 2 and 3.

First, the master device M performs a synchronous clock output process of generating a synchronous clock for data transmission and outputting it to the GCCB 102. In this case, the master clock M may vary according to the operating states of the devices.

After that, the master device M detects slave devices (slave 1 (S1), slave 2 (S2), etc.) connected to the synchronous serial data bus 100, specifies the addresses of the slave devices, and stores the address. Do this. In this process, the data area allocation process of allocating the data occupancy rate of each device in the reference bit string may be further performed. Accordingly, each of the devices may have a variable data rate even in a situation where the same clock is synchronized (S20).

Subsequently, the master device and the slave devices that require data communication synchronize the synchronization by the GCCB synchronization clock in the case of data transmission, uploading address and data location information of the target device to perform data communication with the GCAB 103. The data to be transmitted to the GCDB 101 is outputted. In the case of receiving data, the GCAB 103 is read from the data transmitted to the GCDB 101 in synchronization with the synchronous clock provided to the GCCB 103 after reading the address and data position information transmitted through the GCAB 103. In step S30, a data communication process for performing data communication is performed by reading data corresponding to the data position information transmitted in step S).

5 is a block diagram of a mobile communication terminal to which the on-board synchronous serial data bus device of the present invention is applied.

As shown in FIG. 5, it is assumed that a mobile communication terminal to which the present invention is applied transmits data as IQ data using a transmission method.

The synchronous serial data bus of the present invention includes an I data bus (General Control Data In_phase bus: hereinafter referred to as "GCD_IB") 121 that transmits I data in an I / Q data format in the board of the mobile communication terminal of FIG. General control clock bus which supplies a data bus consisting of a Q data bus (general control data quad_phase bus: hereinafter referred to as "GCD_QB") 122 and a synchronous clock supplied from the MSM 110. : &Quot; GCCB " (hereinafter referred to as " GCCB ") 123 and a synchronous address bus (hereinafter referred to as " GCAB ") 124 for transmitting address and data location information of the devices.

The MSM 110 then replaces the I data as the synchronous data port (GCD_P) of the present invention instead of the I2C_SDAP (2) for supplying data by the I2C scheme and the data port (3) for transmitting data in a different manner from the I2C. It has a port (General Control Data In-phase Port: hereinafter referred to as "GCD_IP") 111 and a Q data port (General Control Data Quad-phase Port: hereinafter referred to as "GCD_QP"). Synchronous clock port for supplying a synchronous clock instead of I2C_SCLP (3) for supplying and clock port 5 for supplying a clock for a device using a different clock than I2C (General Control Clock Port: hereinafter referred to as "GCC_P"). 113, and a synchronous address port (hereinafter referred to as "GCA_P") 114 for inputting and outputting address information for data communication by specifying addresses of devices.

In addition, other devices mounted on the board of the mobile communication terminal of FIG. 5, that is, a power management IC (hereinafter referred to as "PMIC") 130, a charge pump (hereinafter referred to as "CP") 140, the camera unit 150, the user information module (hereinafter referred to as "UIM") 160, the multimedia card (hereinafter referred to as "MMC") 170, and the MSM ( 110, GCD_IP 111 ′, GCD_IP 112 ′, GCC_P 113 ′, and GCA_P 114 ′ are provided.

The GCD_IP 111 of the MSM 110 and the other devices of the mobile communication terminal are connected to the GCD_IB 121, the GCD_IP 112 is assigned to the GCD_QB 122, the GCC_P 113 is assigned to the GCCB 123, and the GCA_P 114 is assigned. ) Is connected to the GCAB 124.

In the connected state as described above, the MSM 110 operates as a master device. That is, when the MSM 110 recognizes other devices connected to the synchronous serial data bus 120, a predetermined bit in a predetermined reference bit string (e.g., 64-bit, 128-bit, etc.) for data and synchronous transmission is provided. (Eg, 8-bit, 16-bit, etc.) to address each device. The GCC_P 113 supplies a synchronous clock for synchronous serial data communication of other devices.

FIG. 6 illustrates a data transmission format of the mobile communication terminal of FIG. 5, in which data is transmitted by the GCD_IB 121 for transmitting I data and the GCD_QB 122 for transmitting Q data. The transmitted data is transmitted using 64 bits per clock cycle as a reference bit string, so a total of 128 bits of data are transmitted.

In FIG. 6, the GCCB 123 represents one clock period of the synchronous clock, and the GCAB 124 represents a data bit string having an address and data position information of a data transmission target device.

The aforementioned mobile communication terminal of FIG. 5 has the data transmission format of FIG. 6 and performs data data communication according to the processing procedure of FIG. 4.

As described above, when the present invention is applied, the GPIO (General Purpose Input / Output Pin) for the I2C method and the GPIO for other devices not using the I2C method in the MSM 110 are GCD_P, GCC_P, and GCA_P according to the present invention. By simplifying this, the structure of a device such as the MSM 110 is simplified. Accordingly, the data bus for other devices connected to the MSM 110 also has a single data bus structure consisting of GCDB, GCCB, and GCAB, thereby providing a data bus for connecting devices on a board (PCB) such as a mobile communication terminal. The structure is also simplified. In addition, since all devices are operated in synchronization by a synchronous clock output from a master device such as the MSM 110, it is easy to add another device.

In addition, the present invention described above further improves the transmission rate of data transmitted through the synchronous data bus by further configuring the address data bus having the address information of the devices in the structure of the on-board synchronous serial data bus.

In addition, since the master device can vary the synchronous clock, and the data of each device transmitted to the synchronous data bus can be set to occupy a certain region of the reference bit string allocated in one clock period, serial data of devices having various data rates. Can provide communication.

Accordingly, the present invention described above enables the in-board synchronous serial data communication to be performed by a single synchronous data bus structure, thereby significantly simplifying the structure of the board itself, and improving the structure of elements such as MSM, which is used as a master device. Simplification facilitates the design and manufacture of boards and board-mounted products, thereby reducing manufacturing costs.

In addition, the present invention described above can be controlled to have different data rates for each device using the same synchronous clock, so that a variety of devices can be selected and used to easily improve the performance of the product on which the board is mounted. It provides the effect of making it possible.

Claims (9)

A master device for addressing slave devices and providing a synchronous clock to control data communication of the slave devices; A synchronous address bus for transmitting an address and data position information designating a slave device for the data communication; A synchronous data bus for transmitting data for the data communication; And a synchronous clock bus for supplying a synchronous clock generated by the master device. The on-board synchronous serial data bus apparatus according to claim 1, wherein the synchronous data bus is composed of an I data bus and a Q data bus for IQ data transmission. The method of claim 1, wherein the master device, A synchronous address port connected to the synchronous address bus; A synchronous data port connected to said synchronous data bus; And a synchronous clock port connected to said synchronous clock bus and outputting a synchronous clock. The method of claim 1, wherein the slave device, A synchronous address port connected to the synchronous address bus; A synchronous data port connected to said synchronous data bus; And a synchronous clock port configured to receive the synchronous clock. 5. The on-board synchronous serial data bus apparatus as claimed in claim 3 or 4, wherein the synchronous data port is composed of an I data port and a Q data port. In a data transmission method of a synchronous serial data bus having a synchronous clock bus, a synchronous data bus, and a synchronous address bus, Generating a synchronous clock and providing the synchronous clock to the synchronous clock bus; An addressing process of allocating address information after recognizing devices connected to the synchronous serial data bus; Synchronizes the clock of the synchronous clock bus to input and output destination address and data position information to the synchronous address bus, and inputs and outputs data using the destination address and data position information transmitted from the synchronous address bus to the synchronous data bus. In-board synchronous serial data transmission method, characterized in that consisting of a data communication process for performing. 7. The method of claim 6, wherein the synchronizing clock generation process further comprises a synchronizing clock variable process of varying the synchronizing clock. The method of claim 6, wherein the addressing process, And a data area allocating step of setting the data bit occupancy ratio of the devices in a reference bit string transmitted from the data bus per one clock period of the synchronous clock. The method of claim 6, wherein the data transmission process, A data transmission process synchronized with the synchronous clock to output data to the synchronous data bus and to transmit the destination address of the data and data position information in the synchronous data bus to the synchronous address bus; And a data receiving process for receiving data corresponding to the data position in the synchronous data bus after receiving the destination address of the data and the position information in the synchronous data bus to the synchronous address bus in synchronization with the synchronous clock. On-board synchronous serial data transmission method.

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